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gerrit-public.fairphone.software / kernel / msm-4.9 / 6d698a83fa768be38780d54fc6c244c99cf7684d / . / sound / soc / codecs / max98088.c
blob: d326d66792bec7dc443f84ab9c9f506248dd544d [file] [log] [blame]
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1/*
2 * max98088.c -- MAX98088 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]18#include <linux/regmap.h>
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <linux/slab.h>
26#include <asm/div64.h>
27#include <sound/max98088.h>
28#include "max98088.h"
29
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]30enum max98088_type {
31 MAX98088,
32 MAX98089,
33};
34
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]35struct max98088_cdata {
36 unsigned int rate;
37 unsigned int fmt;
38 int eq_sel;
39};
40
41struct max98088_priv {
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]42 struct regmap *regmap;
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]43 enum max98088_type devtype;
44 struct max98088_pdata *pdata;
45 unsigned int sysclk;
46 struct max98088_cdata dai[2];
47 int eq_textcnt;
48 const char **eq_texts;
49 struct soc_enum eq_enum;
50 u8 ina_state;
51 u8 inb_state;
52 unsigned int ex_mode;
53 unsigned int digmic;
54 unsigned int mic1pre;
55 unsigned int mic2pre;
56 unsigned int extmic_mode;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]57};
58
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]59static const struct reg_default max98088_reg[] = {
60 { 0xf, 0x00 }, /* 0F interrupt enable */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]61
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]62 { 0x10, 0x00 }, /* 10 master clock */
63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */
64 { 0x12, 0x00 }, /* 12 DAI1 clock control */
65 { 0x13, 0x00 }, /* 13 DAI1 clock control */
66 { 0x14, 0x00 }, /* 14 DAI1 format */
67 { 0x15, 0x00 }, /* 15 DAI1 clock */
68 { 0x16, 0x00 }, /* 16 DAI1 config */
69 { 0x17, 0x00 }, /* 17 DAI1 TDM */
70 { 0x18, 0x00 }, /* 18 DAI1 filters */
71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */
72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */
73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */
74 { 0x1c, 0x00 }, /* 1C DAI2 format */
75 { 0x1d, 0x00 }, /* 1D DAI2 clock */
76 { 0x1e, 0x00 }, /* 1E DAI2 config */
77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]78
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]79 { 0x20, 0x00 }, /* 20 DAI2 filters */
80 { 0x21, 0x00 }, /* 21 data config */
81 { 0x22, 0x00 }, /* 22 DAC mixer */
82 { 0x23, 0x00 }, /* 23 left ADC mixer */
83 { 0x24, 0x00 }, /* 24 right ADC mixer */
84 { 0x25, 0x00 }, /* 25 left HP mixer */
85 { 0x26, 0x00 }, /* 26 right HP mixer */
86 { 0x27, 0x00 }, /* 27 HP control */
87 { 0x28, 0x00 }, /* 28 left REC mixer */
88 { 0x29, 0x00 }, /* 29 right REC mixer */
89 { 0x2a, 0x00 }, /* 2A REC control */
90 { 0x2b, 0x00 }, /* 2B left SPK mixer */
91 { 0x2c, 0x00 }, /* 2C right SPK mixer */
92 { 0x2d, 0x00 }, /* 2D SPK control */
93 { 0x2e, 0x00 }, /* 2E sidetone */
94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]95
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]96 { 0x30, 0x00 }, /* 30 DAI1 playback level */
97 { 0x31, 0x00 }, /* 31 DAI2 playback level */
98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
99 { 0x33, 0x00 }, /* 33 left ADC level */
100 { 0x34, 0x00 }, /* 34 right ADC level */
101 { 0x35, 0x00 }, /* 35 MIC1 level */
102 { 0x36, 0x00 }, /* 36 MIC2 level */
103 { 0x37, 0x00 }, /* 37 INA level */
104 { 0x38, 0x00 }, /* 38 INB level */
105 { 0x39, 0x00 }, /* 39 left HP volume */
106 { 0x3a, 0x00 }, /* 3A right HP volume */
107 { 0x3b, 0x00 }, /* 3B left REC volume */
108 { 0x3c, 0x00 }, /* 3C right REC volume */
109 { 0x3d, 0x00 }, /* 3D left SPK volume */
110 { 0x3e, 0x00 }, /* 3E right SPK volume */
111 { 0x3f, 0x00 }, /* 3F MIC config */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]112
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]113 { 0x40, 0x00 }, /* 40 MIC threshold */
114 { 0x41, 0x00 }, /* 41 excursion limiter filter */
115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */
116 { 0x43, 0x00 }, /* 43 ALC */
117 { 0x44, 0x00 }, /* 44 power limiter threshold */
118 { 0x45, 0x00 }, /* 45 power limiter config */
119 { 0x46, 0x00 }, /* 46 distortion limiter config */
120 { 0x47, 0x00 }, /* 47 audio input */
121 { 0x48, 0x00 }, /* 48 microphone */
122 { 0x49, 0x00 }, /* 49 level control */
123 { 0x4a, 0x00 }, /* 4A bypass switches */
124 { 0x4b, 0x00 }, /* 4B jack detect */
125 { 0x4c, 0x00 }, /* 4C input enable */
126 { 0x4d, 0x00 }, /* 4D output enable */
127 { 0x4e, 0xF0 }, /* 4E bias control */
128 { 0x4f, 0x00 }, /* 4F DAC power */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]129
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]130 { 0x50, 0x0F }, /* 50 DAC power */
131 { 0x51, 0x00 }, /* 51 system */
132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]146
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]163
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]180
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]197
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]214
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */
227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */
228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */
229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */
230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]231
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */
239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */
240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */
242 { 0xba, 0x00 }, /* BA DAI1 biquad */
243 { 0xbb, 0x00 }, /* BB DAI1 biquad */
244 { 0xbc, 0x00 }, /* BC DAI1 biquad */
245 { 0xbd, 0x00 }, /* BD DAI1 biquad */
246 { 0xbe, 0x00 }, /* BE DAI1 biquad */
247 { 0xbf, 0x00 }, /* BF DAI1 biquad */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]248
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */
250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */
251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */
252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */
253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */
254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */
255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */
256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */
257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */
258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]259};
260
261static struct {
262 int readable;
263 int writable;
264 int vol;
265} max98088_access[M98088_REG_CNT] = {
266 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */
267 { 0xFF, 0x00, 1 }, /* 01 MIC status */
268 { 0xFF, 0x00, 1 }, /* 02 jack status */
269 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */
270 { 0xFF, 0xFF, 0 }, /* 04 */
271 { 0xFF, 0xFF, 0 }, /* 05 */
272 { 0xFF, 0xFF, 0 }, /* 06 */
273 { 0xFF, 0xFF, 0 }, /* 07 */
274 { 0xFF, 0xFF, 0 }, /* 08 */
275 { 0xFF, 0xFF, 0 }, /* 09 */
276 { 0xFF, 0xFF, 0 }, /* 0A */
277 { 0xFF, 0xFF, 0 }, /* 0B */
278 { 0xFF, 0xFF, 0 }, /* 0C */
279 { 0xFF, 0xFF, 0 }, /* 0D */
280 { 0xFF, 0xFF, 0 }, /* 0E */
281 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */
282
283 { 0xFF, 0xFF, 0 }, /* 10 master clock */
284 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
285 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
286 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
287 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
288 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
289 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
290 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
291 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
292 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
293 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
294 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
295 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
296 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
297 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
298 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */
299
300 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
301 { 0xFF, 0xFF, 0 }, /* 21 data config */
302 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
303 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
304 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
305 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
306 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
307 { 0xFF, 0xFF, 0 }, /* 27 HP control */
308 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
309 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
310 { 0xFF, 0xFF, 0 }, /* 2A REC control */
311 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
312 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
313 { 0xFF, 0xFF, 0 }, /* 2D SPK control */
314 { 0xFF, 0xFF, 0 }, /* 2E sidetone */
315 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */
316
317 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
318 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
319 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
320 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */
321 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */
322 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
323 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
324 { 0xFF, 0xFF, 0 }, /* 37 INA level */
325 { 0xFF, 0xFF, 0 }, /* 38 INB level */
326 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */
327 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */
328 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */
329 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */
330 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
331 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
332 { 0xFF, 0xFF, 0 }, /* 3F MIC config */
333
334 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
335 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
336 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
337 { 0xFF, 0xFF, 0 }, /* 43 ALC */
338 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
339 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */
340 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
341 { 0xFF, 0xFF, 0 }, /* 47 audio input */
342 { 0xFF, 0xFF, 0 }, /* 48 microphone */
343 { 0xFF, 0xFF, 0 }, /* 49 level control */
344 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */
345 { 0xFF, 0xFF, 0 }, /* 4B jack detect */
346 { 0xFF, 0xFF, 0 }, /* 4C input enable */
347 { 0xFF, 0xFF, 0 }, /* 4D output enable */
348 { 0xFF, 0xFF, 0 }, /* 4E bias control */
349 { 0xFF, 0xFF, 0 }, /* 4F DAC power */
350
351 { 0xFF, 0xFF, 0 }, /* 50 DAC power */
352 { 0xFF, 0xFF, 0 }, /* 51 system */
353 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
354 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
355 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
356 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
357 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
358 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
359 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
360 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
361 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
362 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
363 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
364 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
365 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
366 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */
367
368 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
369 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
370 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
371 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
372 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
373 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
374 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
375 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
376 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
377 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
378 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
379 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
380 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
381 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
382 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
383 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */
384
385 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
386 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
387 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
388 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
389 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
390 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
391 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
392 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
393 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
394 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
395 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
396 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
397 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
398 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
399 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
400 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */
401
402 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
403 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
404 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
405 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
406 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
407 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
408 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
409 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
410 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
411 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
412 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
413 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
414 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
415 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
416 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
417 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */
418
419 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
420 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
421 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
422 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
423 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
424 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
425 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
426 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
427 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
428 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
429 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
430 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
431 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
432 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
433 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
434 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */
435
436 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
437 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
438 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
439 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
440 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
441 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
442 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
443 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
444 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
445 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
446 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
447 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
448 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
449 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
450 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
451 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */
452
453 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
454 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
455 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
456 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
457 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
458 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
459 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
460 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
461 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
462 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
463 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
464 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
465 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
466 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
467 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
468 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */
469
470 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
471 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
472 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
473 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
474 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
475 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
476 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
477 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
478 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
479 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
480 { 0x00, 0x00, 0 }, /* CA */
481 { 0x00, 0x00, 0 }, /* CB */
482 { 0x00, 0x00, 0 }, /* CC */
483 { 0x00, 0x00, 0 }, /* CD */
484 { 0x00, 0x00, 0 }, /* CE */
485 { 0x00, 0x00, 0 }, /* CF */
486
487 { 0x00, 0x00, 0 }, /* D0 */
488 { 0x00, 0x00, 0 }, /* D1 */
489 { 0x00, 0x00, 0 }, /* D2 */
490 { 0x00, 0x00, 0 }, /* D3 */
491 { 0x00, 0x00, 0 }, /* D4 */
492 { 0x00, 0x00, 0 }, /* D5 */
493 { 0x00, 0x00, 0 }, /* D6 */
494 { 0x00, 0x00, 0 }, /* D7 */
495 { 0x00, 0x00, 0 }, /* D8 */
496 { 0x00, 0x00, 0 }, /* D9 */
497 { 0x00, 0x00, 0 }, /* DA */
498 { 0x00, 0x00, 0 }, /* DB */
499 { 0x00, 0x00, 0 }, /* DC */
500 { 0x00, 0x00, 0 }, /* DD */
501 { 0x00, 0x00, 0 }, /* DE */
502 { 0x00, 0x00, 0 }, /* DF */
503
504 { 0x00, 0x00, 0 }, /* E0 */
505 { 0x00, 0x00, 0 }, /* E1 */
506 { 0x00, 0x00, 0 }, /* E2 */
507 { 0x00, 0x00, 0 }, /* E3 */
508 { 0x00, 0x00, 0 }, /* E4 */
509 { 0x00, 0x00, 0 }, /* E5 */
510 { 0x00, 0x00, 0 }, /* E6 */
511 { 0x00, 0x00, 0 }, /* E7 */
512 { 0x00, 0x00, 0 }, /* E8 */
513 { 0x00, 0x00, 0 }, /* E9 */
514 { 0x00, 0x00, 0 }, /* EA */
515 { 0x00, 0x00, 0 }, /* EB */
516 { 0x00, 0x00, 0 }, /* EC */
517 { 0x00, 0x00, 0 }, /* ED */
518 { 0x00, 0x00, 0 }, /* EE */
519 { 0x00, 0x00, 0 }, /* EF */
520
521 { 0x00, 0x00, 0 }, /* F0 */
522 { 0x00, 0x00, 0 }, /* F1 */
523 { 0x00, 0x00, 0 }, /* F2 */
524 { 0x00, 0x00, 0 }, /* F3 */
525 { 0x00, 0x00, 0 }, /* F4 */
526 { 0x00, 0x00, 0 }, /* F5 */
527 { 0x00, 0x00, 0 }, /* F6 */
528 { 0x00, 0x00, 0 }, /* F7 */
529 { 0x00, 0x00, 0 }, /* F8 */
530 { 0x00, 0x00, 0 }, /* F9 */
531 { 0x00, 0x00, 0 }, /* FA */
532 { 0x00, 0x00, 0 }, /* FB */
533 { 0x00, 0x00, 0 }, /* FC */
534 { 0x00, 0x00, 0 }, /* FD */
535 { 0x00, 0x00, 0 }, /* FE */
536 { 0xFF, 0x00, 1 }, /* FF */
537};
538
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]539static bool max98088_readable_register(struct device *dev, unsigned int reg)
540{
541 return max98088_access[reg].readable;
542}
543
544static bool max98088_volatile_register(struct device *dev, unsigned int reg)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]545{
546 return max98088_access[reg].vol;
547}
548
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]549static const struct regmap_config max98088_regmap = {
550 .reg_bits = 8,
551 .val_bits = 8,
552
553 .readable_reg = max98088_readable_register,
554 .volatile_reg = max98088_volatile_register,
Mark Brown19ab2a72013-09-24 11:14:39 +0100[diff] [blame]555 .max_register = 0xff,
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]556
557 .reg_defaults = max98088_reg,
558 .num_reg_defaults = ARRAY_SIZE(max98088_reg),
559 .cache_type = REGCACHE_RBTREE,
560};
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]561
562/*
563 * Load equalizer DSP coefficient configurations registers
564 */
Dimitris Papastamos4428bc02010-10-21 12:15:56 +0100[diff] [blame]565static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]566 unsigned int band, u16 *coefs)
567{
568 unsigned int eq_reg;
569 unsigned int i;
570
Takashi Iwaibee026d2013-11-05 18:39:49 +0100[diff] [blame]571 if (WARN_ON(band > 4) ||
572 WARN_ON(dai > 1))
573 return;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]574
575 /* Load the base register address */
576 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
577
578 /* Add the band address offset, note adjustment for word address */
579 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
580
581 /* Step through the registers and coefs */
582 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
583 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
584 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
585 }
586}
587
588/*
589 * Excursion limiter modes
590 */
591static const char *max98088_exmode_texts[] = {
592 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
593 "400-600Hz", "400-800Hz",
594};
595
596static const unsigned int max98088_exmode_values[] = {
597 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
598};
599
Takashi Iwaia0628932014-02-18 10:12:32 +0100[diff] [blame]600static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum,
601 M98088_REG_41_SPKDHP, 0, 127,
602 max98088_exmode_texts,
603 max98088_exmode_values);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]604
605static const char *max98088_ex_thresh[] = { /* volts PP */
606 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
Takashi Iwaia0628932014-02-18 10:12:32 +0100[diff] [blame]607static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum,
608 M98088_REG_42_SPKDHP_THRESH, 0,
609 max98088_ex_thresh);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]610
611static const char *max98088_fltr_mode[] = {"Voice", "Music" };
Takashi Iwaia0628932014-02-18 10:12:32 +0100[diff] [blame]612static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum,
613 M98088_REG_18_DAI1_FILTERS, 7,
614 max98088_fltr_mode);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]615
616static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
617
Takashi Iwaia0628932014-02-18 10:12:32 +0100[diff] [blame]618static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum,
619 M98088_REG_48_CFG_MIC, 0,
620 max98088_extmic_text);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]621
622static const struct snd_kcontrol_new max98088_extmic_mux =
623 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
624
625static const char *max98088_dai1_fltr[] = {
626 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
627 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
Takashi Iwaia0628932014-02-18 10:12:32 +0100[diff] [blame]628static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum,
629 M98088_REG_18_DAI1_FILTERS, 0,
630 max98088_dai1_fltr);
631static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
632 M98088_REG_18_DAI1_FILTERS, 4,
633 max98088_dai1_fltr);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]634
635static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
636 struct snd_ctl_elem_value *ucontrol)
637{
Lars-Peter Clausenea53bf72014-03-18 09:02:04 +0100[diff] [blame]638 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]639 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
640 unsigned int sel = ucontrol->value.integer.value[0];
641
642 max98088->mic1pre = sel;
643 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
644 (1+sel)<<M98088_MICPRE_SHIFT);
645
646 return 0;
647}
648
649static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
650 struct snd_ctl_elem_value *ucontrol)
651{
Lars-Peter Clausenea53bf72014-03-18 09:02:04 +0100[diff] [blame]652 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]653 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
654
655 ucontrol->value.integer.value[0] = max98088->mic1pre;
656 return 0;
657}
658
659static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
660 struct snd_ctl_elem_value *ucontrol)
661{
Lars-Peter Clausenea53bf72014-03-18 09:02:04 +0100[diff] [blame]662 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]663 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
664 unsigned int sel = ucontrol->value.integer.value[0];
665
666 max98088->mic2pre = sel;
667 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
668 (1+sel)<<M98088_MICPRE_SHIFT);
669
670 return 0;
671}
672
673static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
674 struct snd_ctl_elem_value *ucontrol)
675{
Lars-Peter Clausenea53bf72014-03-18 09:02:04 +0100[diff] [blame]676 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]677 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
678
679 ucontrol->value.integer.value[0] = max98088->mic2pre;
680 return 0;
681}
682
Lars-Peter Clausen80170462015-08-02 17:19:42 +0200[diff] [blame]683static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv,
684 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
685 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
686);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]687
Lars-Peter Clausen80170462015-08-02 17:19:42 +0200[diff] [blame]688static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv,
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]689 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
690 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
691 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
692 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
Lars-Peter Clausen80170462015-08-02 17:19:42 +0200[diff] [blame]693 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
694);
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]695
Lars-Peter Clausen80170462015-08-02 17:19:42 +0200[diff] [blame]696static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv,
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]697 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
698 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
699 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
700 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
Lars-Peter Clausen80170462015-08-02 17:19:42 +0200[diff] [blame]701 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
702);
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]703
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]704static const struct snd_kcontrol_new max98088_snd_controls[] = {
705
Dylan Reidc751a1f2013-02-15 08:55:10 -0800[diff] [blame]706 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
707 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
708 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
709 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
710 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
711 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]712
713 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
714 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
715 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
716 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
717 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
718 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
719
720 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
721 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
722
723 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
724 M98088_REG_35_LVL_MIC1, 5, 2, 0,
725 max98088_mic1pre_get, max98088_mic1pre_set,
726 max98088_micboost_tlv),
727 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
728 M98088_REG_36_LVL_MIC2, 5, 2, 0,
729 max98088_mic2pre_get, max98088_mic2pre_set,
730 max98088_micboost_tlv),
731
732 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
733 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
734
735 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
736 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
737
738 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
739 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
740
741 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
742 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
743
Jin Park938b4fb2011-05-12 14:58:37 +0900[diff] [blame]744 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]745 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
746
747 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
748 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
749 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
750 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
751 0, 1, 0),
752
753 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
754 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
755 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
756 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
757
758 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
759 4, 15, 0),
760 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
761 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
762 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
763
764 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
765 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
766};
767
768/* Left speaker mixer switch */
769static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]770 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
771 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
772 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
773 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]774 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
775 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
776 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
777 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
778 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
779 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
780};
781
782/* Right speaker mixer switch */
783static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
784 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
785 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
786 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
787 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
788 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
789 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
790 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
791 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
792 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
793 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
794};
795
796/* Left headphone mixer switch */
797static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]798 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
799 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
800 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
801 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]802 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
803 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
804 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
805 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
806 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
807 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
808};
809
810/* Right headphone mixer switch */
811static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
812 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
813 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
814 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
815 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
816 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
817 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
818 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
819 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
820 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
821 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
822};
823
824/* Left earpiece/receiver mixer switch */
825static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
Jin Park770939c2011-05-12 14:58:36 +0900[diff] [blame]826 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
827 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
828 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
829 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]830 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
831 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
832 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
833 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
834 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
835 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
836};
837
838/* Right earpiece/receiver mixer switch */
839static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
840 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
841 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
842 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
843 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
844 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
845 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
846 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
847 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
848 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
849 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
850};
851
852/* Left ADC mixer switch */
853static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
854 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
855 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
856 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
857 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
858 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
859 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
860};
861
862/* Right ADC mixer switch */
863static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
864 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
865 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
866 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
867 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
868 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
869 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
870};
871
872static int max98088_mic_event(struct snd_soc_dapm_widget *w,
873 struct snd_kcontrol *kcontrol, int event)
874{
Lars-Peter Clausen0b5155b2014-11-20 21:21:53 +0100[diff] [blame]875 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]876 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
877
878 switch (event) {
879 case SND_SOC_DAPM_POST_PMU:
880 if (w->reg == M98088_REG_35_LVL_MIC1) {
881 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
882 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
883 } else {
884 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
885 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
886 }
887 break;
888 case SND_SOC_DAPM_POST_PMD:
889 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
890 break;
891 default:
892 return -EINVAL;
893 }
894
895 return 0;
896}
897
898/*
899 * The line inputs are 2-channel stereo inputs with the left
900 * and right channels sharing a common PGA power control signal.
901 */
902static int max98088_line_pga(struct snd_soc_dapm_widget *w,
903 int event, int line, u8 channel)
904{
Lars-Peter Clausen0b5155b2014-11-20 21:21:53 +0100[diff] [blame]905 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]906 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
907 u8 *state;
908
Takashi Iwaibee026d2013-11-05 18:39:49 +0100[diff] [blame]909 if (WARN_ON(!(channel == 1 || channel == 2)))
910 return -EINVAL;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]911
912 switch (line) {
913 case LINE_INA:
914 state = &max98088->ina_state;
915 break;
916 case LINE_INB:
917 state = &max98088->inb_state;
918 break;
919 default:
920 return -EINVAL;
921 }
922
923 switch (event) {
924 case SND_SOC_DAPM_POST_PMU:
925 *state |= channel;
926 snd_soc_update_bits(codec, w->reg,
927 (1 << w->shift), (1 << w->shift));
928 break;
929 case SND_SOC_DAPM_POST_PMD:
930 *state &= ~channel;
931 if (*state == 0) {
932 snd_soc_update_bits(codec, w->reg,
933 (1 << w->shift), 0);
934 }
935 break;
936 default:
937 return -EINVAL;
938 }
939
940 return 0;
941}
942
943static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
944 struct snd_kcontrol *k, int event)
945{
946 return max98088_line_pga(w, event, LINE_INA, 1);
947}
948
949static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
950 struct snd_kcontrol *k, int event)
951{
952 return max98088_line_pga(w, event, LINE_INA, 2);
953}
954
955static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
956 struct snd_kcontrol *k, int event)
957{
958 return max98088_line_pga(w, event, LINE_INB, 1);
959}
960
961static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
962 struct snd_kcontrol *k, int event)
963{
964 return max98088_line_pga(w, event, LINE_INB, 2);
965}
966
967static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
968
969 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
970 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
971
972 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
973 M98088_REG_4D_PWR_EN_OUT, 1, 0),
974 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
975 M98088_REG_4D_PWR_EN_OUT, 0, 0),
976 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
977 M98088_REG_4D_PWR_EN_OUT, 1, 0),
978 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
979 M98088_REG_4D_PWR_EN_OUT, 0, 0),
980
981 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
982 7, 0, NULL, 0),
983 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
984 6, 0, NULL, 0),
985
986 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
987 5, 0, NULL, 0),
988 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
989 4, 0, NULL, 0),
990
991 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
992 3, 0, NULL, 0),
993 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
994 2, 0, NULL, 0),
995
996 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
997 &max98088_extmic_mux),
998
999 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
1000 &max98088_left_hp_mixer_controls[0],
1001 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
1002
1003 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
1004 &max98088_right_hp_mixer_controls[0],
1005 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
1006
1007 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
1008 &max98088_left_speaker_mixer_controls[0],
1009 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
1010
1011 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
1012 &max98088_right_speaker_mixer_controls[0],
1013 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
1014
1015 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
1016 &max98088_left_rec_mixer_controls[0],
1017 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
1018
1019 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
1020 &max98088_right_rec_mixer_controls[0],
1021 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
1022
1023 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1024 &max98088_left_ADC_mixer_controls[0],
1025 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
1026
1027 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1028 &max98088_right_ADC_mixer_controls[0],
1029 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
1030
1031 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
1032 5, 0, NULL, 0, max98088_mic_event,
1033 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1034
1035 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
1036 5, 0, NULL, 0, max98088_mic_event,
1037 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1038
1039 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
1040 7, 0, NULL, 0, max98088_pga_ina1_event,
1041 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1042
1043 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
1044 7, 0, NULL, 0, max98088_pga_ina2_event,
1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1046
1047 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
1048 6, 0, NULL, 0, max98088_pga_inb1_event,
1049 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1050
1051 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
1052 6, 0, NULL, 0, max98088_pga_inb2_event,
1053 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1054
1055 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
1056
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1057 SND_SOC_DAPM_OUTPUT("HPL"),
1058 SND_SOC_DAPM_OUTPUT("HPR"),
1059 SND_SOC_DAPM_OUTPUT("SPKL"),
1060 SND_SOC_DAPM_OUTPUT("SPKR"),
1061 SND_SOC_DAPM_OUTPUT("RECL"),
1062 SND_SOC_DAPM_OUTPUT("RECR"),
1063
1064 SND_SOC_DAPM_INPUT("MIC1"),
1065 SND_SOC_DAPM_INPUT("MIC2"),
1066 SND_SOC_DAPM_INPUT("INA1"),
1067 SND_SOC_DAPM_INPUT("INA2"),
1068 SND_SOC_DAPM_INPUT("INB1"),
1069 SND_SOC_DAPM_INPUT("INB2"),
1070};
1071
Lu Guanqundc6fc492011-03-30 21:53:10 +0800[diff] [blame]1072static const struct snd_soc_dapm_route max98088_audio_map[] = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1073 /* Left headphone output mixer */
1074 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
1075 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
1076 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
1077 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
1078 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
1079 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
1080 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
1081 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
1082 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
1083 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
1084
1085 /* Right headphone output mixer */
1086 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
1087 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
1088 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
1089 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
1090 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
1091 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
1092 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
1093 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
1094 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
1095 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
1096
1097 /* Left speaker output mixer */
1098 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
1099 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
1100 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
1101 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
1102 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1103 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1104 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
1105 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
1106 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
1107 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
1108
1109 /* Right speaker output mixer */
1110 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
1111 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
1112 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
1113 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
1114 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1115 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1116 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
1117 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
1118 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
1119 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
1120
1121 /* Earpiece/Receiver output mixer */
1122 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
1123 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
1124 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
1125 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
1126 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
1127 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
1128 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
1129 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
1130 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
1131 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
1132
1133 /* Earpiece/Receiver output mixer */
1134 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
1135 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
1136 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
1137 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
1138 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
1139 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
1140 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
1141 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
1142 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
1143 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
1144
1145 {"HP Left Out", NULL, "Left HP Mixer"},
1146 {"HP Right Out", NULL, "Right HP Mixer"},
1147 {"SPK Left Out", NULL, "Left SPK Mixer"},
1148 {"SPK Right Out", NULL, "Right SPK Mixer"},
1149 {"REC Left Out", NULL, "Left REC Mixer"},
1150 {"REC Right Out", NULL, "Right REC Mixer"},
1151
1152 {"HPL", NULL, "HP Left Out"},
1153 {"HPR", NULL, "HP Right Out"},
1154 {"SPKL", NULL, "SPK Left Out"},
1155 {"SPKR", NULL, "SPK Right Out"},
1156 {"RECL", NULL, "REC Left Out"},
1157 {"RECR", NULL, "REC Right Out"},
1158
1159 /* Left ADC input mixer */
1160 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1161 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1162 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
1163 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
1164 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
1165 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
1166
1167 /* Right ADC input mixer */
1168 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1169 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1170 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
1171 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
1172 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
1173 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
1174
1175 /* Inputs */
1176 {"ADCL", NULL, "Left ADC Mixer"},
1177 {"ADCR", NULL, "Right ADC Mixer"},
1178 {"INA1 Input", NULL, "INA1"},
1179 {"INA2 Input", NULL, "INA2"},
1180 {"INB1 Input", NULL, "INB1"},
1181 {"INB2 Input", NULL, "INB2"},
1182 {"MIC1 Input", NULL, "MIC1"},
1183 {"MIC2 Input", NULL, "MIC2"},
1184};
1185
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1186/* codec mclk clock divider coefficients */
1187static const struct {
1188 u32 rate;
1189 u8 sr;
1190} rate_table[] = {
1191 {8000, 0x10},
1192 {11025, 0x20},
1193 {16000, 0x30},
1194 {22050, 0x40},
1195 {24000, 0x50},
1196 {32000, 0x60},
1197 {44100, 0x70},
1198 {48000, 0x80},
1199 {88200, 0x90},
1200 {96000, 0xA0},
1201};
1202
1203static inline int rate_value(int rate, u8 *value)
1204{
1205 int i;
1206
1207 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1208 if (rate_table[i].rate >= rate) {
1209 *value = rate_table[i].sr;
1210 return 0;
1211 }
1212 }
1213 *value = rate_table[0].sr;
1214 return -EINVAL;
1215}
1216
1217static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
1218 struct snd_pcm_hw_params *params,
1219 struct snd_soc_dai *dai)
1220{
1221 struct snd_soc_codec *codec = dai->codec;
1222 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1223 struct max98088_cdata *cdata;
1224 unsigned long long ni;
1225 unsigned int rate;
1226 u8 regval;
1227
1228 cdata = &max98088->dai[0];
1229
1230 rate = params_rate(params);
1231
Mark Brown793f7702014-01-08 20:39:22 +0000[diff] [blame]1232 switch (params_width(params)) {
1233 case 16:
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1234 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1235 M98088_DAI_WS, 0);
1236 break;
Mark Brown793f7702014-01-08 20:39:22 +0000[diff] [blame]1237 case 24:
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1238 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1239 M98088_DAI_WS, M98088_DAI_WS);
1240 break;
1241 default:
1242 return -EINVAL;
1243 }
1244
1245 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1246
1247 if (rate_value(rate, &regval))
1248 return -EINVAL;
1249
1250 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
1251 M98088_CLKMODE_MASK, regval);
1252 cdata->rate = rate;
1253
1254 /* Configure NI when operating as master */
1255 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
1256 & M98088_DAI_MAS) {
1257 if (max98088->sysclk == 0) {
1258 dev_err(codec->dev, "Invalid system clock frequency\n");
1259 return -EINVAL;
1260 }
1261 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1262 * (unsigned long long int)rate;
1263 do_div(ni, (unsigned long long int)max98088->sysclk);
1264 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1265 (ni >> 8) & 0x7F);
1266 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1267 ni & 0xFF);
1268 }
1269
1270 /* Update sample rate mode */
1271 if (rate < 50000)
1272 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1273 M98088_DAI_DHF, 0);
1274 else
1275 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1276 M98088_DAI_DHF, M98088_DAI_DHF);
1277
1278 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1279 M98088_SHDNRUN);
1280
1281 return 0;
1282}
1283
1284static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1285 struct snd_pcm_hw_params *params,
1286 struct snd_soc_dai *dai)
1287{
1288 struct snd_soc_codec *codec = dai->codec;
1289 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1290 struct max98088_cdata *cdata;
1291 unsigned long long ni;
1292 unsigned int rate;
1293 u8 regval;
1294
1295 cdata = &max98088->dai[1];
1296
1297 rate = params_rate(params);
1298
Mark Brownb05e16d2014-07-31 12:31:44 +0100[diff] [blame]1299 switch (params_width(params)) {
1300 case 16:
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1301 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1302 M98088_DAI_WS, 0);
1303 break;
Mark Brownb05e16d2014-07-31 12:31:44 +0100[diff] [blame]1304 case 24:
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1305 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1306 M98088_DAI_WS, M98088_DAI_WS);
1307 break;
1308 default:
1309 return -EINVAL;
1310 }
1311
1312 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1313
1314 if (rate_value(rate, &regval))
1315 return -EINVAL;
1316
1317 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
1318 M98088_CLKMODE_MASK, regval);
1319 cdata->rate = rate;
1320
1321 /* Configure NI when operating as master */
1322 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
1323 & M98088_DAI_MAS) {
1324 if (max98088->sysclk == 0) {
1325 dev_err(codec->dev, "Invalid system clock frequency\n");
1326 return -EINVAL;
1327 }
1328 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1329 * (unsigned long long int)rate;
1330 do_div(ni, (unsigned long long int)max98088->sysclk);
1331 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1332 (ni >> 8) & 0x7F);
1333 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1334 ni & 0xFF);
1335 }
1336
1337 /* Update sample rate mode */
1338 if (rate < 50000)
1339 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1340 M98088_DAI_DHF, 0);
1341 else
1342 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1343 M98088_DAI_DHF, M98088_DAI_DHF);
1344
1345 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1346 M98088_SHDNRUN);
1347
1348 return 0;
1349}
1350
1351static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1352 int clk_id, unsigned int freq, int dir)
1353{
1354 struct snd_soc_codec *codec = dai->codec;
1355 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1356
1357 /* Requested clock frequency is already setup */
1358 if (freq == max98088->sysclk)
1359 return 0;
1360
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1361 /* Setup clocks for slave mode, and using the PLL
1362 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1363 * 0x02 (when master clk is 20MHz to 30MHz)..
1364 */
1365 if ((freq >= 10000000) && (freq < 20000000)) {
1366 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
1367 } else if ((freq >= 20000000) && (freq < 30000000)) {
1368 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
1369 } else {
1370 dev_err(codec->dev, "Invalid master clock frequency\n");
1371 return -EINVAL;
1372 }
1373
1374 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1375 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1376 M98088_SHDNRUN, 0);
1377 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1378 M98088_SHDNRUN, M98088_SHDNRUN);
1379 }
1380
1381 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1382
1383 max98088->sysclk = freq;
1384 return 0;
1385}
1386
1387static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1388 unsigned int fmt)
1389{
1390 struct snd_soc_codec *codec = codec_dai->codec;
1391 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1392 struct max98088_cdata *cdata;
1393 u8 reg15val;
1394 u8 reg14val = 0;
1395
1396 cdata = &max98088->dai[0];
1397
1398 if (fmt != cdata->fmt) {
1399 cdata->fmt = fmt;
1400
1401 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1402 case SND_SOC_DAIFMT_CBS_CFS:
1403 /* Slave mode PLL */
1404 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1405 0x80);
1406 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1407 0x00);
1408 break;
1409 case SND_SOC_DAIFMT_CBM_CFM:
1410 /* Set to master mode */
1411 reg14val |= M98088_DAI_MAS;
1412 break;
1413 case SND_SOC_DAIFMT_CBS_CFM:
1414 case SND_SOC_DAIFMT_CBM_CFS:
1415 default:
1416 dev_err(codec->dev, "Clock mode unsupported");
1417 return -EINVAL;
1418 }
1419
1420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1421 case SND_SOC_DAIFMT_I2S:
1422 reg14val |= M98088_DAI_DLY;
1423 break;
1424 case SND_SOC_DAIFMT_LEFT_J:
1425 break;
1426 default:
1427 return -EINVAL;
1428 }
1429
1430 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1431 case SND_SOC_DAIFMT_NB_NF:
1432 break;
1433 case SND_SOC_DAIFMT_NB_IF:
1434 reg14val |= M98088_DAI_WCI;
1435 break;
1436 case SND_SOC_DAIFMT_IB_NF:
1437 reg14val |= M98088_DAI_BCI;
1438 break;
1439 case SND_SOC_DAIFMT_IB_IF:
1440 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1441 break;
1442 default:
1443 return -EINVAL;
1444 }
1445
1446 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1447 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1448 M98088_DAI_WCI, reg14val);
1449
1450 reg15val = M98088_DAI_BSEL64;
1451 if (max98088->digmic)
1452 reg15val |= M98088_DAI_OSR64;
1453 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
1454 }
1455
1456 return 0;
1457}
1458
1459static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1460 unsigned int fmt)
1461{
1462 struct snd_soc_codec *codec = codec_dai->codec;
1463 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1464 struct max98088_cdata *cdata;
1465 u8 reg1Cval = 0;
1466
1467 cdata = &max98088->dai[1];
1468
1469 if (fmt != cdata->fmt) {
1470 cdata->fmt = fmt;
1471
1472 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1473 case SND_SOC_DAIFMT_CBS_CFS:
1474 /* Slave mode PLL */
1475 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1476 0x80);
1477 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1478 0x00);
1479 break;
1480 case SND_SOC_DAIFMT_CBM_CFM:
1481 /* Set to master mode */
1482 reg1Cval |= M98088_DAI_MAS;
1483 break;
1484 case SND_SOC_DAIFMT_CBS_CFM:
1485 case SND_SOC_DAIFMT_CBM_CFS:
1486 default:
1487 dev_err(codec->dev, "Clock mode unsupported");
1488 return -EINVAL;
1489 }
1490
1491 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1492 case SND_SOC_DAIFMT_I2S:
1493 reg1Cval |= M98088_DAI_DLY;
1494 break;
1495 case SND_SOC_DAIFMT_LEFT_J:
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1502 case SND_SOC_DAIFMT_NB_NF:
1503 break;
1504 case SND_SOC_DAIFMT_NB_IF:
1505 reg1Cval |= M98088_DAI_WCI;
1506 break;
1507 case SND_SOC_DAIFMT_IB_NF:
1508 reg1Cval |= M98088_DAI_BCI;
1509 break;
1510 case SND_SOC_DAIFMT_IB_IF:
1511 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1512 break;
1513 default:
1514 return -EINVAL;
1515 }
1516
1517 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1518 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1519 M98088_DAI_WCI, reg1Cval);
1520
1521 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
1522 M98088_DAI_BSEL64);
1523 }
1524
1525 return 0;
1526}
1527
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1528static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1529{
1530 struct snd_soc_codec *codec = codec_dai->codec;
1531 int reg;
1532
1533 if (mute)
1534 reg = M98088_DAI_MUTE;
1535 else
1536 reg = 0;
1537
1538 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY,
1539 M98088_DAI_MUTE_MASK, reg);
1540 return 0;
1541}
1542
1543static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1544{
1545 struct snd_soc_codec *codec = codec_dai->codec;
1546 int reg;
1547
1548 if (mute)
1549 reg = M98088_DAI_MUTE;
1550 else
1551 reg = 0;
1552
1553 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY,
1554 M98088_DAI_MUTE_MASK, reg);
1555 return 0;
1556}
1557
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1558static int max98088_set_bias_level(struct snd_soc_codec *codec,
1559 enum snd_soc_bias_level level)
1560{
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1561 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1562
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1563 switch (level) {
1564 case SND_SOC_BIAS_ON:
1565 break;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1566
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1567 case SND_SOC_BIAS_PREPARE:
1568 break;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1569
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1570 case SND_SOC_BIAS_STANDBY:
Lars-Peter Clausen0fbcbef2015-05-14 11:19:59 +0200[diff] [blame]1571 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1572 regcache_sync(max98088->regmap);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1573
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1574 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1575 M98088_MBEN, M98088_MBEN);
1576 break;
1577
1578 case SND_SOC_BIAS_OFF:
1579 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1580 M98088_MBEN, 0);
1581 regcache_mark_dirty(max98088->regmap);
1582 break;
1583 }
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1584 return 0;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1585}
1586
1587#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1588#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1589
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]1590static const struct snd_soc_dai_ops max98088_dai1_ops = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1591 .set_sysclk = max98088_dai_set_sysclk,
1592 .set_fmt = max98088_dai1_set_fmt,
1593 .hw_params = max98088_dai1_hw_params,
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1594 .digital_mute = max98088_dai1_digital_mute,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1595};
1596
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]1597static const struct snd_soc_dai_ops max98088_dai2_ops = {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1598 .set_sysclk = max98088_dai_set_sysclk,
1599 .set_fmt = max98088_dai2_set_fmt,
1600 .hw_params = max98088_dai2_hw_params,
Jin Park25709f62011-05-12 14:58:38 +0900[diff] [blame]1601 .digital_mute = max98088_dai2_digital_mute,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1602};
1603
1604static struct snd_soc_dai_driver max98088_dai[] = {
1605{
1606 .name = "HiFi",
1607 .playback = {
1608 .stream_name = "HiFi Playback",
1609 .channels_min = 1,
1610 .channels_max = 2,
1611 .rates = MAX98088_RATES,
1612 .formats = MAX98088_FORMATS,
1613 },
1614 .capture = {
1615 .stream_name = "HiFi Capture",
1616 .channels_min = 1,
1617 .channels_max = 2,
1618 .rates = MAX98088_RATES,
1619 .formats = MAX98088_FORMATS,
1620 },
1621 .ops = &max98088_dai1_ops,
1622},
1623{
1624 .name = "Aux",
1625 .playback = {
1626 .stream_name = "Aux Playback",
1627 .channels_min = 1,
1628 .channels_max = 2,
1629 .rates = MAX98088_RATES,
1630 .formats = MAX98088_FORMATS,
1631 },
1632 .ops = &max98088_dai2_ops,
1633}
1634};
1635
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1636static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1637
1638static int max98088_get_channel(struct snd_soc_codec *codec, const char *name)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1639{
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1640 int i;
1641
1642 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++)
1643 if (strcmp(name, eq_mode_name[i]) == 0)
1644 return i;
1645
1646 /* Shouldn't happen */
1647 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name);
1648 return -EINVAL;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1649}
1650
1651static void max98088_setup_eq1(struct snd_soc_codec *codec)
1652{
1653 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1654 struct max98088_pdata *pdata = max98088->pdata;
1655 struct max98088_eq_cfg *coef_set;
1656 int best, best_val, save, i, sel, fs;
1657 struct max98088_cdata *cdata;
1658
1659 cdata = &max98088->dai[0];
1660
1661 if (!pdata || !max98088->eq_textcnt)
1662 return;
1663
1664 /* Find the selected configuration with nearest sample rate */
1665 fs = cdata->rate;
1666 sel = cdata->eq_sel;
1667
1668 best = 0;
1669 best_val = INT_MAX;
1670 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1671 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1672 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1673 best = i;
1674 best_val = abs(pdata->eq_cfg[i].rate - fs);
1675 }
1676 }
1677
1678 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1679 pdata->eq_cfg[best].name,
1680 pdata->eq_cfg[best].rate, fs);
1681
1682 /* Disable EQ while configuring, and save current on/off state */
1683 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1684 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1685
1686 coef_set = &pdata->eq_cfg[sel];
1687
1688 m98088_eq_band(codec, 0, 0, coef_set->band1);
1689 m98088_eq_band(codec, 0, 1, coef_set->band2);
1690 m98088_eq_band(codec, 0, 2, coef_set->band3);
1691 m98088_eq_band(codec, 0, 3, coef_set->band4);
1692 m98088_eq_band(codec, 0, 4, coef_set->band5);
1693
1694 /* Restore the original on/off state */
1695 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1696}
1697
1698static void max98088_setup_eq2(struct snd_soc_codec *codec)
1699{
1700 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1701 struct max98088_pdata *pdata = max98088->pdata;
1702 struct max98088_eq_cfg *coef_set;
1703 int best, best_val, save, i, sel, fs;
1704 struct max98088_cdata *cdata;
1705
1706 cdata = &max98088->dai[1];
1707
1708 if (!pdata || !max98088->eq_textcnt)
1709 return;
1710
1711 /* Find the selected configuration with nearest sample rate */
1712 fs = cdata->rate;
1713
1714 sel = cdata->eq_sel;
1715 best = 0;
1716 best_val = INT_MAX;
1717 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1718 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1719 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1720 best = i;
1721 best_val = abs(pdata->eq_cfg[i].rate - fs);
1722 }
1723 }
1724
1725 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1726 pdata->eq_cfg[best].name,
1727 pdata->eq_cfg[best].rate, fs);
1728
1729 /* Disable EQ while configuring, and save current on/off state */
1730 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1731 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1732
1733 coef_set = &pdata->eq_cfg[sel];
1734
1735 m98088_eq_band(codec, 1, 0, coef_set->band1);
1736 m98088_eq_band(codec, 1, 1, coef_set->band2);
1737 m98088_eq_band(codec, 1, 2, coef_set->band3);
1738 m98088_eq_band(codec, 1, 3, coef_set->band4);
1739 m98088_eq_band(codec, 1, 4, coef_set->band5);
1740
1741 /* Restore the original on/off state */
1742 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1743 save);
1744}
1745
1746static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1747 struct snd_ctl_elem_value *ucontrol)
1748{
Lars-Peter Clausenea53bf72014-03-18 09:02:04 +0100[diff] [blame]1749 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1750 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1751 struct max98088_pdata *pdata = max98088->pdata;
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1752 int channel = max98088_get_channel(codec, kcontrol->id.name);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1753 struct max98088_cdata *cdata;
1754 int sel = ucontrol->value.integer.value[0];
1755
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1756 if (channel < 0)
1757 return channel;
1758
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1759 cdata = &max98088->dai[channel];
1760
1761 if (sel >= pdata->eq_cfgcnt)
1762 return -EINVAL;
1763
1764 cdata->eq_sel = sel;
1765
1766 switch (channel) {
1767 case 0:
1768 max98088_setup_eq1(codec);
1769 break;
1770 case 1:
1771 max98088_setup_eq2(codec);
1772 break;
1773 }
1774
1775 return 0;
1776}
1777
1778static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1779 struct snd_ctl_elem_value *ucontrol)
1780{
Lars-Peter Clausenea53bf72014-03-18 09:02:04 +0100[diff] [blame]1781 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1782 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1783 int channel = max98088_get_channel(codec, kcontrol->id.name);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1784 struct max98088_cdata *cdata;
1785
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1786 if (channel < 0)
1787 return channel;
1788
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1789 cdata = &max98088->dai[channel];
1790 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1791 return 0;
1792}
1793
1794static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
1795{
1796 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1797 struct max98088_pdata *pdata = max98088->pdata;
1798 struct max98088_eq_cfg *cfg;
1799 unsigned int cfgcnt;
1800 int i, j;
1801 const char **t;
1802 int ret;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1803 struct snd_kcontrol_new controls[] = {
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1804 SOC_ENUM_EXT((char *)eq_mode_name[0],
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1805 max98088->eq_enum,
1806 max98088_get_eq_enum,
1807 max98088_put_eq_enum),
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1808 SOC_ENUM_EXT((char *)eq_mode_name[1],
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1809 max98088->eq_enum,
1810 max98088_get_eq_enum,
1811 max98088_put_eq_enum),
1812 };
Ryan Mallon8754f222011-10-04 09:55:40 +1100[diff] [blame]1813 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1814
1815 cfg = pdata->eq_cfg;
1816 cfgcnt = pdata->eq_cfgcnt;
1817
1818 /* Setup an array of texts for the equalizer enum.
1819 * This is based on Mark Brown's equalizer driver code.
1820 */
1821 max98088->eq_textcnt = 0;
1822 max98088->eq_texts = NULL;
1823 for (i = 0; i < cfgcnt; i++) {
1824 for (j = 0; j < max98088->eq_textcnt; j++) {
1825 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1826 break;
1827 }
1828
1829 if (j != max98088->eq_textcnt)
1830 continue;
1831
1832 /* Expand the array */
1833 t = krealloc(max98088->eq_texts,
1834 sizeof(char *) * (max98088->eq_textcnt + 1),
1835 GFP_KERNEL);
1836 if (t == NULL)
1837 continue;
1838
1839 /* Store the new entry */
1840 t[max98088->eq_textcnt] = cfg[i].name;
1841 max98088->eq_textcnt++;
1842 max98088->eq_texts = t;
1843 }
1844
1845 /* Now point the soc_enum to .texts array items */
1846 max98088->eq_enum.texts = max98088->eq_texts;
Takashi Iwai9a8d38d2014-02-18 08:11:42 +0100[diff] [blame]1847 max98088->eq_enum.items = max98088->eq_textcnt;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1848
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]1849 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1850 if (ret != 0)
1851 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1852}
1853
1854static void max98088_handle_pdata(struct snd_soc_codec *codec)
1855{
1856 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1857 struct max98088_pdata *pdata = max98088->pdata;
1858 u8 regval = 0;
1859
1860 if (!pdata) {
1861 dev_dbg(codec->dev, "No platform data\n");
1862 return;
1863 }
1864
1865 /* Configure mic for analog/digital mic mode */
1866 if (pdata->digmic_left_mode)
1867 regval |= M98088_DIGMIC_L;
1868
1869 if (pdata->digmic_right_mode)
1870 regval |= M98088_DIGMIC_R;
1871
1872 max98088->digmic = (regval ? 1 : 0);
1873
1874 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
1875
1876 /* Configure receiver output */
1877 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1878 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
1879 M98088_REC_LINEMODE_MASK, regval);
1880
1881 /* Configure equalizers */
1882 if (pdata->eq_cfgcnt)
1883 max98088_handle_eq_pdata(codec);
1884}
1885
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1886static int max98088_probe(struct snd_soc_codec *codec)
1887{
1888 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1889 struct max98088_cdata *cdata;
1890 int ret = 0;
1891
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1892 regcache_mark_dirty(max98088->regmap);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1893
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400[diff] [blame]1894 /* initialize private data */
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1895
1896 max98088->sysclk = (unsigned)-1;
1897 max98088->eq_textcnt = 0;
1898
1899 cdata = &max98088->dai[0];
1900 cdata->rate = (unsigned)-1;
1901 cdata->fmt = (unsigned)-1;
1902 cdata->eq_sel = 0;
1903
1904 cdata = &max98088->dai[1];
1905 cdata->rate = (unsigned)-1;
1906 cdata->fmt = (unsigned)-1;
1907 cdata->eq_sel = 0;
1908
1909 max98088->ina_state = 0;
1910 max98088->inb_state = 0;
1911 max98088->ex_mode = 0;
1912 max98088->digmic = 0;
1913 max98088->mic1pre = 0;
1914 max98088->mic2pre = 0;
1915
1916 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
1917 if (ret < 0) {
1918 dev_err(codec->dev, "Failed to read device revision: %d\n",
1919 ret);
1920 goto err_access;
1921 }
Dylan Reid98682062013-04-16 20:02:34 -0700[diff] [blame]1922 dev_info(codec->dev, "revision %c\n", ret - 0x40 + 'A');
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1923
1924 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1925
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1926 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
1927
1928 snd_soc_write(codec, M98088_REG_22_MIX_DAC,
1929 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1930 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
1931
1932 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
1933 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
1934
1935 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
1936 M98088_S1NORMAL|M98088_SDATA);
1937
1938 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
1939 M98088_S2NORMAL|M98088_SDATA);
1940
1941 max98088_handle_pdata(codec);
1942
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1943err_access:
1944 return ret;
1945}
1946
1947static int max98088_remove(struct snd_soc_codec *codec)
1948{
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]1949 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1950
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]1951 kfree(max98088->eq_texts);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1952
1953 return 0;
1954}
1955
1956static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]1957 .probe = max98088_probe,
1958 .remove = max98088_remove,
Mark Brown356d86e2013-09-23 17:22:17 +0100[diff] [blame]1959 .set_bias_level = max98088_set_bias_level,
Lars-Peter Clausena613cc42014-10-20 10:56:33 +0200[diff] [blame]1960 .suspend_bias_off = true,
1961
Mark Brownad65adf2013-09-23 17:54:02 +0100[diff] [blame]1962 .controls = max98088_snd_controls,
1963 .num_controls = ARRAY_SIZE(max98088_snd_controls),
Lu Guanqundc6fc492011-03-30 21:53:10 +0800[diff] [blame]1964 .dapm_widgets = max98088_dapm_widgets,
1965 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
1966 .dapm_routes = max98088_audio_map,
1967 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1968};
1969
1970static int max98088_i2c_probe(struct i2c_client *i2c,
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1971 const struct i2c_device_id *id)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1972{
1973 struct max98088_priv *max98088;
1974 int ret;
1975
Axel Lin49ba7672011-12-29 12:01:07 +0800[diff] [blame]1976 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
1977 GFP_KERNEL);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1978 if (max98088 == NULL)
1979 return -ENOMEM;
1980
Mark Brown4127d5d2013-09-23 17:56:17 +0100[diff] [blame]1981 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
1982 if (IS_ERR(max98088->regmap))
1983 return PTR_ERR(max98088->regmap);
1984
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]1985 max98088->devtype = id->driver_data;
1986
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1987 i2c_set_clientdata(i2c, max98088);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1988 max98088->pdata = i2c->dev.platform_data;
1989
1990 ret = snd_soc_register_codec(&i2c->dev,
1991 &soc_codec_dev_max98088, &max98088_dai[0], 2);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1992 return ret;
1993}
1994
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]1995static int max98088_i2c_remove(struct i2c_client *client)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1996{
1997 snd_soc_unregister_codec(&client->dev);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1998 return 0;
1999}
2000
2001static const struct i2c_device_id max98088_i2c_id[] = {
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2002 { "max98088", MAX98088 },
2003 { "max98089", MAX98089 },
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2004 { }
2005};
2006MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
2007
2008static struct i2c_driver max98088_i2c_driver = {
Bill Pemberton69395652012-11-19 13:19:39 -0500[diff] [blame]2009 .driver = {
2010 .name = "max98088",
2011 .owner = THIS_MODULE,
2012 },
2013 .probe = max98088_i2c_probe,
2014 .remove = max98088_i2c_remove,
2015 .id_table = max98088_i2c_id,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2016};
2017
Sachin Kamat2342a072012-08-06 17:25:51 +0530[diff] [blame]2018module_i2c_driver(max98088_i2c_driver);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2019
2020MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
2021MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
2022MODULE_LICENSE("GPL");