blob: 913edf2832399cb5d5cb36b3bb26bf9d8364e638 [file] [log] [blame]
Christian Pellegrin1cad1de2008-11-15 08:58:16 +01001/*
2 * uda134x.c -- UDA134X ALSA SoC Codec driver
3 *
4 * Modifications by Christian Pellegrin <chripell@evolware.org>
5 *
6 * Copyright 2007 Dension Audio Systems Ltd.
7 * Author: Zoltan Devai
8 *
9 * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Christian Pellegrin1cad1de2008-11-15 08:58:16 +010019#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
Christian Pellegrin1cad1de2008-11-15 08:58:16 +010022#include <sound/initval.h>
23
24#include <sound/uda134x.h>
25#include <sound/l3.h>
26
Mark Brown72f2b892008-11-18 12:25:46 +000027#include "uda134x.h"
Christian Pellegrin1cad1de2008-11-15 08:58:16 +010028
29
Christian Pellegrin1cad1de2008-11-15 08:58:16 +010030#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
31#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
32 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)
33
34struct uda134x_priv {
35 int sysclk;
36 int dai_fmt;
37
38 struct snd_pcm_substream *master_substream;
39 struct snd_pcm_substream *slave_substream;
40};
41
42/* In-data addresses are hard-coded into the reg-cache values */
43static const char uda134x_reg[UDA134X_REGS_NUM] = {
44 /* Extended address registers */
45 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
46 /* Status, data regs */
Vladimir Zapolskiyed632ad2010-06-24 15:17:07 +040047 0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
Christian Pellegrin1cad1de2008-11-15 08:58:16 +010048};
49
50/*
51 * The codec has no support for reading its registers except for peak level...
52 */
53static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
54 unsigned int reg)
55{
56 u8 *cache = codec->reg_cache;
57
58 if (reg >= UDA134X_REGS_NUM)
59 return -1;
60 return cache[reg];
61}
62
63/*
64 * Write the register cache
65 */
66static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
67 u8 reg, unsigned int value)
68{
69 u8 *cache = codec->reg_cache;
70
71 if (reg >= UDA134X_REGS_NUM)
72 return;
73 cache[reg] = value;
74}
75
76/*
77 * Write to the uda134x registers
78 *
79 */
80static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
81 unsigned int value)
82{
83 int ret;
84 u8 addr;
85 u8 data = value;
86 struct uda134x_platform_data *pd = codec->control_data;
87
88 pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
89
90 if (reg >= UDA134X_REGS_NUM) {
André Goddard Rosaaf901ca2009-11-14 13:09:05 -020091 printk(KERN_ERR "%s unknown register: reg: %u",
Christian Pellegrin1cad1de2008-11-15 08:58:16 +010092 __func__, reg);
93 return -EINVAL;
94 }
95
96 uda134x_write_reg_cache(codec, reg, value);
97
98 switch (reg) {
99 case UDA134X_STATUS0:
100 case UDA134X_STATUS1:
101 addr = UDA134X_STATUS_ADDR;
102 break;
103 case UDA134X_DATA000:
104 case UDA134X_DATA001:
105 case UDA134X_DATA010:
Vladimir Zapolskiyed632ad2010-06-24 15:17:07 +0400106 case UDA134X_DATA011:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100107 addr = UDA134X_DATA0_ADDR;
108 break;
109 case UDA134X_DATA1:
110 addr = UDA134X_DATA1_ADDR;
111 break;
112 default:
113 /* It's an extended address register */
114 addr = (reg | UDA134X_EXTADDR_PREFIX);
115
116 ret = l3_write(&pd->l3,
117 UDA134X_DATA0_ADDR, &addr, 1);
118 if (ret != 1)
119 return -EIO;
120
121 addr = UDA134X_DATA0_ADDR;
122 data = (value | UDA134X_EXTDATA_PREFIX);
123 break;
124 }
125
126 ret = l3_write(&pd->l3,
127 addr, &data, 1);
128 if (ret != 1)
129 return -EIO;
130
131 return 0;
132}
133
134static inline void uda134x_reset(struct snd_soc_codec *codec)
135{
136 u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
137 uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
138 msleep(1);
139 uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
140}
141
142static int uda134x_mute(struct snd_soc_dai *dai, int mute)
143{
144 struct snd_soc_codec *codec = dai->codec;
145 u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
146
147 pr_debug("%s mute: %d\n", __func__, mute);
148
149 if (mute)
150 mute_reg |= (1<<2);
151 else
152 mute_reg &= ~(1<<2);
153
Shine Liu0c093fb2009-08-17 18:52:01 +0800154 uda134x_write(codec, UDA134X_DATA010, mute_reg);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100155
156 return 0;
157}
158
Mark Browndee89c42008-11-18 22:11:38 +0000159static int uda134x_startup(struct snd_pcm_substream *substream,
160 struct snd_soc_dai *dai)
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100161{
Mark Browne6968a12012-04-04 15:58:16 +0100162 struct snd_soc_codec *codec = dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900163 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100164 struct snd_pcm_runtime *master_runtime;
165
166 if (uda134x->master_substream) {
167 master_runtime = uda134x->master_substream->runtime;
168
169 pr_debug("%s constraining to %d bits at %d\n", __func__,
170 master_runtime->sample_bits,
171 master_runtime->rate);
172
173 snd_pcm_hw_constraint_minmax(substream->runtime,
174 SNDRV_PCM_HW_PARAM_RATE,
175 master_runtime->rate,
176 master_runtime->rate);
177
178 snd_pcm_hw_constraint_minmax(substream->runtime,
179 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
180 master_runtime->sample_bits,
181 master_runtime->sample_bits);
182
183 uda134x->slave_substream = substream;
184 } else
185 uda134x->master_substream = substream;
186
187 return 0;
188}
189
Mark Browndee89c42008-11-18 22:11:38 +0000190static void uda134x_shutdown(struct snd_pcm_substream *substream,
191 struct snd_soc_dai *dai)
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100192{
Mark Browne6968a12012-04-04 15:58:16 +0100193 struct snd_soc_codec *codec = dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900194 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100195
196 if (uda134x->master_substream == substream)
197 uda134x->master_substream = uda134x->slave_substream;
198
199 uda134x->slave_substream = NULL;
200}
201
202static int uda134x_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +0000203 struct snd_pcm_hw_params *params,
204 struct snd_soc_dai *dai)
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100205{
Lars-Peter Clausenab642462014-03-13 21:24:54 +0100206 struct snd_soc_codec *codec = dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900207 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100208 u8 hw_params;
209
210 if (substream == uda134x->slave_substream) {
211 pr_debug("%s ignoring hw_params for slave substream\n",
212 __func__);
213 return 0;
214 }
215
216 hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
217 hw_params &= STATUS0_SYSCLK_MASK;
218 hw_params &= STATUS0_DAIFMT_MASK;
219
220 pr_debug("%s sysclk: %d, rate:%d\n", __func__,
221 uda134x->sysclk, params_rate(params));
222
223 /* set SYSCLK / fs ratio */
224 switch (uda134x->sysclk / params_rate(params)) {
225 case 512:
226 break;
227 case 384:
228 hw_params |= (1<<4);
229 break;
230 case 256:
231 hw_params |= (1<<5);
232 break;
233 default:
234 printk(KERN_ERR "%s unsupported fs\n", __func__);
235 return -EINVAL;
236 }
237
238 pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
239 uda134x->dai_fmt, params_format(params));
240
241 /* set DAI format and word length */
242 switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
243 case SND_SOC_DAIFMT_I2S:
244 break;
245 case SND_SOC_DAIFMT_RIGHT_J:
Mark Brownaa9ffad2014-07-31 12:49:26 +0100246 switch (params_width(params)) {
247 case 16:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100248 hw_params |= (1<<1);
249 break;
Mark Brownaa9ffad2014-07-31 12:49:26 +0100250 case 18:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100251 hw_params |= (1<<2);
252 break;
Mark Brownaa9ffad2014-07-31 12:49:26 +0100253 case 20:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100254 hw_params |= ((1<<2) | (1<<1));
255 break;
256 default:
257 printk(KERN_ERR "%s unsupported format (right)\n",
258 __func__);
259 return -EINVAL;
260 }
261 break;
262 case SND_SOC_DAIFMT_LEFT_J:
263 hw_params |= (1<<3);
264 break;
265 default:
266 printk(KERN_ERR "%s unsupported format\n", __func__);
267 return -EINVAL;
268 }
269
270 uda134x_write(codec, UDA134X_STATUS0, hw_params);
271
272 return 0;
273}
274
275static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
276 int clk_id, unsigned int freq, int dir)
277{
278 struct snd_soc_codec *codec = codec_dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900279 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100280
Roel Kluin449bd542009-05-27 17:08:39 -0700281 pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100282 clk_id, freq, dir);
283
284 /* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
285 because the codec is slave. Of course limitations of the clock
286 master (the IIS controller) apply.
287 We'll error out on set_hw_params if it's not OK */
288 if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
289 uda134x->sysclk = freq;
290 return 0;
291 }
292
293 printk(KERN_ERR "%s unsupported sysclk\n", __func__);
294 return -EINVAL;
295}
296
297static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
298 unsigned int fmt)
299{
300 struct snd_soc_codec *codec = codec_dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900301 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100302
303 pr_debug("%s fmt: %08X\n", __func__, fmt);
304
305 /* codec supports only full slave mode */
306 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
307 printk(KERN_ERR "%s unsupported slave mode\n", __func__);
308 return -EINVAL;
309 }
310
311 /* no support for clock inversion */
312 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
313 printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
314 return -EINVAL;
315 }
316
317 /* We can't setup DAI format here as it depends on the word bit num */
318 /* so let's just store the value for later */
319 uda134x->dai_fmt = fmt;
320
321 return 0;
322}
323
324static int uda134x_set_bias_level(struct snd_soc_codec *codec,
325 enum snd_soc_bias_level level)
326{
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100327 struct uda134x_platform_data *pd = codec->control_data;
328 int i;
329 u8 *cache = codec->reg_cache;
330
331 pr_debug("%s bias level %d\n", __func__, level);
332
333 switch (level) {
334 case SND_SOC_BIAS_ON:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100335 break;
336 case SND_SOC_BIAS_PREPARE:
337 /* power on */
338 if (pd->power) {
339 pd->power(1);
340 /* Sync reg_cache with the hardware */
341 for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000342 codec->driver->write(codec, i, *cache++);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100343 }
344 break;
345 case SND_SOC_BIAS_STANDBY:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100346 break;
347 case SND_SOC_BIAS_OFF:
348 /* power off */
349 if (pd->power)
350 pd->power(0);
351 break;
352 }
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100353 return 0;
354}
355
356static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
357 "Minimum2", "Maximum"};
358static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
359static const char *uda134x_mixmode[] = {"Differential", "Analog1",
360 "Analog2", "Both"};
361
362static const struct soc_enum uda134x_mixer_enum[] = {
363SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
364SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
365SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
366};
367
368static const struct snd_kcontrol_new uda1341_snd_controls[] = {
369SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
370SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
371SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
372SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
373
374SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
375SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
376
377SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
378SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
379
380SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
381SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
382SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
383
384SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
385SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
386SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
387
388SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
389SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
390SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
391SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
392SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
393SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
394};
395
396static const struct snd_kcontrol_new uda1340_snd_controls[] = {
397SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
398
399SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
400SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
401
402SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
403SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
404
405SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
406};
407
Vladimir Zapolskiyb28528a2010-04-26 14:56:57 +0400408static const struct snd_kcontrol_new uda1345_snd_controls[] = {
409SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
410
411SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
412
413SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
414};
415
Russell King113591e2013-07-30 11:18:52 +0100416/* UDA1341 has the DAC/ADC power down in STATUS1 */
417static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
418 SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
419 SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
420};
421
422/* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
423static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
424 SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
425 SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
426};
427
428/* Common DAPM widgets */
429static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
430 SND_SOC_DAPM_INPUT("VINL1"),
431 SND_SOC_DAPM_INPUT("VINR1"),
432 SND_SOC_DAPM_INPUT("VINL2"),
433 SND_SOC_DAPM_INPUT("VINR2"),
434 SND_SOC_DAPM_OUTPUT("VOUTL"),
435 SND_SOC_DAPM_OUTPUT("VOUTR"),
436};
437
438static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
439 { "ADC", NULL, "VINL1" },
440 { "ADC", NULL, "VINR1" },
441 { "ADC", NULL, "VINL2" },
442 { "ADC", NULL, "VINR2" },
443 { "VOUTL", NULL, "DAC" },
444 { "VOUTR", NULL, "DAC" },
445};
446
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100447static const struct snd_soc_dai_ops uda134x_dai_ops = {
Eric Miao6335d052009-03-03 09:41:00 +0800448 .startup = uda134x_startup,
449 .shutdown = uda134x_shutdown,
450 .hw_params = uda134x_hw_params,
451 .digital_mute = uda134x_mute,
452 .set_sysclk = uda134x_set_dai_sysclk,
453 .set_fmt = uda134x_set_dai_fmt,
454};
455
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000456static struct snd_soc_dai_driver uda134x_dai = {
457 .name = "uda134x-hifi",
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100458 /* playback capabilities */
459 .playback = {
460 .stream_name = "Playback",
461 .channels_min = 1,
462 .channels_max = 2,
463 .rates = UDA134X_RATES,
464 .formats = UDA134X_FORMATS,
465 },
466 /* capture capabilities */
467 .capture = {
468 .stream_name = "Capture",
469 .channels_min = 1,
470 .channels_max = 2,
471 .rates = UDA134X_RATES,
472 .formats = UDA134X_FORMATS,
473 },
474 /* pcm operations */
Eric Miao6335d052009-03-03 09:41:00 +0800475 .ops = &uda134x_dai_ops,
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100476};
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100477
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000478static int uda134x_soc_probe(struct snd_soc_codec *codec)
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100479{
Lars-Peter Clausen81024b12015-05-11 09:42:33 +0200480 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100481 struct uda134x_priv *uda134x;
Lars-Peter Clausen00200102014-07-17 22:01:07 +0200482 struct uda134x_platform_data *pd = codec->component.card->dev->platform_data;
Russell King113591e2013-07-30 11:18:52 +0100483 const struct snd_soc_dapm_widget *widgets;
484 unsigned num_widgets;
Marek Beliskoa110f4e2011-03-09 21:46:20 +0100485
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000486 int ret;
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100487
488 printk(KERN_INFO "UDA134X SoC Audio Codec\n");
489
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000490 if (!pd) {
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100491 printk(KERN_ERR "UDA134X SoC codec: "
492 "missing L3 bitbang function\n");
493 return -ENODEV;
494 }
495
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100496 switch (pd->model) {
497 case UDA134X_UDA1340:
498 case UDA134X_UDA1341:
499 case UDA134X_UDA1344:
Vladimir Zapolskiyb28528a2010-04-26 14:56:57 +0400500 case UDA134X_UDA1345:
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100501 break;
502 default:
503 printk(KERN_ERR "UDA134X SoC codec: "
504 "unsupported model %d\n",
505 pd->model);
506 return -EINVAL;
507 }
508
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100509 uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
510 if (uda134x == NULL)
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000511 return -ENOMEM;
Mark Brownb2c812e2010-04-14 15:35:19 +0900512 snd_soc_codec_set_drvdata(codec, uda134x);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100513
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000514 codec->control_data = pd;
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100515
516 if (pd->power)
517 pd->power(1);
518
519 uda134x_reset(codec);
520
Russell King113591e2013-07-30 11:18:52 +0100521 if (pd->model == UDA134X_UDA1341) {
522 widgets = uda1341_dapm_widgets;
523 num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
524 } else {
525 widgets = uda1340_dapm_widgets;
526 num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
527 }
528
Lars-Peter Clausen81024b12015-05-11 09:42:33 +0200529 ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
Russell King113591e2013-07-30 11:18:52 +0100530 if (ret) {
531 printk(KERN_ERR "%s failed to register dapm controls: %d",
532 __func__, ret);
533 kfree(uda134x);
534 return ret;
535 }
536
Ian Molton3e8e1952009-01-09 00:23:21 +0000537 switch (pd->model) {
538 case UDA134X_UDA1340:
539 case UDA134X_UDA1344:
Liam Girdwood022658b2012-02-03 17:43:09 +0000540 ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
Ian Molton3e8e1952009-01-09 00:23:21 +0000541 ARRAY_SIZE(uda1340_snd_controls));
542 break;
543 case UDA134X_UDA1341:
Liam Girdwood022658b2012-02-03 17:43:09 +0000544 ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
Ian Molton3e8e1952009-01-09 00:23:21 +0000545 ARRAY_SIZE(uda1341_snd_controls));
546 break;
Vladimir Zapolskiyb28528a2010-04-26 14:56:57 +0400547 case UDA134X_UDA1345:
Liam Girdwood022658b2012-02-03 17:43:09 +0000548 ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
Vladimir Zapolskiyb28528a2010-04-26 14:56:57 +0400549 ARRAY_SIZE(uda1345_snd_controls));
550 break;
Ian Molton3e8e1952009-01-09 00:23:21 +0000551 default:
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200552 printk(KERN_ERR "%s unknown codec type: %d",
Ian Molton3e8e1952009-01-09 00:23:21 +0000553 __func__, pd->model);
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000554 kfree(uda134x);
555 return -EINVAL;
Ian Molton3e8e1952009-01-09 00:23:21 +0000556 }
557
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100558 if (ret < 0) {
559 printk(KERN_ERR "UDA134X: failed to register controls\n");
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000560 kfree(uda134x);
561 return ret;
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100562 }
563
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100564 return 0;
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100565}
566
567/* power down chip */
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000568static int uda134x_soc_remove(struct snd_soc_codec *codec)
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100569{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000570 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100571
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000572 kfree(uda134x);
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100573 return 0;
574}
575
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000576static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100577 .probe = uda134x_soc_probe,
578 .remove = uda134x_soc_remove,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000579 .reg_cache_size = sizeof(uda134x_reg),
580 .reg_word_size = sizeof(u8),
Axel Lin2811fe22010-11-19 15:48:06 +0800581 .reg_cache_default = uda134x_reg,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000582 .reg_cache_step = 1,
583 .read = uda134x_read_reg_cache,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000584 .set_bias_level = uda134x_set_bias_level,
Lars-Peter Clausene03b9752014-11-23 15:04:13 +0100585 .suspend_bias_off = true,
586
Russell King113591e2013-07-30 11:18:52 +0100587 .dapm_widgets = uda134x_dapm_widgets,
588 .num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets),
589 .dapm_routes = uda134x_dapm_routes,
590 .num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes),
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100591};
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100592
Bill Pemberton7a79e942012-12-07 09:26:37 -0500593static int uda134x_codec_probe(struct platform_device *pdev)
Mark Brown64089b82008-12-08 19:17:58 +0000594{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000595 return snd_soc_register_codec(&pdev->dev,
596 &soc_codec_dev_uda134x, &uda134x_dai, 1);
Mark Brown64089b82008-12-08 19:17:58 +0000597}
Mark Brown64089b82008-12-08 19:17:58 +0000598
Bill Pemberton7a79e942012-12-07 09:26:37 -0500599static int uda134x_codec_remove(struct platform_device *pdev)
Mark Brown64089b82008-12-08 19:17:58 +0000600{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000601 snd_soc_unregister_codec(&pdev->dev);
602 return 0;
Mark Brown64089b82008-12-08 19:17:58 +0000603}
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000604
605static struct platform_driver uda134x_codec_driver = {
606 .driver = {
607 .name = "uda134x-codec",
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000608 },
609 .probe = uda134x_codec_probe,
Bill Pemberton7a79e942012-12-07 09:26:37 -0500610 .remove = uda134x_codec_remove,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000611};
612
Mark Brown5bbcc3c2011-11-23 22:52:08 +0000613module_platform_driver(uda134x_codec_driver);
Mark Brown64089b82008-12-08 19:17:58 +0000614
Christian Pellegrin1cad1de2008-11-15 08:58:16 +0100615MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
616MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
617MODULE_LICENSE("GPL");