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gerrit-public.fairphone.software / kernel / msm-4.9 / 6d803ba736abb5e122dede70a4720e4843dd6df4 / . / arch / arm / mach-tcc8k / time.c
blob: 78d06008841d87adda56524b0b101555097ce55d [file] [log] [blame]
Hans J. Koch3de7b512010-09-17 18:17:42 +0200[diff] [blame]1/*
2 * TCC8000 system timer setup
3 *
4 * (C) 2009 Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPL version 2.
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/clockchips.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#include <asm/mach/time.h>
20
21#include <mach/tcc8k-regs.h>
22#include <mach/irqs.h>
23
24#include "common.h"
25
26static void __iomem *timer_base;
27
28static cycle_t tcc_get_cycles(struct clocksource *cs)
29{
30 return __raw_readl(timer_base + TC32MCNT_OFFS);
31}
32
33static struct clocksource clocksource_tcc = {
34 .name = "tcc_tc32",
35 .rating = 200,
36 .read = tcc_get_cycles,
37 .mask = CLOCKSOURCE_MASK(32),
38 .shift = 28,
39 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
40};
41
42static int tcc_set_next_event(unsigned long evt,
43 struct clock_event_device *unused)
44{
45 unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
46
47 __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
48 return 0;
49}
50
51static void tcc_set_mode(enum clock_event_mode mode,
52 struct clock_event_device *evt)
53{
54 unsigned long tc32irq;
55
56 switch (mode) {
57 case CLOCK_EVT_MODE_ONESHOT:
58 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
59 tc32irq |= TC32IRQ_IRQEN0;
60 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
61 break;
62 case CLOCK_EVT_MODE_SHUTDOWN:
63 case CLOCK_EVT_MODE_UNUSED:
64 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
65 tc32irq &= ~TC32IRQ_IRQEN0;
66 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
67 break;
68 case CLOCK_EVT_MODE_PERIODIC:
69 case CLOCK_EVT_MODE_RESUME:
70 break;
71 }
72}
73
74static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
75{
76 struct clock_event_device *evt = dev_id;
77
78 /* Acknowledge TC32 interrupt by reading TC32IRQ */
79 __raw_readl(timer_base + TC32IRQ_OFFS);
80
81 evt->event_handler(evt);
82
83 return IRQ_HANDLED;
84}
85
86static struct clock_event_device clockevent_tcc = {
87 .name = "tcc_timer1",
88 .features = CLOCK_EVT_FEAT_ONESHOT,
89 .shift = 32,
90 .set_mode = tcc_set_mode,
91 .set_next_event = tcc_set_next_event,
92 .rating = 200,
93};
94
95static struct irqaction tcc8k_timer_irq = {
96 .name = "TC32_timer",
97 .flags = IRQF_DISABLED | IRQF_TIMER,
98 .handler = tcc8k_timer_interrupt,
99 .dev_id = &clockevent_tcc,
100};
101
102static int __init tcc_clockevent_init(struct clk *clock)
103{
104 unsigned int c = clk_get_rate(clock);
105
106 clocksource_tcc.mult = clocksource_hz2mult(c,
107 clocksource_tcc.shift);
108 clocksource_register(&clocksource_tcc);
109
110 clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
111 clockevent_tcc.shift);
112 clockevent_tcc.max_delta_ns =
113 clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
114 clockevent_tcc.min_delta_ns =
115 clockevent_delta2ns(0xff, &clockevent_tcc);
116
117 clockevent_tcc.cpumask = cpumask_of(0);
118
119 clockevents_register_device(&clockevent_tcc);
120
121 return 0;
122}
123
124void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
125{
126 u32 reg;
127
128 timer_base = base;
129 tcc8k_timer_irq.irq = irq;
130
131 /* Enable clocks */
132 clk_enable(clock);
133
134 /* Initialize 32-bit timer */
135 reg = __raw_readl(timer_base + TC32EN_OFFS);
136 reg &= ~TC32EN_ENABLE; /* Disable timer */
137 __raw_writel(reg, timer_base + TC32EN_OFFS);
138 /* Free running timer, counting from 0 to 0xffffffff */
139 __raw_writel(0, timer_base + TC32EN_OFFS);
140 __raw_writel(0, timer_base + TC32LDV_OFFS);
141 reg = __raw_readl(timer_base + TC32IRQ_OFFS);
142 reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
143 __raw_writel(reg, timer_base + TC32IRQ_OFFS);
144
145 __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
146
147 tcc_clockevent_init(clock);
148 setup_irq(irq, &tcc8k_timer_irq);
149}