Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare network controllers and boards |
| 3 | * Copyright 2012-2013 Solarflare Communications Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published |
| 7 | * by the Free Software Foundation, incorporated herein by reference. |
| 8 | */ |
| 9 | |
| 10 | #include "net_driver.h" |
| 11 | #include "ef10_regs.h" |
| 12 | #include "io.h" |
| 13 | #include "mcdi.h" |
| 14 | #include "mcdi_pcol.h" |
| 15 | #include "nic.h" |
| 16 | #include "workarounds.h" |
Jon Cooper | 74cd60a | 2013-09-16 14:18:51 +0100 | [diff] [blame] | 17 | #include "selftest.h" |
Shradha Shah | 7fa8d54 | 2015-05-06 00:55:13 +0100 | [diff] [blame] | 18 | #include "ef10_sriov.h" |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 19 | #include <linux/in.h> |
| 20 | #include <linux/jhash.h> |
| 21 | #include <linux/wait.h> |
| 22 | #include <linux/workqueue.h> |
| 23 | |
| 24 | /* Hardware control for EF10 architecture including 'Huntington'. */ |
| 25 | |
| 26 | #define EFX_EF10_DRVGEN_EV 7 |
| 27 | enum { |
| 28 | EFX_EF10_TEST = 1, |
| 29 | EFX_EF10_REFILL, |
| 30 | }; |
| 31 | |
| 32 | /* The reserved RSS context value */ |
| 33 | #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff |
| 34 | |
| 35 | /* The filter table(s) are managed by firmware and we have write-only |
| 36 | * access. When removing filters we must identify them to the |
| 37 | * firmware by a 64-bit handle, but this is too wide for Linux kernel |
| 38 | * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to |
| 39 | * be able to tell in advance whether a requested insertion will |
| 40 | * replace an existing filter. Therefore we maintain a software hash |
| 41 | * table, which should be at least as large as the hardware hash |
| 42 | * table. |
| 43 | * |
| 44 | * Huntington has a single 8K filter table shared between all filter |
| 45 | * types and both ports. |
| 46 | */ |
| 47 | #define HUNT_FILTER_TBL_ROWS 8192 |
| 48 | |
| 49 | struct efx_ef10_filter_table { |
| 50 | /* The RX match field masks supported by this fw & hw, in order of priority */ |
| 51 | enum efx_filter_match_flags rx_match_flags[ |
| 52 | MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; |
| 53 | unsigned int rx_match_count; |
| 54 | |
| 55 | struct { |
| 56 | unsigned long spec; /* pointer to spec plus flag bits */ |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 57 | /* BUSY flag indicates that an update is in progress. AUTO_OLD is |
| 58 | * used to mark and sweep MAC filters for the device address lists. |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 59 | */ |
| 60 | #define EFX_EF10_FILTER_FLAG_BUSY 1UL |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 61 | #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 62 | #define EFX_EF10_FILTER_FLAGS 3UL |
| 63 | u64 handle; /* firmware handle */ |
| 64 | } *entry; |
| 65 | wait_queue_head_t waitq; |
| 66 | /* Shadow of net_device address lists, guarded by mac_lock */ |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 67 | #define EFX_EF10_FILTER_DEV_UC_MAX 32 |
| 68 | #define EFX_EF10_FILTER_DEV_MC_MAX 256 |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 69 | struct { |
| 70 | u8 addr[ETH_ALEN]; |
| 71 | u16 id; |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 72 | } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX], |
| 73 | dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; |
| 74 | int dev_uc_count; /* negative for PROMISC */ |
| 75 | int dev_mc_count; /* negative for PROMISC/ALLMULTI */ |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | /* An arbitrary search limit for the software hash table */ |
| 79 | #define EFX_EF10_FILTER_SEARCH_LIMIT 200 |
| 80 | |
Andrew Rybchenko | d43050c | 2013-11-14 09:00:27 +0400 | [diff] [blame] | 81 | static void efx_ef10_rx_push_rss_config(struct efx_nic *efx); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 82 | static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); |
| 83 | static void efx_ef10_filter_table_remove(struct efx_nic *efx); |
| 84 | |
| 85 | static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) |
| 86 | { |
| 87 | efx_dword_t reg; |
| 88 | |
| 89 | efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); |
| 90 | return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? |
| 91 | EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; |
| 92 | } |
| 93 | |
| 94 | static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) |
| 95 | { |
| 96 | return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]); |
| 97 | } |
| 98 | |
Ben Hutchings | e5a2538 | 2013-09-05 22:50:59 +0100 | [diff] [blame] | 99 | static int efx_ef10_init_datapath_caps(struct efx_nic *efx) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 100 | { |
| 101 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); |
| 102 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 103 | size_t outlen; |
| 104 | int rc; |
| 105 | |
| 106 | BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); |
| 107 | |
| 108 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, |
| 109 | outbuf, sizeof(outbuf), &outlen); |
| 110 | if (rc) |
| 111 | return rc; |
Ben Hutchings | e5a2538 | 2013-09-05 22:50:59 +0100 | [diff] [blame] | 112 | if (outlen < sizeof(outbuf)) { |
| 113 | netif_err(efx, drv, efx->net_dev, |
| 114 | "unable to read datapath firmware capabilities\n"); |
| 115 | return -EIO; |
| 116 | } |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 117 | |
Ben Hutchings | e5a2538 | 2013-09-05 22:50:59 +0100 | [diff] [blame] | 118 | nic_data->datapath_caps = |
| 119 | MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); |
| 120 | |
Daniel Pieczko | 8d9f9dd | 2015-05-06 00:56:55 +0100 | [diff] [blame] | 121 | /* record the DPCPU firmware IDs to determine VEB vswitching support. |
| 122 | */ |
| 123 | nic_data->rx_dpcpu_fw_id = |
| 124 | MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); |
| 125 | nic_data->tx_dpcpu_fw_id = |
| 126 | MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); |
| 127 | |
Ben Hutchings | e5a2538 | 2013-09-05 22:50:59 +0100 | [diff] [blame] | 128 | if (!(nic_data->datapath_caps & |
| 129 | (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { |
| 130 | netif_err(efx, drv, efx->net_dev, |
| 131 | "current firmware does not support TSO\n"); |
| 132 | return -ENODEV; |
| 133 | } |
| 134 | |
| 135 | if (!(nic_data->datapath_caps & |
| 136 | (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { |
| 137 | netif_err(efx, probe, efx->net_dev, |
| 138 | "current firmware does not support an RX prefix\n"); |
| 139 | return -ENODEV; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) |
| 146 | { |
| 147 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); |
| 148 | int rc; |
| 149 | |
| 150 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, |
| 151 | outbuf, sizeof(outbuf), NULL); |
| 152 | if (rc) |
| 153 | return rc; |
| 154 | rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); |
| 155 | return rc > 0 ? rc : -ERANGE; |
| 156 | } |
| 157 | |
| 158 | static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address) |
| 159 | { |
| 160 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); |
| 161 | size_t outlen; |
| 162 | int rc; |
| 163 | |
| 164 | BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); |
| 165 | |
| 166 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, |
| 167 | outbuf, sizeof(outbuf), &outlen); |
| 168 | if (rc) |
| 169 | return rc; |
| 170 | if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) |
| 171 | return -EIO; |
| 172 | |
Edward Cree | cd84ff4 | 2014-03-07 18:27:41 +0000 | [diff] [blame] | 173 | ether_addr_copy(mac_address, |
| 174 | MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | static int efx_ef10_probe(struct efx_nic *efx) |
| 179 | { |
| 180 | struct efx_ef10_nic_data *nic_data; |
| 181 | int i, rc; |
| 182 | |
Ben Hutchings | aa3930e | 2014-02-12 18:59:19 +0000 | [diff] [blame] | 183 | /* We can have one VI for each 8K region. However, until we |
| 184 | * use TX option descriptors we need two TX queues per channel. |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 185 | */ |
| 186 | efx->max_channels = |
| 187 | min_t(unsigned int, |
| 188 | EFX_MAX_CHANNELS, |
| 189 | resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) / |
| 190 | (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); |
Edward Cree | 9fd3d3a | 2014-11-03 14:14:35 +0000 | [diff] [blame] | 191 | if (WARN_ON(efx->max_channels == 0)) |
| 192 | return -EIO; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 193 | |
| 194 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); |
| 195 | if (!nic_data) |
| 196 | return -ENOMEM; |
| 197 | efx->nic_data = nic_data; |
| 198 | |
| 199 | rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, |
| 200 | 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); |
| 201 | if (rc) |
| 202 | goto fail1; |
| 203 | |
| 204 | /* Get the MC's warm boot count. In case it's rebooting right |
| 205 | * now, be prepared to retry. |
| 206 | */ |
| 207 | i = 0; |
| 208 | for (;;) { |
| 209 | rc = efx_ef10_get_warm_boot_count(efx); |
| 210 | if (rc >= 0) |
| 211 | break; |
| 212 | if (++i == 5) |
| 213 | goto fail2; |
| 214 | ssleep(1); |
| 215 | } |
| 216 | nic_data->warm_boot_count = rc; |
| 217 | |
| 218 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; |
| 219 | |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 220 | nic_data->vport_id = EVB_PORT_ID_ASSIGNED; |
| 221 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 222 | /* In case we're recovering from a crash (kexec), we want to |
| 223 | * cancel any outstanding request by the previous user of this |
| 224 | * function. We send a special message using the least |
| 225 | * significant bits of the 'high' (doorbell) register. |
| 226 | */ |
| 227 | _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); |
| 228 | |
| 229 | rc = efx_mcdi_init(efx); |
| 230 | if (rc) |
| 231 | goto fail2; |
| 232 | |
| 233 | /* Reset (most) configuration for this function */ |
| 234 | rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); |
| 235 | if (rc) |
| 236 | goto fail3; |
| 237 | |
| 238 | /* Enable event logging */ |
| 239 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); |
| 240 | if (rc) |
| 241 | goto fail3; |
| 242 | |
Ben Hutchings | e5a2538 | 2013-09-05 22:50:59 +0100 | [diff] [blame] | 243 | rc = efx_ef10_init_datapath_caps(efx); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 244 | if (rc < 0) |
| 245 | goto fail3; |
| 246 | |
| 247 | efx->rx_packet_len_offset = |
| 248 | ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; |
| 249 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 250 | rc = efx_mcdi_port_get_number(efx); |
| 251 | if (rc < 0) |
| 252 | goto fail3; |
| 253 | efx->port_num = rc; |
| 254 | |
| 255 | rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr); |
| 256 | if (rc) |
| 257 | goto fail3; |
| 258 | |
| 259 | rc = efx_ef10_get_sysclk_freq(efx); |
| 260 | if (rc < 0) |
| 261 | goto fail3; |
| 262 | efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ |
| 263 | |
| 264 | /* Check whether firmware supports bug 35388 workaround */ |
| 265 | rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true); |
| 266 | if (rc == 0) |
| 267 | nic_data->workaround_35388 = true; |
| 268 | else if (rc != -ENOSYS && rc != -ENOENT) |
| 269 | goto fail3; |
| 270 | netif_dbg(efx, probe, efx->net_dev, |
| 271 | "workaround for bug 35388 is %sabled\n", |
| 272 | nic_data->workaround_35388 ? "en" : "dis"); |
| 273 | |
| 274 | rc = efx_mcdi_mon_probe(efx); |
| 275 | if (rc) |
| 276 | goto fail3; |
| 277 | |
Ben Hutchings | 9aecda9 | 2013-12-05 21:28:42 +0000 | [diff] [blame] | 278 | efx_ptp_probe(efx, NULL); |
| 279 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 280 | return 0; |
| 281 | |
| 282 | fail3: |
| 283 | efx_mcdi_fini(efx); |
| 284 | fail2: |
| 285 | efx_nic_free_buffer(efx, &nic_data->mcdi_buf); |
| 286 | fail1: |
| 287 | kfree(nic_data); |
| 288 | efx->nic_data = NULL; |
| 289 | return rc; |
| 290 | } |
| 291 | |
| 292 | static int efx_ef10_free_vis(struct efx_nic *efx) |
| 293 | { |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 294 | MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0); |
| 295 | size_t outlen; |
| 296 | int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, |
| 297 | outbuf, sizeof(outbuf), &outlen); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 298 | |
| 299 | /* -EALREADY means nothing to free, so ignore */ |
| 300 | if (rc == -EALREADY) |
| 301 | rc = 0; |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 302 | if (rc) |
| 303 | efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, |
| 304 | rc); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 305 | return rc; |
| 306 | } |
| 307 | |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 308 | #ifdef EFX_USE_PIO |
| 309 | |
| 310 | static void efx_ef10_free_piobufs(struct efx_nic *efx) |
| 311 | { |
| 312 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 313 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); |
| 314 | unsigned int i; |
| 315 | int rc; |
| 316 | |
| 317 | BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); |
| 318 | |
| 319 | for (i = 0; i < nic_data->n_piobufs; i++) { |
| 320 | MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, |
| 321 | nic_data->piobuf_handle[i]); |
| 322 | rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), |
| 323 | NULL, 0, NULL); |
| 324 | WARN_ON(rc); |
| 325 | } |
| 326 | |
| 327 | nic_data->n_piobufs = 0; |
| 328 | } |
| 329 | |
| 330 | static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) |
| 331 | { |
| 332 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 333 | MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); |
| 334 | unsigned int i; |
| 335 | size_t outlen; |
| 336 | int rc = 0; |
| 337 | |
| 338 | BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); |
| 339 | |
| 340 | for (i = 0; i < n; i++) { |
| 341 | rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, |
| 342 | outbuf, sizeof(outbuf), &outlen); |
| 343 | if (rc) |
| 344 | break; |
| 345 | if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { |
| 346 | rc = -EIO; |
| 347 | break; |
| 348 | } |
| 349 | nic_data->piobuf_handle[i] = |
| 350 | MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); |
| 351 | netif_dbg(efx, probe, efx->net_dev, |
| 352 | "allocated PIO buffer %u handle %x\n", i, |
| 353 | nic_data->piobuf_handle[i]); |
| 354 | } |
| 355 | |
| 356 | nic_data->n_piobufs = i; |
| 357 | if (rc) |
| 358 | efx_ef10_free_piobufs(efx); |
| 359 | return rc; |
| 360 | } |
| 361 | |
| 362 | static int efx_ef10_link_piobufs(struct efx_nic *efx) |
| 363 | { |
| 364 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 365 | MCDI_DECLARE_BUF(inbuf, |
| 366 | max(MC_CMD_LINK_PIOBUF_IN_LEN, |
| 367 | MC_CMD_UNLINK_PIOBUF_IN_LEN)); |
| 368 | struct efx_channel *channel; |
| 369 | struct efx_tx_queue *tx_queue; |
| 370 | unsigned int offset, index; |
| 371 | int rc; |
| 372 | |
| 373 | BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); |
| 374 | BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); |
| 375 | |
| 376 | /* Link a buffer to each VI in the write-combining mapping */ |
| 377 | for (index = 0; index < nic_data->n_piobufs; ++index) { |
| 378 | MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, |
| 379 | nic_data->piobuf_handle[index]); |
| 380 | MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, |
| 381 | nic_data->pio_write_vi_base + index); |
| 382 | rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, |
| 383 | inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, |
| 384 | NULL, 0, NULL); |
| 385 | if (rc) { |
| 386 | netif_err(efx, drv, efx->net_dev, |
| 387 | "failed to link VI %u to PIO buffer %u (%d)\n", |
| 388 | nic_data->pio_write_vi_base + index, index, |
| 389 | rc); |
| 390 | goto fail; |
| 391 | } |
| 392 | netif_dbg(efx, probe, efx->net_dev, |
| 393 | "linked VI %u to PIO buffer %u\n", |
| 394 | nic_data->pio_write_vi_base + index, index); |
| 395 | } |
| 396 | |
| 397 | /* Link a buffer to each TX queue */ |
| 398 | efx_for_each_channel(channel, efx) { |
| 399 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
| 400 | /* We assign the PIO buffers to queues in |
| 401 | * reverse order to allow for the following |
| 402 | * special case. |
| 403 | */ |
| 404 | offset = ((efx->tx_channel_offset + efx->n_tx_channels - |
| 405 | tx_queue->channel->channel - 1) * |
| 406 | efx_piobuf_size); |
| 407 | index = offset / ER_DZ_TX_PIOBUF_SIZE; |
| 408 | offset = offset % ER_DZ_TX_PIOBUF_SIZE; |
| 409 | |
| 410 | /* When the host page size is 4K, the first |
| 411 | * host page in the WC mapping may be within |
| 412 | * the same VI page as the last TX queue. We |
| 413 | * can only link one buffer to each VI. |
| 414 | */ |
| 415 | if (tx_queue->queue == nic_data->pio_write_vi_base) { |
| 416 | BUG_ON(index != 0); |
| 417 | rc = 0; |
| 418 | } else { |
| 419 | MCDI_SET_DWORD(inbuf, |
| 420 | LINK_PIOBUF_IN_PIOBUF_HANDLE, |
| 421 | nic_data->piobuf_handle[index]); |
| 422 | MCDI_SET_DWORD(inbuf, |
| 423 | LINK_PIOBUF_IN_TXQ_INSTANCE, |
| 424 | tx_queue->queue); |
| 425 | rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, |
| 426 | inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, |
| 427 | NULL, 0, NULL); |
| 428 | } |
| 429 | |
| 430 | if (rc) { |
| 431 | /* This is non-fatal; the TX path just |
| 432 | * won't use PIO for this queue |
| 433 | */ |
| 434 | netif_err(efx, drv, efx->net_dev, |
| 435 | "failed to link VI %u to PIO buffer %u (%d)\n", |
| 436 | tx_queue->queue, index, rc); |
| 437 | tx_queue->piobuf = NULL; |
| 438 | } else { |
| 439 | tx_queue->piobuf = |
| 440 | nic_data->pio_write_base + |
| 441 | index * EFX_VI_PAGE_SIZE + offset; |
| 442 | tx_queue->piobuf_offset = offset; |
| 443 | netif_dbg(efx, probe, efx->net_dev, |
| 444 | "linked VI %u to PIO buffer %u offset %x addr %p\n", |
| 445 | tx_queue->queue, index, |
| 446 | tx_queue->piobuf_offset, |
| 447 | tx_queue->piobuf); |
| 448 | } |
| 449 | } |
| 450 | } |
| 451 | |
| 452 | return 0; |
| 453 | |
| 454 | fail: |
| 455 | while (index--) { |
| 456 | MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, |
| 457 | nic_data->pio_write_vi_base + index); |
| 458 | efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, |
| 459 | inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, |
| 460 | NULL, 0, NULL); |
| 461 | } |
| 462 | return rc; |
| 463 | } |
| 464 | |
| 465 | #else /* !EFX_USE_PIO */ |
| 466 | |
| 467 | static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) |
| 468 | { |
| 469 | return n == 0 ? 0 : -ENOBUFS; |
| 470 | } |
| 471 | |
| 472 | static int efx_ef10_link_piobufs(struct efx_nic *efx) |
| 473 | { |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | static void efx_ef10_free_piobufs(struct efx_nic *efx) |
| 478 | { |
| 479 | } |
| 480 | |
| 481 | #endif /* EFX_USE_PIO */ |
| 482 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 483 | static void efx_ef10_remove(struct efx_nic *efx) |
| 484 | { |
| 485 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 486 | int rc; |
| 487 | |
Ben Hutchings | 9aecda9 | 2013-12-05 21:28:42 +0000 | [diff] [blame] | 488 | efx_ptp_remove(efx); |
| 489 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 490 | efx_mcdi_mon_remove(efx); |
| 491 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 492 | efx_ef10_rx_free_indir_table(efx); |
| 493 | |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 494 | if (nic_data->wc_membase) |
| 495 | iounmap(nic_data->wc_membase); |
| 496 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 497 | rc = efx_ef10_free_vis(efx); |
| 498 | WARN_ON(rc != 0); |
| 499 | |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 500 | if (!nic_data->must_restore_piobufs) |
| 501 | efx_ef10_free_piobufs(efx); |
| 502 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 503 | efx_mcdi_fini(efx); |
| 504 | efx_nic_free_buffer(efx, &nic_data->mcdi_buf); |
| 505 | kfree(nic_data); |
| 506 | } |
| 507 | |
| 508 | static int efx_ef10_alloc_vis(struct efx_nic *efx, |
| 509 | unsigned int min_vis, unsigned int max_vis) |
| 510 | { |
| 511 | MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); |
| 512 | MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); |
| 513 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 514 | size_t outlen; |
| 515 | int rc; |
| 516 | |
| 517 | MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); |
| 518 | MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); |
| 519 | rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), |
| 520 | outbuf, sizeof(outbuf), &outlen); |
| 521 | if (rc != 0) |
| 522 | return rc; |
| 523 | |
| 524 | if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) |
| 525 | return -EIO; |
| 526 | |
| 527 | netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", |
| 528 | MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); |
| 529 | |
| 530 | nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); |
| 531 | nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); |
| 532 | return 0; |
| 533 | } |
| 534 | |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 535 | /* Note that the failure path of this function does not free |
| 536 | * resources, as this will be done by efx_ef10_remove(). |
| 537 | */ |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 538 | static int efx_ef10_dimension_resources(struct efx_nic *efx) |
| 539 | { |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 540 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 541 | unsigned int uc_mem_map_size, wc_mem_map_size; |
| 542 | unsigned int min_vis, pio_write_vi_base, max_vis; |
| 543 | void __iomem *membase; |
| 544 | int rc; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 545 | |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 546 | min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); |
| 547 | |
| 548 | #ifdef EFX_USE_PIO |
| 549 | /* Try to allocate PIO buffers if wanted and if the full |
| 550 | * number of PIO buffers would be sufficient to allocate one |
| 551 | * copy-buffer per TX channel. Failure is non-fatal, as there |
| 552 | * are only a small number of PIO buffers shared between all |
| 553 | * functions of the controller. |
| 554 | */ |
| 555 | if (efx_piobuf_size != 0 && |
| 556 | ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= |
| 557 | efx->n_tx_channels) { |
| 558 | unsigned int n_piobufs = |
| 559 | DIV_ROUND_UP(efx->n_tx_channels, |
| 560 | ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); |
| 561 | |
| 562 | rc = efx_ef10_alloc_piobufs(efx, n_piobufs); |
| 563 | if (rc) |
| 564 | netif_err(efx, probe, efx->net_dev, |
| 565 | "failed to allocate PIO buffers (%d)\n", rc); |
| 566 | else |
| 567 | netif_dbg(efx, probe, efx->net_dev, |
| 568 | "allocated %u PIO buffers\n", n_piobufs); |
| 569 | } |
| 570 | #else |
| 571 | nic_data->n_piobufs = 0; |
| 572 | #endif |
| 573 | |
| 574 | /* PIO buffers should be mapped with write-combining enabled, |
| 575 | * and we want to make single UC and WC mappings rather than |
| 576 | * several of each (in fact that's the only option if host |
| 577 | * page size is >4K). So we may allocate some extra VIs just |
| 578 | * for writing PIO buffers through. |
Daniel Pieczko | 52ad762 | 2014-04-01 13:10:34 +0100 | [diff] [blame] | 579 | * |
| 580 | * The UC mapping contains (min_vis - 1) complete VIs and the |
| 581 | * first half of the next VI. Then the WC mapping begins with |
| 582 | * the second half of this last VI. |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 583 | */ |
| 584 | uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + |
| 585 | ER_DZ_TX_PIOBUF); |
| 586 | if (nic_data->n_piobufs) { |
Daniel Pieczko | 52ad762 | 2014-04-01 13:10:34 +0100 | [diff] [blame] | 587 | /* pio_write_vi_base rounds down to give the number of complete |
| 588 | * VIs inside the UC mapping. |
| 589 | */ |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 590 | pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; |
| 591 | wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + |
| 592 | nic_data->n_piobufs) * |
| 593 | EFX_VI_PAGE_SIZE) - |
| 594 | uc_mem_map_size); |
| 595 | max_vis = pio_write_vi_base + nic_data->n_piobufs; |
| 596 | } else { |
| 597 | pio_write_vi_base = 0; |
| 598 | wc_mem_map_size = 0; |
| 599 | max_vis = min_vis; |
| 600 | } |
| 601 | |
| 602 | /* In case the last attached driver failed to free VIs, do it now */ |
| 603 | rc = efx_ef10_free_vis(efx); |
| 604 | if (rc != 0) |
| 605 | return rc; |
| 606 | |
| 607 | rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); |
| 608 | if (rc != 0) |
| 609 | return rc; |
| 610 | |
| 611 | /* If we didn't get enough VIs to map all the PIO buffers, free the |
| 612 | * PIO buffers |
| 613 | */ |
| 614 | if (nic_data->n_piobufs && |
| 615 | nic_data->n_allocated_vis < |
| 616 | pio_write_vi_base + nic_data->n_piobufs) { |
| 617 | netif_dbg(efx, probe, efx->net_dev, |
| 618 | "%u VIs are not sufficient to map %u PIO buffers\n", |
| 619 | nic_data->n_allocated_vis, nic_data->n_piobufs); |
| 620 | efx_ef10_free_piobufs(efx); |
| 621 | } |
| 622 | |
| 623 | /* Shrink the original UC mapping of the memory BAR */ |
| 624 | membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); |
| 625 | if (!membase) { |
| 626 | netif_err(efx, probe, efx->net_dev, |
| 627 | "could not shrink memory BAR to %x\n", |
| 628 | uc_mem_map_size); |
| 629 | return -ENOMEM; |
| 630 | } |
| 631 | iounmap(efx->membase); |
| 632 | efx->membase = membase; |
| 633 | |
| 634 | /* Set up the WC mapping if needed */ |
| 635 | if (wc_mem_map_size) { |
| 636 | nic_data->wc_membase = ioremap_wc(efx->membase_phys + |
| 637 | uc_mem_map_size, |
| 638 | wc_mem_map_size); |
| 639 | if (!nic_data->wc_membase) { |
| 640 | netif_err(efx, probe, efx->net_dev, |
| 641 | "could not allocate WC mapping of size %x\n", |
| 642 | wc_mem_map_size); |
| 643 | return -ENOMEM; |
| 644 | } |
| 645 | nic_data->pio_write_vi_base = pio_write_vi_base; |
| 646 | nic_data->pio_write_base = |
| 647 | nic_data->wc_membase + |
| 648 | (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - |
| 649 | uc_mem_map_size); |
| 650 | |
| 651 | rc = efx_ef10_link_piobufs(efx); |
| 652 | if (rc) |
| 653 | efx_ef10_free_piobufs(efx); |
| 654 | } |
| 655 | |
| 656 | netif_dbg(efx, probe, efx->net_dev, |
| 657 | "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", |
| 658 | &efx->membase_phys, efx->membase, uc_mem_map_size, |
| 659 | nic_data->wc_membase, wc_mem_map_size); |
| 660 | |
| 661 | return 0; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 662 | } |
| 663 | |
| 664 | static int efx_ef10_init_nic(struct efx_nic *efx) |
| 665 | { |
| 666 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 667 | int rc; |
| 668 | |
Ben Hutchings | a915ccc | 2013-09-05 22:51:55 +0100 | [diff] [blame] | 669 | if (nic_data->must_check_datapath_caps) { |
| 670 | rc = efx_ef10_init_datapath_caps(efx); |
| 671 | if (rc) |
| 672 | return rc; |
| 673 | nic_data->must_check_datapath_caps = false; |
| 674 | } |
| 675 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 676 | if (nic_data->must_realloc_vis) { |
| 677 | /* We cannot let the number of VIs change now */ |
| 678 | rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, |
| 679 | nic_data->n_allocated_vis); |
| 680 | if (rc) |
| 681 | return rc; |
| 682 | nic_data->must_realloc_vis = false; |
| 683 | } |
| 684 | |
Ben Hutchings | 183233b | 2013-06-28 21:47:12 +0100 | [diff] [blame] | 685 | if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { |
| 686 | rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); |
| 687 | if (rc == 0) { |
| 688 | rc = efx_ef10_link_piobufs(efx); |
| 689 | if (rc) |
| 690 | efx_ef10_free_piobufs(efx); |
| 691 | } |
| 692 | |
| 693 | /* Log an error on failure, but this is non-fatal */ |
| 694 | if (rc) |
| 695 | netif_err(efx, drv, efx->net_dev, |
| 696 | "failed to restore PIO buffers (%d)\n", rc); |
| 697 | nic_data->must_restore_piobufs = false; |
| 698 | } |
| 699 | |
Andrew Rybchenko | d43050c | 2013-11-14 09:00:27 +0400 | [diff] [blame] | 700 | efx_ef10_rx_push_rss_config(efx); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 701 | return 0; |
| 702 | } |
| 703 | |
Jon Cooper | 3e33626 | 2014-01-17 19:48:06 +0000 | [diff] [blame] | 704 | static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) |
| 705 | { |
| 706 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 707 | |
| 708 | /* All our allocations have been reset */ |
| 709 | nic_data->must_realloc_vis = true; |
| 710 | nic_data->must_restore_filters = true; |
| 711 | nic_data->must_restore_piobufs = true; |
| 712 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; |
| 713 | } |
| 714 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 715 | static int efx_ef10_map_reset_flags(u32 *flags) |
| 716 | { |
| 717 | enum { |
| 718 | EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << |
| 719 | ETH_RESET_SHARED_SHIFT), |
| 720 | EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | |
| 721 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | |
| 722 | ETH_RESET_PHY | ETH_RESET_MGMT) << |
| 723 | ETH_RESET_SHARED_SHIFT) |
| 724 | }; |
| 725 | |
| 726 | /* We assume for now that our PCI function is permitted to |
| 727 | * reset everything. |
| 728 | */ |
| 729 | |
| 730 | if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { |
| 731 | *flags &= ~EF10_RESET_MC; |
| 732 | return RESET_TYPE_WORLD; |
| 733 | } |
| 734 | |
| 735 | if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { |
| 736 | *flags &= ~EF10_RESET_PORT; |
| 737 | return RESET_TYPE_ALL; |
| 738 | } |
| 739 | |
| 740 | /* no invisible reset implemented */ |
| 741 | |
| 742 | return -EINVAL; |
| 743 | } |
| 744 | |
Jon Cooper | 3e33626 | 2014-01-17 19:48:06 +0000 | [diff] [blame] | 745 | static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) |
| 746 | { |
| 747 | int rc = efx_mcdi_reset(efx, reset_type); |
| 748 | |
| 749 | /* If it was a port reset, trigger reallocation of MC resources. |
| 750 | * Note that on an MC reset nothing needs to be done now because we'll |
| 751 | * detect the MC reset later and handle it then. |
Edward Cree | e283546 | 2014-04-16 19:27:48 +0100 | [diff] [blame] | 752 | * For an FLR, we never get an MC reset event, but the MC has reset all |
| 753 | * resources assigned to us, so we have to trigger reallocation now. |
Jon Cooper | 3e33626 | 2014-01-17 19:48:06 +0000 | [diff] [blame] | 754 | */ |
Edward Cree | e283546 | 2014-04-16 19:27:48 +0100 | [diff] [blame] | 755 | if ((reset_type == RESET_TYPE_ALL || |
| 756 | reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) |
Jon Cooper | 3e33626 | 2014-01-17 19:48:06 +0000 | [diff] [blame] | 757 | efx_ef10_reset_mc_allocations(efx); |
| 758 | return rc; |
| 759 | } |
| 760 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 761 | #define EF10_DMA_STAT(ext_name, mcdi_name) \ |
| 762 | [EF10_STAT_ ## ext_name] = \ |
| 763 | { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } |
| 764 | #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ |
| 765 | [EF10_STAT_ ## int_name] = \ |
| 766 | { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } |
| 767 | #define EF10_OTHER_STAT(ext_name) \ |
| 768 | [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } |
Edward Cree | e4d112e | 2014-07-15 11:58:12 +0100 | [diff] [blame] | 769 | #define GENERIC_SW_STAT(ext_name) \ |
| 770 | [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 771 | |
| 772 | static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { |
| 773 | EF10_DMA_STAT(tx_bytes, TX_BYTES), |
| 774 | EF10_DMA_STAT(tx_packets, TX_PKTS), |
| 775 | EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS), |
| 776 | EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS), |
| 777 | EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), |
| 778 | EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), |
| 779 | EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), |
| 780 | EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS), |
| 781 | EF10_DMA_STAT(tx_64, TX_64_PKTS), |
| 782 | EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), |
| 783 | EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), |
| 784 | EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), |
| 785 | EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), |
| 786 | EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), |
| 787 | EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), |
| 788 | EF10_DMA_STAT(rx_bytes, RX_BYTES), |
| 789 | EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES), |
| 790 | EF10_OTHER_STAT(rx_good_bytes), |
| 791 | EF10_OTHER_STAT(rx_bad_bytes), |
| 792 | EF10_DMA_STAT(rx_packets, RX_PKTS), |
| 793 | EF10_DMA_STAT(rx_good, RX_GOOD_PKTS), |
| 794 | EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), |
| 795 | EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS), |
| 796 | EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS), |
| 797 | EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), |
| 798 | EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), |
| 799 | EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), |
| 800 | EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), |
| 801 | EF10_DMA_STAT(rx_64, RX_64_PKTS), |
| 802 | EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), |
| 803 | EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), |
| 804 | EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), |
| 805 | EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), |
| 806 | EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), |
| 807 | EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), |
| 808 | EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), |
| 809 | EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), |
| 810 | EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), |
| 811 | EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), |
| 812 | EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), |
| 813 | EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS), |
Edward Cree | e4d112e | 2014-07-15 11:58:12 +0100 | [diff] [blame] | 814 | GENERIC_SW_STAT(rx_nodesc_trunc), |
| 815 | GENERIC_SW_STAT(rx_noskb_drops), |
Edward Cree | 568d7a0 | 2013-09-25 17:32:09 +0100 | [diff] [blame] | 816 | EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), |
| 817 | EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), |
| 818 | EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), |
| 819 | EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), |
| 820 | EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB), |
| 821 | EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB), |
| 822 | EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING), |
| 823 | EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), |
| 824 | EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), |
| 825 | EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS), |
Shradha Shah | 79ac47a | 2013-11-28 18:48:49 +0000 | [diff] [blame] | 826 | EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS), |
| 827 | EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS), |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 828 | }; |
| 829 | |
| 830 | #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \ |
| 831 | (1ULL << EF10_STAT_tx_packets) | \ |
| 832 | (1ULL << EF10_STAT_tx_pause) | \ |
| 833 | (1ULL << EF10_STAT_tx_unicast) | \ |
| 834 | (1ULL << EF10_STAT_tx_multicast) | \ |
| 835 | (1ULL << EF10_STAT_tx_broadcast) | \ |
| 836 | (1ULL << EF10_STAT_rx_bytes) | \ |
| 837 | (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \ |
| 838 | (1ULL << EF10_STAT_rx_good_bytes) | \ |
| 839 | (1ULL << EF10_STAT_rx_bad_bytes) | \ |
| 840 | (1ULL << EF10_STAT_rx_packets) | \ |
| 841 | (1ULL << EF10_STAT_rx_good) | \ |
| 842 | (1ULL << EF10_STAT_rx_bad) | \ |
| 843 | (1ULL << EF10_STAT_rx_pause) | \ |
| 844 | (1ULL << EF10_STAT_rx_control) | \ |
| 845 | (1ULL << EF10_STAT_rx_unicast) | \ |
| 846 | (1ULL << EF10_STAT_rx_multicast) | \ |
| 847 | (1ULL << EF10_STAT_rx_broadcast) | \ |
| 848 | (1ULL << EF10_STAT_rx_lt64) | \ |
| 849 | (1ULL << EF10_STAT_rx_64) | \ |
| 850 | (1ULL << EF10_STAT_rx_65_to_127) | \ |
| 851 | (1ULL << EF10_STAT_rx_128_to_255) | \ |
| 852 | (1ULL << EF10_STAT_rx_256_to_511) | \ |
| 853 | (1ULL << EF10_STAT_rx_512_to_1023) | \ |
| 854 | (1ULL << EF10_STAT_rx_1024_to_15xx) | \ |
| 855 | (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \ |
| 856 | (1ULL << EF10_STAT_rx_gtjumbo) | \ |
| 857 | (1ULL << EF10_STAT_rx_bad_gtjumbo) | \ |
| 858 | (1ULL << EF10_STAT_rx_overflow) | \ |
Edward Cree | e4d112e | 2014-07-15 11:58:12 +0100 | [diff] [blame] | 859 | (1ULL << EF10_STAT_rx_nodesc_drops) | \ |
| 860 | (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ |
| 861 | (1ULL << GENERIC_STAT_rx_noskb_drops)) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 862 | |
| 863 | /* These statistics are only provided by the 10G MAC. For a 10G/40G |
| 864 | * switchable port we do not expose these because they might not |
| 865 | * include all the packets they should. |
| 866 | */ |
| 867 | #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \ |
| 868 | (1ULL << EF10_STAT_tx_lt64) | \ |
| 869 | (1ULL << EF10_STAT_tx_64) | \ |
| 870 | (1ULL << EF10_STAT_tx_65_to_127) | \ |
| 871 | (1ULL << EF10_STAT_tx_128_to_255) | \ |
| 872 | (1ULL << EF10_STAT_tx_256_to_511) | \ |
| 873 | (1ULL << EF10_STAT_tx_512_to_1023) | \ |
| 874 | (1ULL << EF10_STAT_tx_1024_to_15xx) | \ |
| 875 | (1ULL << EF10_STAT_tx_15xx_to_jumbo)) |
| 876 | |
| 877 | /* These statistics are only provided by the 40G MAC. For a 10G/40G |
| 878 | * switchable port we do expose these because the errors will otherwise |
| 879 | * be silent. |
| 880 | */ |
| 881 | #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \ |
| 882 | (1ULL << EF10_STAT_rx_length_error)) |
| 883 | |
Edward Cree | 568d7a0 | 2013-09-25 17:32:09 +0100 | [diff] [blame] | 884 | /* These statistics are only provided if the firmware supports the |
| 885 | * capability PM_AND_RXDP_COUNTERS. |
| 886 | */ |
| 887 | #define HUNT_PM_AND_RXDP_STAT_MASK ( \ |
| 888 | (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \ |
| 889 | (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \ |
| 890 | (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \ |
| 891 | (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \ |
| 892 | (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \ |
| 893 | (1ULL << EF10_STAT_rx_pm_discard_qbb) | \ |
| 894 | (1ULL << EF10_STAT_rx_pm_discard_mapping) | \ |
| 895 | (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \ |
| 896 | (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \ |
| 897 | (1ULL << EF10_STAT_rx_dp_streaming_packets) | \ |
Shradha Shah | 79ac47a | 2013-11-28 18:48:49 +0000 | [diff] [blame] | 898 | (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \ |
| 899 | (1ULL << EF10_STAT_rx_dp_hlb_wait)) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 900 | |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 901 | static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 902 | { |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 903 | u64 raw_mask = HUNT_COMMON_STAT_MASK; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 904 | u32 port_caps = efx_mcdi_phy_get_caps(efx); |
Edward Cree | 568d7a0 | 2013-09-25 17:32:09 +0100 | [diff] [blame] | 905 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 906 | |
| 907 | if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 908 | raw_mask |= HUNT_40G_EXTRA_STAT_MASK; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 909 | else |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 910 | raw_mask |= HUNT_10G_ONLY_STAT_MASK; |
Edward Cree | 568d7a0 | 2013-09-25 17:32:09 +0100 | [diff] [blame] | 911 | |
| 912 | if (nic_data->datapath_caps & |
| 913 | (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) |
| 914 | raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; |
| 915 | |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 916 | return raw_mask; |
| 917 | } |
| 918 | |
| 919 | static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) |
| 920 | { |
| 921 | u64 raw_mask = efx_ef10_raw_stat_mask(efx); |
| 922 | |
| 923 | #if BITS_PER_LONG == 64 |
| 924 | mask[0] = raw_mask; |
| 925 | #else |
| 926 | mask[0] = raw_mask & 0xffffffff; |
| 927 | mask[1] = raw_mask >> 32; |
| 928 | #endif |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) |
| 932 | { |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 933 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
| 934 | |
| 935 | efx_ef10_get_stat_mask(efx, mask); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 936 | return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 937 | mask, names); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | static int efx_ef10_try_update_nic_stats(struct efx_nic *efx) |
| 941 | { |
| 942 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 943 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 944 | __le64 generation_start, generation_end; |
| 945 | u64 *stats = nic_data->stats; |
| 946 | __le64 *dma_stats; |
| 947 | |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 948 | efx_ef10_get_stat_mask(efx, mask); |
| 949 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 950 | dma_stats = efx->stats_buffer.addr; |
| 951 | nic_data = efx->nic_data; |
| 952 | |
| 953 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; |
| 954 | if (generation_end == EFX_MC_STATS_GENERATION_INVALID) |
| 955 | return 0; |
| 956 | rmb(); |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 957 | efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 958 | stats, efx->stats_buffer.addr, false); |
Jon Cooper | d546a89 | 2013-09-27 18:26:30 +0100 | [diff] [blame] | 959 | rmb(); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 960 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; |
| 961 | if (generation_end != generation_start) |
| 962 | return -EAGAIN; |
| 963 | |
| 964 | /* Update derived statistics */ |
Jon Cooper | f8f3b5a | 2013-09-30 17:36:50 +0100 | [diff] [blame] | 965 | efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 966 | stats[EF10_STAT_rx_good_bytes] = |
| 967 | stats[EF10_STAT_rx_bytes] - |
| 968 | stats[EF10_STAT_rx_bytes_minus_good_bytes]; |
| 969 | efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes], |
| 970 | stats[EF10_STAT_rx_bytes_minus_good_bytes]); |
Edward Cree | e4d112e | 2014-07-15 11:58:12 +0100 | [diff] [blame] | 971 | efx_update_sw_stats(efx, stats); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 972 | return 0; |
| 973 | } |
| 974 | |
| 975 | |
| 976 | static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats, |
| 977 | struct rtnl_link_stats64 *core_stats) |
| 978 | { |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 979 | DECLARE_BITMAP(mask, EF10_STAT_COUNT); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 980 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 981 | u64 *stats = nic_data->stats; |
| 982 | size_t stats_count = 0, index; |
| 983 | int retry; |
| 984 | |
Edward Cree | 4bae913 | 2013-09-27 18:52:49 +0100 | [diff] [blame] | 985 | efx_ef10_get_stat_mask(efx, mask); |
| 986 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 987 | /* If we're unlucky enough to read statistics during the DMA, wait |
| 988 | * up to 10ms for it to finish (typically takes <500us) |
| 989 | */ |
| 990 | for (retry = 0; retry < 100; ++retry) { |
| 991 | if (efx_ef10_try_update_nic_stats(efx) == 0) |
| 992 | break; |
| 993 | udelay(100); |
| 994 | } |
| 995 | |
| 996 | if (full_stats) { |
| 997 | for_each_set_bit(index, mask, EF10_STAT_COUNT) { |
| 998 | if (efx_ef10_stat_desc[index].name) { |
| 999 | *full_stats++ = stats[index]; |
| 1000 | ++stats_count; |
| 1001 | } |
| 1002 | } |
| 1003 | } |
| 1004 | |
| 1005 | if (core_stats) { |
| 1006 | core_stats->rx_packets = stats[EF10_STAT_rx_packets]; |
| 1007 | core_stats->tx_packets = stats[EF10_STAT_tx_packets]; |
| 1008 | core_stats->rx_bytes = stats[EF10_STAT_rx_bytes]; |
| 1009 | core_stats->tx_bytes = stats[EF10_STAT_tx_bytes]; |
Edward Cree | e4d112e | 2014-07-15 11:58:12 +0100 | [diff] [blame] | 1010 | core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] + |
| 1011 | stats[GENERIC_STAT_rx_nodesc_trunc] + |
| 1012 | stats[GENERIC_STAT_rx_noskb_drops]; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1013 | core_stats->multicast = stats[EF10_STAT_rx_multicast]; |
| 1014 | core_stats->rx_length_errors = |
| 1015 | stats[EF10_STAT_rx_gtjumbo] + |
| 1016 | stats[EF10_STAT_rx_length_error]; |
| 1017 | core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; |
| 1018 | core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error]; |
| 1019 | core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; |
| 1020 | core_stats->rx_errors = (core_stats->rx_length_errors + |
| 1021 | core_stats->rx_crc_errors + |
| 1022 | core_stats->rx_frame_errors); |
| 1023 | } |
| 1024 | |
| 1025 | return stats_count; |
| 1026 | } |
| 1027 | |
| 1028 | static void efx_ef10_push_irq_moderation(struct efx_channel *channel) |
| 1029 | { |
| 1030 | struct efx_nic *efx = channel->efx; |
| 1031 | unsigned int mode, value; |
| 1032 | efx_dword_t timer_cmd; |
| 1033 | |
| 1034 | if (channel->irq_moderation) { |
| 1035 | mode = 3; |
| 1036 | value = channel->irq_moderation - 1; |
| 1037 | } else { |
| 1038 | mode = 0; |
| 1039 | value = 0; |
| 1040 | } |
| 1041 | |
| 1042 | if (EFX_EF10_WORKAROUND_35388(efx)) { |
| 1043 | EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, |
| 1044 | EFE_DD_EVQ_IND_TIMER_FLAGS, |
| 1045 | ERF_DD_EVQ_IND_TIMER_MODE, mode, |
| 1046 | ERF_DD_EVQ_IND_TIMER_VAL, value); |
| 1047 | efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, |
| 1048 | channel->channel); |
| 1049 | } else { |
| 1050 | EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, |
| 1051 | ERF_DZ_TC_TIMER_VAL, value); |
| 1052 | efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, |
| 1053 | channel->channel); |
| 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) |
| 1058 | { |
| 1059 | wol->supported = 0; |
| 1060 | wol->wolopts = 0; |
| 1061 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
| 1062 | } |
| 1063 | |
| 1064 | static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) |
| 1065 | { |
| 1066 | if (type != 0) |
| 1067 | return -EINVAL; |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
| 1071 | static void efx_ef10_mcdi_request(struct efx_nic *efx, |
| 1072 | const efx_dword_t *hdr, size_t hdr_len, |
| 1073 | const efx_dword_t *sdu, size_t sdu_len) |
| 1074 | { |
| 1075 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1076 | u8 *pdu = nic_data->mcdi_buf.addr; |
| 1077 | |
| 1078 | memcpy(pdu, hdr, hdr_len); |
| 1079 | memcpy(pdu + hdr_len, sdu, sdu_len); |
| 1080 | wmb(); |
| 1081 | |
| 1082 | /* The hardware provides 'low' and 'high' (doorbell) registers |
| 1083 | * for passing the 64-bit address of an MCDI request to |
| 1084 | * firmware. However the dwords are swapped by firmware. The |
| 1085 | * least significant bits of the doorbell are then 0 for all |
| 1086 | * MCDI requests due to alignment. |
| 1087 | */ |
| 1088 | _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), |
| 1089 | ER_DZ_MC_DB_LWRD); |
| 1090 | _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), |
| 1091 | ER_DZ_MC_DB_HWRD); |
| 1092 | } |
| 1093 | |
| 1094 | static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) |
| 1095 | { |
| 1096 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1097 | const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; |
| 1098 | |
| 1099 | rmb(); |
| 1100 | return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); |
| 1101 | } |
| 1102 | |
| 1103 | static void |
| 1104 | efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, |
| 1105 | size_t offset, size_t outlen) |
| 1106 | { |
| 1107 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1108 | const u8 *pdu = nic_data->mcdi_buf.addr; |
| 1109 | |
| 1110 | memcpy(outbuf, pdu + offset, outlen); |
| 1111 | } |
| 1112 | |
| 1113 | static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) |
| 1114 | { |
| 1115 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1116 | int rc; |
| 1117 | |
| 1118 | rc = efx_ef10_get_warm_boot_count(efx); |
| 1119 | if (rc < 0) { |
| 1120 | /* The firmware is presumably in the process of |
| 1121 | * rebooting. However, we are supposed to report each |
| 1122 | * reboot just once, so we must only do that once we |
| 1123 | * can read and store the updated warm boot count. |
| 1124 | */ |
| 1125 | return 0; |
| 1126 | } |
| 1127 | |
| 1128 | if (rc == nic_data->warm_boot_count) |
| 1129 | return 0; |
| 1130 | |
| 1131 | nic_data->warm_boot_count = rc; |
| 1132 | |
| 1133 | /* All our allocations have been reset */ |
Jon Cooper | 3e33626 | 2014-01-17 19:48:06 +0000 | [diff] [blame] | 1134 | efx_ef10_reset_mc_allocations(efx); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1135 | |
Daniel Pieczko | 6d8aaaf | 2015-05-06 00:57:34 +0100 | [diff] [blame^] | 1136 | /* Driver-created vswitches and vports must be re-created */ |
| 1137 | nic_data->must_probe_vswitching = true; |
| 1138 | nic_data->vport_id = EVB_PORT_ID_ASSIGNED; |
| 1139 | |
Ben Hutchings | a915ccc | 2013-09-05 22:51:55 +0100 | [diff] [blame] | 1140 | /* The datapath firmware might have been changed */ |
| 1141 | nic_data->must_check_datapath_caps = true; |
| 1142 | |
Ben Hutchings | 869070c | 2013-09-05 22:46:10 +0100 | [diff] [blame] | 1143 | /* MAC statistics have been cleared on the NIC; clear the local |
| 1144 | * statistic that we update with efx_update_diff_stat(). |
| 1145 | */ |
| 1146 | nic_data->stats[EF10_STAT_rx_bad_bytes] = 0; |
| 1147 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1148 | return -EIO; |
| 1149 | } |
| 1150 | |
| 1151 | /* Handle an MSI interrupt |
| 1152 | * |
| 1153 | * Handle an MSI hardware interrupt. This routine schedules event |
| 1154 | * queue processing. No interrupt acknowledgement cycle is necessary. |
| 1155 | * Also, we never need to check that the interrupt is for us, since |
| 1156 | * MSI interrupts cannot be shared. |
| 1157 | */ |
| 1158 | static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) |
| 1159 | { |
| 1160 | struct efx_msi_context *context = dev_id; |
| 1161 | struct efx_nic *efx = context->efx; |
| 1162 | |
| 1163 | netif_vdbg(efx, intr, efx->net_dev, |
| 1164 | "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); |
| 1165 | |
| 1166 | if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { |
| 1167 | /* Note test interrupts */ |
| 1168 | if (context->index == efx->irq_level) |
| 1169 | efx->last_irq_cpu = raw_smp_processor_id(); |
| 1170 | |
| 1171 | /* Schedule processing of the channel */ |
| 1172 | efx_schedule_channel_irq(efx->channel[context->index]); |
| 1173 | } |
| 1174 | |
| 1175 | return IRQ_HANDLED; |
| 1176 | } |
| 1177 | |
| 1178 | static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) |
| 1179 | { |
| 1180 | struct efx_nic *efx = dev_id; |
| 1181 | bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); |
| 1182 | struct efx_channel *channel; |
| 1183 | efx_dword_t reg; |
| 1184 | u32 queues; |
| 1185 | |
| 1186 | /* Read the ISR which also ACKs the interrupts */ |
| 1187 | efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); |
| 1188 | queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); |
| 1189 | |
| 1190 | if (queues == 0) |
| 1191 | return IRQ_NONE; |
| 1192 | |
| 1193 | if (likely(soft_enabled)) { |
| 1194 | /* Note test interrupts */ |
| 1195 | if (queues & (1U << efx->irq_level)) |
| 1196 | efx->last_irq_cpu = raw_smp_processor_id(); |
| 1197 | |
| 1198 | efx_for_each_channel(channel, efx) { |
| 1199 | if (queues & 1) |
| 1200 | efx_schedule_channel_irq(channel); |
| 1201 | queues >>= 1; |
| 1202 | } |
| 1203 | } |
| 1204 | |
| 1205 | netif_vdbg(efx, intr, efx->net_dev, |
| 1206 | "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", |
| 1207 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); |
| 1208 | |
| 1209 | return IRQ_HANDLED; |
| 1210 | } |
| 1211 | |
| 1212 | static void efx_ef10_irq_test_generate(struct efx_nic *efx) |
| 1213 | { |
| 1214 | MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); |
| 1215 | |
| 1216 | BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); |
| 1217 | |
| 1218 | MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); |
| 1219 | (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, |
| 1220 | inbuf, sizeof(inbuf), NULL, 0, NULL); |
| 1221 | } |
| 1222 | |
| 1223 | static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) |
| 1224 | { |
| 1225 | return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, |
| 1226 | (tx_queue->ptr_mask + 1) * |
| 1227 | sizeof(efx_qword_t), |
| 1228 | GFP_KERNEL); |
| 1229 | } |
| 1230 | |
| 1231 | /* This writes to the TX_DESC_WPTR and also pushes data */ |
| 1232 | static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, |
| 1233 | const efx_qword_t *txd) |
| 1234 | { |
| 1235 | unsigned int write_ptr; |
| 1236 | efx_oword_t reg; |
| 1237 | |
| 1238 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; |
| 1239 | EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); |
| 1240 | reg.qword[0] = *txd; |
| 1241 | efx_writeo_page(tx_queue->efx, ®, |
| 1242 | ER_DZ_TX_DESC_UPD, tx_queue->queue); |
| 1243 | } |
| 1244 | |
| 1245 | static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) |
| 1246 | { |
| 1247 | MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / |
| 1248 | EFX_BUF_SIZE)); |
| 1249 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN); |
| 1250 | bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; |
| 1251 | size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; |
| 1252 | struct efx_channel *channel = tx_queue->channel; |
| 1253 | struct efx_nic *efx = tx_queue->efx; |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 1254 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1255 | size_t inlen, outlen; |
| 1256 | dma_addr_t dma_addr; |
| 1257 | efx_qword_t *txd; |
| 1258 | int rc; |
| 1259 | int i; |
| 1260 | |
| 1261 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); |
| 1262 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); |
| 1263 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); |
| 1264 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); |
| 1265 | MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, |
| 1266 | INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, |
| 1267 | INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); |
| 1268 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 1269 | MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1270 | |
| 1271 | dma_addr = tx_queue->txd.buf.dma_addr; |
| 1272 | |
| 1273 | netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", |
| 1274 | tx_queue->queue, entries, (u64)dma_addr); |
| 1275 | |
| 1276 | for (i = 0; i < entries; ++i) { |
| 1277 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); |
| 1278 | dma_addr += EFX_BUF_SIZE; |
| 1279 | } |
| 1280 | |
| 1281 | inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); |
| 1282 | |
| 1283 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, |
| 1284 | outbuf, sizeof(outbuf), &outlen); |
| 1285 | if (rc) |
| 1286 | goto fail; |
| 1287 | |
| 1288 | /* A previous user of this TX queue might have set us up the |
| 1289 | * bomb by writing a descriptor to the TX push collector but |
| 1290 | * not the doorbell. (Each collector belongs to a port, not a |
| 1291 | * queue or function, so cannot easily be reset.) We must |
| 1292 | * attempt to push a no-op descriptor in its place. |
| 1293 | */ |
| 1294 | tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; |
| 1295 | tx_queue->insert_count = 1; |
| 1296 | txd = efx_tx_desc(tx_queue, 0); |
| 1297 | EFX_POPULATE_QWORD_4(*txd, |
| 1298 | ESF_DZ_TX_DESC_IS_OPT, true, |
| 1299 | ESF_DZ_TX_OPTION_TYPE, |
| 1300 | ESE_DZ_TX_OPTION_DESC_CRC_CSUM, |
| 1301 | ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, |
| 1302 | ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); |
| 1303 | tx_queue->write_count = 1; |
| 1304 | wmb(); |
| 1305 | efx_ef10_push_tx_desc(tx_queue, txd); |
| 1306 | |
| 1307 | return; |
| 1308 | |
| 1309 | fail: |
Ben Hutchings | 48ce563 | 2013-11-01 16:42:44 +0000 | [diff] [blame] | 1310 | netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", |
| 1311 | tx_queue->queue); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1312 | } |
| 1313 | |
| 1314 | static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) |
| 1315 | { |
| 1316 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); |
| 1317 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN); |
| 1318 | struct efx_nic *efx = tx_queue->efx; |
| 1319 | size_t outlen; |
| 1320 | int rc; |
| 1321 | |
| 1322 | MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, |
| 1323 | tx_queue->queue); |
| 1324 | |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 1325 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1326 | outbuf, sizeof(outbuf), &outlen); |
| 1327 | |
| 1328 | if (rc && rc != -EALREADY) |
| 1329 | goto fail; |
| 1330 | |
| 1331 | return; |
| 1332 | |
| 1333 | fail: |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 1334 | efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, |
| 1335 | outbuf, outlen, rc); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1336 | } |
| 1337 | |
| 1338 | static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) |
| 1339 | { |
| 1340 | efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); |
| 1341 | } |
| 1342 | |
| 1343 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ |
| 1344 | static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) |
| 1345 | { |
| 1346 | unsigned int write_ptr; |
| 1347 | efx_dword_t reg; |
| 1348 | |
| 1349 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; |
| 1350 | EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); |
| 1351 | efx_writed_page(tx_queue->efx, ®, |
| 1352 | ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); |
| 1353 | } |
| 1354 | |
| 1355 | static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) |
| 1356 | { |
| 1357 | unsigned int old_write_count = tx_queue->write_count; |
| 1358 | struct efx_tx_buffer *buffer; |
| 1359 | unsigned int write_ptr; |
| 1360 | efx_qword_t *txd; |
| 1361 | |
| 1362 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); |
| 1363 | |
| 1364 | do { |
| 1365 | write_ptr = tx_queue->write_count & tx_queue->ptr_mask; |
| 1366 | buffer = &tx_queue->buffer[write_ptr]; |
| 1367 | txd = efx_tx_desc(tx_queue, write_ptr); |
| 1368 | ++tx_queue->write_count; |
| 1369 | |
| 1370 | /* Create TX descriptor ring entry */ |
| 1371 | if (buffer->flags & EFX_TX_BUF_OPTION) { |
| 1372 | *txd = buffer->option; |
| 1373 | } else { |
| 1374 | BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); |
| 1375 | EFX_POPULATE_QWORD_3( |
| 1376 | *txd, |
| 1377 | ESF_DZ_TX_KER_CONT, |
| 1378 | buffer->flags & EFX_TX_BUF_CONT, |
| 1379 | ESF_DZ_TX_KER_BYTE_CNT, buffer->len, |
| 1380 | ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); |
| 1381 | } |
| 1382 | } while (tx_queue->write_count != tx_queue->insert_count); |
| 1383 | |
| 1384 | wmb(); /* Ensure descriptors are written before they are fetched */ |
| 1385 | |
| 1386 | if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { |
| 1387 | txd = efx_tx_desc(tx_queue, |
| 1388 | old_write_count & tx_queue->ptr_mask); |
| 1389 | efx_ef10_push_tx_desc(tx_queue, txd); |
| 1390 | ++tx_queue->pushes; |
| 1391 | } else { |
| 1392 | efx_ef10_notify_tx_desc(tx_queue); |
| 1393 | } |
| 1394 | } |
| 1395 | |
| 1396 | static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context) |
| 1397 | { |
| 1398 | MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); |
| 1399 | MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 1400 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1401 | size_t outlen; |
| 1402 | int rc; |
| 1403 | |
| 1404 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 1405 | nic_data->vport_id); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1406 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, |
| 1407 | MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); |
| 1408 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, |
| 1409 | EFX_MAX_CHANNELS); |
| 1410 | |
| 1411 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), |
| 1412 | outbuf, sizeof(outbuf), &outlen); |
| 1413 | if (rc != 0) |
| 1414 | return rc; |
| 1415 | |
| 1416 | if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) |
| 1417 | return -EIO; |
| 1418 | |
| 1419 | *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); |
| 1420 | |
| 1421 | return 0; |
| 1422 | } |
| 1423 | |
| 1424 | static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) |
| 1425 | { |
| 1426 | MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); |
| 1427 | int rc; |
| 1428 | |
| 1429 | MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, |
| 1430 | context); |
| 1431 | |
| 1432 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), |
| 1433 | NULL, 0, NULL); |
| 1434 | WARN_ON(rc != 0); |
| 1435 | } |
| 1436 | |
| 1437 | static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context) |
| 1438 | { |
| 1439 | MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); |
| 1440 | MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); |
| 1441 | int i, rc; |
| 1442 | |
| 1443 | MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, |
| 1444 | context); |
| 1445 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != |
| 1446 | MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); |
| 1447 | |
| 1448 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) |
| 1449 | MCDI_PTR(tablebuf, |
| 1450 | RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = |
| 1451 | (u8) efx->rx_indir_table[i]; |
| 1452 | |
| 1453 | rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, |
| 1454 | sizeof(tablebuf), NULL, 0, NULL); |
| 1455 | if (rc != 0) |
| 1456 | return rc; |
| 1457 | |
| 1458 | MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, |
| 1459 | context); |
| 1460 | BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != |
| 1461 | MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); |
| 1462 | for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) |
| 1463 | MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = |
| 1464 | efx->rx_hash_key[i]; |
| 1465 | |
| 1466 | return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, |
| 1467 | sizeof(keybuf), NULL, 0, NULL); |
| 1468 | } |
| 1469 | |
| 1470 | static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) |
| 1471 | { |
| 1472 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1473 | |
| 1474 | if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) |
| 1475 | efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); |
| 1476 | nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; |
| 1477 | } |
| 1478 | |
Andrew Rybchenko | d43050c | 2013-11-14 09:00:27 +0400 | [diff] [blame] | 1479 | static void efx_ef10_rx_push_rss_config(struct efx_nic *efx) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1480 | { |
| 1481 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1482 | int rc; |
| 1483 | |
Andrew Rybchenko | d43050c | 2013-11-14 09:00:27 +0400 | [diff] [blame] | 1484 | netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n"); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1485 | |
| 1486 | if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) { |
| 1487 | rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context); |
| 1488 | if (rc != 0) |
| 1489 | goto fail; |
| 1490 | } |
| 1491 | |
| 1492 | rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context); |
| 1493 | if (rc != 0) |
| 1494 | goto fail; |
| 1495 | |
| 1496 | return; |
| 1497 | |
| 1498 | fail: |
| 1499 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
| 1500 | } |
| 1501 | |
| 1502 | static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) |
| 1503 | { |
| 1504 | return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, |
| 1505 | (rx_queue->ptr_mask + 1) * |
| 1506 | sizeof(efx_qword_t), |
| 1507 | GFP_KERNEL); |
| 1508 | } |
| 1509 | |
| 1510 | static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) |
| 1511 | { |
| 1512 | MCDI_DECLARE_BUF(inbuf, |
| 1513 | MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / |
| 1514 | EFX_BUF_SIZE)); |
| 1515 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN); |
| 1516 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); |
| 1517 | size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; |
| 1518 | struct efx_nic *efx = rx_queue->efx; |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 1519 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1520 | size_t inlen, outlen; |
| 1521 | dma_addr_t dma_addr; |
| 1522 | int rc; |
| 1523 | int i; |
| 1524 | |
| 1525 | rx_queue->scatter_n = 0; |
| 1526 | rx_queue->scatter_len = 0; |
| 1527 | |
| 1528 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); |
| 1529 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); |
| 1530 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); |
| 1531 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, |
| 1532 | efx_rx_queue_index(rx_queue)); |
Jon Cooper | bd9a265 | 2013-11-18 12:54:41 +0000 | [diff] [blame] | 1533 | MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, |
| 1534 | INIT_RXQ_IN_FLAG_PREFIX, 1, |
| 1535 | INIT_RXQ_IN_FLAG_TIMESTAMP, 1); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1536 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 1537 | MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1538 | |
| 1539 | dma_addr = rx_queue->rxd.buf.dma_addr; |
| 1540 | |
| 1541 | netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", |
| 1542 | efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); |
| 1543 | |
| 1544 | for (i = 0; i < entries; ++i) { |
| 1545 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); |
| 1546 | dma_addr += EFX_BUF_SIZE; |
| 1547 | } |
| 1548 | |
| 1549 | inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); |
| 1550 | |
| 1551 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, |
| 1552 | outbuf, sizeof(outbuf), &outlen); |
Ben Hutchings | 48ce563 | 2013-11-01 16:42:44 +0000 | [diff] [blame] | 1553 | if (rc) |
| 1554 | netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", |
| 1555 | efx_rx_queue_index(rx_queue)); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1556 | } |
| 1557 | |
| 1558 | static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) |
| 1559 | { |
| 1560 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); |
| 1561 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN); |
| 1562 | struct efx_nic *efx = rx_queue->efx; |
| 1563 | size_t outlen; |
| 1564 | int rc; |
| 1565 | |
| 1566 | MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, |
| 1567 | efx_rx_queue_index(rx_queue)); |
| 1568 | |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 1569 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1570 | outbuf, sizeof(outbuf), &outlen); |
| 1571 | |
| 1572 | if (rc && rc != -EALREADY) |
| 1573 | goto fail; |
| 1574 | |
| 1575 | return; |
| 1576 | |
| 1577 | fail: |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 1578 | efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, |
| 1579 | outbuf, outlen, rc); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1580 | } |
| 1581 | |
| 1582 | static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) |
| 1583 | { |
| 1584 | efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); |
| 1585 | } |
| 1586 | |
| 1587 | /* This creates an entry in the RX descriptor queue */ |
| 1588 | static inline void |
| 1589 | efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) |
| 1590 | { |
| 1591 | struct efx_rx_buffer *rx_buf; |
| 1592 | efx_qword_t *rxd; |
| 1593 | |
| 1594 | rxd = efx_rx_desc(rx_queue, index); |
| 1595 | rx_buf = efx_rx_buffer(rx_queue, index); |
| 1596 | EFX_POPULATE_QWORD_2(*rxd, |
| 1597 | ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, |
| 1598 | ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); |
| 1599 | } |
| 1600 | |
| 1601 | static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) |
| 1602 | { |
| 1603 | struct efx_nic *efx = rx_queue->efx; |
| 1604 | unsigned int write_count; |
| 1605 | efx_dword_t reg; |
| 1606 | |
| 1607 | /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ |
| 1608 | write_count = rx_queue->added_count & ~7; |
| 1609 | if (rx_queue->notified_count == write_count) |
| 1610 | return; |
| 1611 | |
| 1612 | do |
| 1613 | efx_ef10_build_rx_desc( |
| 1614 | rx_queue, |
| 1615 | rx_queue->notified_count & rx_queue->ptr_mask); |
| 1616 | while (++rx_queue->notified_count != write_count); |
| 1617 | |
| 1618 | wmb(); |
| 1619 | EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, |
| 1620 | write_count & rx_queue->ptr_mask); |
| 1621 | efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, |
| 1622 | efx_rx_queue_index(rx_queue)); |
| 1623 | } |
| 1624 | |
| 1625 | static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; |
| 1626 | |
| 1627 | static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) |
| 1628 | { |
| 1629 | struct efx_channel *channel = efx_rx_queue_channel(rx_queue); |
| 1630 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); |
| 1631 | efx_qword_t event; |
| 1632 | |
| 1633 | EFX_POPULATE_QWORD_2(event, |
| 1634 | ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, |
| 1635 | ESF_DZ_EV_DATA, EFX_EF10_REFILL); |
| 1636 | |
| 1637 | MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); |
| 1638 | |
| 1639 | /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has |
| 1640 | * already swapped the data to little-endian order. |
| 1641 | */ |
| 1642 | memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], |
| 1643 | sizeof(efx_qword_t)); |
| 1644 | |
| 1645 | efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, |
| 1646 | inbuf, sizeof(inbuf), 0, |
| 1647 | efx_ef10_rx_defer_refill_complete, 0); |
| 1648 | } |
| 1649 | |
| 1650 | static void |
| 1651 | efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, |
| 1652 | int rc, efx_dword_t *outbuf, |
| 1653 | size_t outlen_actual) |
| 1654 | { |
| 1655 | /* nothing to do */ |
| 1656 | } |
| 1657 | |
| 1658 | static int efx_ef10_ev_probe(struct efx_channel *channel) |
| 1659 | { |
| 1660 | return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, |
| 1661 | (channel->eventq_mask + 1) * |
| 1662 | sizeof(efx_qword_t), |
| 1663 | GFP_KERNEL); |
| 1664 | } |
| 1665 | |
| 1666 | static int efx_ef10_ev_init(struct efx_channel *channel) |
| 1667 | { |
| 1668 | MCDI_DECLARE_BUF(inbuf, |
| 1669 | MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / |
| 1670 | EFX_BUF_SIZE)); |
| 1671 | MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); |
| 1672 | size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; |
| 1673 | struct efx_nic *efx = channel->efx; |
| 1674 | struct efx_ef10_nic_data *nic_data; |
| 1675 | bool supports_rx_merge; |
| 1676 | size_t inlen, outlen; |
| 1677 | dma_addr_t dma_addr; |
| 1678 | int rc; |
| 1679 | int i; |
| 1680 | |
| 1681 | nic_data = efx->nic_data; |
| 1682 | supports_rx_merge = |
| 1683 | !!(nic_data->datapath_caps & |
| 1684 | 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); |
| 1685 | |
| 1686 | /* Fill event queue with all ones (i.e. empty events) */ |
| 1687 | memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); |
| 1688 | |
| 1689 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); |
| 1690 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); |
| 1691 | /* INIT_EVQ expects index in vector table, not absolute */ |
| 1692 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); |
| 1693 | MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, |
| 1694 | INIT_EVQ_IN_FLAG_INTERRUPTING, 1, |
| 1695 | INIT_EVQ_IN_FLAG_RX_MERGE, 1, |
| 1696 | INIT_EVQ_IN_FLAG_TX_MERGE, 1, |
| 1697 | INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); |
| 1698 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, |
| 1699 | MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); |
| 1700 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); |
| 1701 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); |
| 1702 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, |
| 1703 | MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); |
| 1704 | MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); |
| 1705 | |
| 1706 | dma_addr = channel->eventq.buf.dma_addr; |
| 1707 | for (i = 0; i < entries; ++i) { |
| 1708 | MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); |
| 1709 | dma_addr += EFX_BUF_SIZE; |
| 1710 | } |
| 1711 | |
| 1712 | inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); |
| 1713 | |
| 1714 | rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, |
| 1715 | outbuf, sizeof(outbuf), &outlen); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1716 | /* IRQ return is ignored */ |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1717 | return rc; |
| 1718 | } |
| 1719 | |
| 1720 | static void efx_ef10_ev_fini(struct efx_channel *channel) |
| 1721 | { |
| 1722 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); |
| 1723 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN); |
| 1724 | struct efx_nic *efx = channel->efx; |
| 1725 | size_t outlen; |
| 1726 | int rc; |
| 1727 | |
| 1728 | MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); |
| 1729 | |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 1730 | rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1731 | outbuf, sizeof(outbuf), &outlen); |
| 1732 | |
| 1733 | if (rc && rc != -EALREADY) |
| 1734 | goto fail; |
| 1735 | |
| 1736 | return; |
| 1737 | |
| 1738 | fail: |
Edward Cree | 1e0b812 | 2013-05-31 18:36:12 +0100 | [diff] [blame] | 1739 | efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, |
| 1740 | outbuf, outlen, rc); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1741 | } |
| 1742 | |
| 1743 | static void efx_ef10_ev_remove(struct efx_channel *channel) |
| 1744 | { |
| 1745 | efx_nic_free_buffer(channel->efx, &channel->eventq.buf); |
| 1746 | } |
| 1747 | |
| 1748 | static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, |
| 1749 | unsigned int rx_queue_label) |
| 1750 | { |
| 1751 | struct efx_nic *efx = rx_queue->efx; |
| 1752 | |
| 1753 | netif_info(efx, hw, efx->net_dev, |
| 1754 | "rx event arrived on queue %d labeled as queue %u\n", |
| 1755 | efx_rx_queue_index(rx_queue), rx_queue_label); |
| 1756 | |
| 1757 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); |
| 1758 | } |
| 1759 | |
| 1760 | static void |
| 1761 | efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, |
| 1762 | unsigned int actual, unsigned int expected) |
| 1763 | { |
| 1764 | unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; |
| 1765 | struct efx_nic *efx = rx_queue->efx; |
| 1766 | |
| 1767 | netif_info(efx, hw, efx->net_dev, |
| 1768 | "dropped %d events (index=%d expected=%d)\n", |
| 1769 | dropped, actual, expected); |
| 1770 | |
| 1771 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); |
| 1772 | } |
| 1773 | |
| 1774 | /* partially received RX was aborted. clean up. */ |
| 1775 | static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) |
| 1776 | { |
| 1777 | unsigned int rx_desc_ptr; |
| 1778 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1779 | netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, |
| 1780 | "scattered RX aborted (dropping %u buffers)\n", |
| 1781 | rx_queue->scatter_n); |
| 1782 | |
| 1783 | rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; |
| 1784 | |
| 1785 | efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, |
| 1786 | 0, EFX_RX_PKT_DISCARD); |
| 1787 | |
| 1788 | rx_queue->removed_count += rx_queue->scatter_n; |
| 1789 | rx_queue->scatter_n = 0; |
| 1790 | rx_queue->scatter_len = 0; |
| 1791 | ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; |
| 1792 | } |
| 1793 | |
| 1794 | static int efx_ef10_handle_rx_event(struct efx_channel *channel, |
| 1795 | const efx_qword_t *event) |
| 1796 | { |
| 1797 | unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; |
| 1798 | unsigned int n_descs, n_packets, i; |
| 1799 | struct efx_nic *efx = channel->efx; |
| 1800 | struct efx_rx_queue *rx_queue; |
| 1801 | bool rx_cont; |
| 1802 | u16 flags = 0; |
| 1803 | |
| 1804 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) |
| 1805 | return 0; |
| 1806 | |
| 1807 | /* Basic packet information */ |
| 1808 | rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); |
| 1809 | next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); |
| 1810 | rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); |
| 1811 | rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); |
| 1812 | rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); |
| 1813 | |
Ben Hutchings | 48ce563 | 2013-11-01 16:42:44 +0000 | [diff] [blame] | 1814 | if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) |
| 1815 | netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" |
| 1816 | EFX_QWORD_FMT "\n", |
| 1817 | EFX_QWORD_VAL(*event)); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1818 | |
| 1819 | rx_queue = efx_channel_get_rx_queue(channel); |
| 1820 | |
| 1821 | if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) |
| 1822 | efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); |
| 1823 | |
| 1824 | n_descs = ((next_ptr_lbits - rx_queue->removed_count) & |
| 1825 | ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); |
| 1826 | |
| 1827 | if (n_descs != rx_queue->scatter_n + 1) { |
Ben Hutchings | 92a0416 | 2013-09-24 23:21:57 +0100 | [diff] [blame] | 1828 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 1829 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1830 | /* detect rx abort */ |
| 1831 | if (unlikely(n_descs == rx_queue->scatter_n)) { |
Ben Hutchings | 48ce563 | 2013-11-01 16:42:44 +0000 | [diff] [blame] | 1832 | if (rx_queue->scatter_n == 0 || rx_bytes != 0) |
| 1833 | netdev_WARN(efx->net_dev, |
| 1834 | "invalid RX abort: scatter_n=%u event=" |
| 1835 | EFX_QWORD_FMT "\n", |
| 1836 | rx_queue->scatter_n, |
| 1837 | EFX_QWORD_VAL(*event)); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1838 | efx_ef10_handle_rx_abort(rx_queue); |
| 1839 | return 0; |
| 1840 | } |
| 1841 | |
Ben Hutchings | 92a0416 | 2013-09-24 23:21:57 +0100 | [diff] [blame] | 1842 | /* Check that RX completion merging is valid, i.e. |
| 1843 | * the current firmware supports it and this is a |
| 1844 | * non-scattered packet. |
| 1845 | */ |
| 1846 | if (!(nic_data->datapath_caps & |
| 1847 | (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || |
| 1848 | rx_queue->scatter_n != 0 || rx_cont) { |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1849 | efx_ef10_handle_rx_bad_lbits( |
| 1850 | rx_queue, next_ptr_lbits, |
| 1851 | (rx_queue->removed_count + |
| 1852 | rx_queue->scatter_n + 1) & |
| 1853 | ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); |
| 1854 | return 0; |
| 1855 | } |
| 1856 | |
| 1857 | /* Merged completion for multiple non-scattered packets */ |
| 1858 | rx_queue->scatter_n = 1; |
| 1859 | rx_queue->scatter_len = 0; |
| 1860 | n_packets = n_descs; |
| 1861 | ++channel->n_rx_merge_events; |
| 1862 | channel->n_rx_merge_packets += n_packets; |
| 1863 | flags |= EFX_RX_PKT_PREFIX_LEN; |
| 1864 | } else { |
| 1865 | ++rx_queue->scatter_n; |
| 1866 | rx_queue->scatter_len += rx_bytes; |
| 1867 | if (rx_cont) |
| 1868 | return 0; |
| 1869 | n_packets = 1; |
| 1870 | } |
| 1871 | |
| 1872 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) |
| 1873 | flags |= EFX_RX_PKT_DISCARD; |
| 1874 | |
| 1875 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { |
| 1876 | channel->n_rx_ip_hdr_chksum_err += n_packets; |
| 1877 | } else if (unlikely(EFX_QWORD_FIELD(*event, |
| 1878 | ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { |
| 1879 | channel->n_rx_tcp_udp_chksum_err += n_packets; |
| 1880 | } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || |
| 1881 | rx_l4_class == ESE_DZ_L4_CLASS_UDP) { |
| 1882 | flags |= EFX_RX_PKT_CSUMMED; |
| 1883 | } |
| 1884 | |
| 1885 | if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) |
| 1886 | flags |= EFX_RX_PKT_TCP; |
| 1887 | |
| 1888 | channel->irq_mod_score += 2 * n_packets; |
| 1889 | |
| 1890 | /* Handle received packet(s) */ |
| 1891 | for (i = 0; i < n_packets; i++) { |
| 1892 | efx_rx_packet(rx_queue, |
| 1893 | rx_queue->removed_count & rx_queue->ptr_mask, |
| 1894 | rx_queue->scatter_n, rx_queue->scatter_len, |
| 1895 | flags); |
| 1896 | rx_queue->removed_count += rx_queue->scatter_n; |
| 1897 | } |
| 1898 | |
| 1899 | rx_queue->scatter_n = 0; |
| 1900 | rx_queue->scatter_len = 0; |
| 1901 | |
| 1902 | return n_packets; |
| 1903 | } |
| 1904 | |
| 1905 | static int |
| 1906 | efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) |
| 1907 | { |
| 1908 | struct efx_nic *efx = channel->efx; |
| 1909 | struct efx_tx_queue *tx_queue; |
| 1910 | unsigned int tx_ev_desc_ptr; |
| 1911 | unsigned int tx_ev_q_label; |
| 1912 | int tx_descs = 0; |
| 1913 | |
| 1914 | if (unlikely(ACCESS_ONCE(efx->reset_pending))) |
| 1915 | return 0; |
| 1916 | |
| 1917 | if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) |
| 1918 | return 0; |
| 1919 | |
| 1920 | /* Transmit completion */ |
| 1921 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); |
| 1922 | tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); |
| 1923 | tx_queue = efx_channel_get_tx_queue(channel, |
| 1924 | tx_ev_q_label % EFX_TXQ_TYPES); |
| 1925 | tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & |
| 1926 | tx_queue->ptr_mask); |
| 1927 | efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); |
| 1928 | |
| 1929 | return tx_descs; |
| 1930 | } |
| 1931 | |
| 1932 | static void |
| 1933 | efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) |
| 1934 | { |
| 1935 | struct efx_nic *efx = channel->efx; |
| 1936 | int subcode; |
| 1937 | |
| 1938 | subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); |
| 1939 | |
| 1940 | switch (subcode) { |
| 1941 | case ESE_DZ_DRV_TIMER_EV: |
| 1942 | case ESE_DZ_DRV_WAKE_UP_EV: |
| 1943 | break; |
| 1944 | case ESE_DZ_DRV_START_UP_EV: |
| 1945 | /* event queue init complete. ok. */ |
| 1946 | break; |
| 1947 | default: |
| 1948 | netif_err(efx, hw, efx->net_dev, |
| 1949 | "channel %d unknown driver event type %d" |
| 1950 | " (data " EFX_QWORD_FMT ")\n", |
| 1951 | channel->channel, subcode, |
| 1952 | EFX_QWORD_VAL(*event)); |
| 1953 | |
| 1954 | } |
| 1955 | } |
| 1956 | |
| 1957 | static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, |
| 1958 | efx_qword_t *event) |
| 1959 | { |
| 1960 | struct efx_nic *efx = channel->efx; |
| 1961 | u32 subcode; |
| 1962 | |
| 1963 | subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); |
| 1964 | |
| 1965 | switch (subcode) { |
| 1966 | case EFX_EF10_TEST: |
| 1967 | channel->event_test_cpu = raw_smp_processor_id(); |
| 1968 | break; |
| 1969 | case EFX_EF10_REFILL: |
| 1970 | /* The queue must be empty, so we won't receive any rx |
| 1971 | * events, so efx_process_channel() won't refill the |
| 1972 | * queue. Refill it here |
| 1973 | */ |
Jon Cooper | cce2879 | 2013-10-02 11:04:14 +0100 | [diff] [blame] | 1974 | efx_fast_push_rx_descriptors(&channel->rx_queue, true); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1975 | break; |
| 1976 | default: |
| 1977 | netif_err(efx, hw, efx->net_dev, |
| 1978 | "channel %d unknown driver event type %u" |
| 1979 | " (data " EFX_QWORD_FMT ")\n", |
| 1980 | channel->channel, (unsigned) subcode, |
| 1981 | EFX_QWORD_VAL(*event)); |
| 1982 | } |
| 1983 | } |
| 1984 | |
| 1985 | static int efx_ef10_ev_process(struct efx_channel *channel, int quota) |
| 1986 | { |
| 1987 | struct efx_nic *efx = channel->efx; |
| 1988 | efx_qword_t event, *p_event; |
| 1989 | unsigned int read_ptr; |
| 1990 | int ev_code; |
| 1991 | int tx_descs = 0; |
| 1992 | int spent = 0; |
| 1993 | |
Eric W. Biederman | 75363a4 | 2014-03-14 18:11:22 -0700 | [diff] [blame] | 1994 | if (quota <= 0) |
| 1995 | return spent; |
| 1996 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 1997 | read_ptr = channel->eventq_read_ptr; |
| 1998 | |
| 1999 | for (;;) { |
| 2000 | p_event = efx_event(channel, read_ptr); |
| 2001 | event = *p_event; |
| 2002 | |
| 2003 | if (!efx_event_present(&event)) |
| 2004 | break; |
| 2005 | |
| 2006 | EFX_SET_QWORD(*p_event); |
| 2007 | |
| 2008 | ++read_ptr; |
| 2009 | |
| 2010 | ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); |
| 2011 | |
| 2012 | netif_vdbg(efx, drv, efx->net_dev, |
| 2013 | "processing event on %d " EFX_QWORD_FMT "\n", |
| 2014 | channel->channel, EFX_QWORD_VAL(event)); |
| 2015 | |
| 2016 | switch (ev_code) { |
| 2017 | case ESE_DZ_EV_CODE_MCDI_EV: |
| 2018 | efx_mcdi_process_event(channel, &event); |
| 2019 | break; |
| 2020 | case ESE_DZ_EV_CODE_RX_EV: |
| 2021 | spent += efx_ef10_handle_rx_event(channel, &event); |
| 2022 | if (spent >= quota) { |
| 2023 | /* XXX can we split a merged event to |
| 2024 | * avoid going over-quota? |
| 2025 | */ |
| 2026 | spent = quota; |
| 2027 | goto out; |
| 2028 | } |
| 2029 | break; |
| 2030 | case ESE_DZ_EV_CODE_TX_EV: |
| 2031 | tx_descs += efx_ef10_handle_tx_event(channel, &event); |
| 2032 | if (tx_descs > efx->txq_entries) { |
| 2033 | spent = quota; |
| 2034 | goto out; |
| 2035 | } else if (++spent == quota) { |
| 2036 | goto out; |
| 2037 | } |
| 2038 | break; |
| 2039 | case ESE_DZ_EV_CODE_DRIVER_EV: |
| 2040 | efx_ef10_handle_driver_event(channel, &event); |
| 2041 | if (++spent == quota) |
| 2042 | goto out; |
| 2043 | break; |
| 2044 | case EFX_EF10_DRVGEN_EV: |
| 2045 | efx_ef10_handle_driver_generated_event(channel, &event); |
| 2046 | break; |
| 2047 | default: |
| 2048 | netif_err(efx, hw, efx->net_dev, |
| 2049 | "channel %d unknown event type %d" |
| 2050 | " (data " EFX_QWORD_FMT ")\n", |
| 2051 | channel->channel, ev_code, |
| 2052 | EFX_QWORD_VAL(event)); |
| 2053 | } |
| 2054 | } |
| 2055 | |
| 2056 | out: |
| 2057 | channel->eventq_read_ptr = read_ptr; |
| 2058 | return spent; |
| 2059 | } |
| 2060 | |
| 2061 | static void efx_ef10_ev_read_ack(struct efx_channel *channel) |
| 2062 | { |
| 2063 | struct efx_nic *efx = channel->efx; |
| 2064 | efx_dword_t rptr; |
| 2065 | |
| 2066 | if (EFX_EF10_WORKAROUND_35388(efx)) { |
| 2067 | BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < |
| 2068 | (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); |
| 2069 | BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > |
| 2070 | (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); |
| 2071 | |
| 2072 | EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, |
| 2073 | EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, |
| 2074 | ERF_DD_EVQ_IND_RPTR, |
| 2075 | (channel->eventq_read_ptr & |
| 2076 | channel->eventq_mask) >> |
| 2077 | ERF_DD_EVQ_IND_RPTR_WIDTH); |
| 2078 | efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, |
| 2079 | channel->channel); |
| 2080 | EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, |
| 2081 | EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, |
| 2082 | ERF_DD_EVQ_IND_RPTR, |
| 2083 | channel->eventq_read_ptr & |
| 2084 | ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); |
| 2085 | efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, |
| 2086 | channel->channel); |
| 2087 | } else { |
| 2088 | EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, |
| 2089 | channel->eventq_read_ptr & |
| 2090 | channel->eventq_mask); |
| 2091 | efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); |
| 2092 | } |
| 2093 | } |
| 2094 | |
| 2095 | static void efx_ef10_ev_test_generate(struct efx_channel *channel) |
| 2096 | { |
| 2097 | MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); |
| 2098 | struct efx_nic *efx = channel->efx; |
| 2099 | efx_qword_t event; |
| 2100 | int rc; |
| 2101 | |
| 2102 | EFX_POPULATE_QWORD_2(event, |
| 2103 | ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, |
| 2104 | ESF_DZ_EV_DATA, EFX_EF10_TEST); |
| 2105 | |
| 2106 | MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); |
| 2107 | |
| 2108 | /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has |
| 2109 | * already swapped the data to little-endian order. |
| 2110 | */ |
| 2111 | memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], |
| 2112 | sizeof(efx_qword_t)); |
| 2113 | |
| 2114 | rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), |
| 2115 | NULL, 0, NULL); |
| 2116 | if (rc != 0) |
| 2117 | goto fail; |
| 2118 | |
| 2119 | return; |
| 2120 | |
| 2121 | fail: |
| 2122 | WARN_ON(true); |
| 2123 | netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); |
| 2124 | } |
| 2125 | |
| 2126 | void efx_ef10_handle_drain_event(struct efx_nic *efx) |
| 2127 | { |
| 2128 | if (atomic_dec_and_test(&efx->active_queues)) |
| 2129 | wake_up(&efx->flush_wq); |
| 2130 | |
| 2131 | WARN_ON(atomic_read(&efx->active_queues) < 0); |
| 2132 | } |
| 2133 | |
| 2134 | static int efx_ef10_fini_dmaq(struct efx_nic *efx) |
| 2135 | { |
| 2136 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 2137 | struct efx_channel *channel; |
| 2138 | struct efx_tx_queue *tx_queue; |
| 2139 | struct efx_rx_queue *rx_queue; |
| 2140 | int pending; |
| 2141 | |
| 2142 | /* If the MC has just rebooted, the TX/RX queues will have already been |
| 2143 | * torn down, but efx->active_queues needs to be set to zero. |
| 2144 | */ |
| 2145 | if (nic_data->must_realloc_vis) { |
| 2146 | atomic_set(&efx->active_queues, 0); |
| 2147 | return 0; |
| 2148 | } |
| 2149 | |
| 2150 | /* Do not attempt to write to the NIC during EEH recovery */ |
| 2151 | if (efx->state != STATE_RECOVERY) { |
| 2152 | efx_for_each_channel(channel, efx) { |
| 2153 | efx_for_each_channel_rx_queue(rx_queue, channel) |
| 2154 | efx_ef10_rx_fini(rx_queue); |
| 2155 | efx_for_each_channel_tx_queue(tx_queue, channel) |
| 2156 | efx_ef10_tx_fini(tx_queue); |
| 2157 | } |
| 2158 | |
| 2159 | wait_event_timeout(efx->flush_wq, |
| 2160 | atomic_read(&efx->active_queues) == 0, |
| 2161 | msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); |
| 2162 | pending = atomic_read(&efx->active_queues); |
| 2163 | if (pending) { |
| 2164 | netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", |
| 2165 | pending); |
| 2166 | return -ETIMEDOUT; |
| 2167 | } |
| 2168 | } |
| 2169 | |
| 2170 | return 0; |
| 2171 | } |
| 2172 | |
Edward Cree | e283546 | 2014-04-16 19:27:48 +0100 | [diff] [blame] | 2173 | static void efx_ef10_prepare_flr(struct efx_nic *efx) |
| 2174 | { |
| 2175 | atomic_set(&efx->active_queues, 0); |
| 2176 | } |
| 2177 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2178 | static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, |
| 2179 | const struct efx_filter_spec *right) |
| 2180 | { |
| 2181 | if ((left->match_flags ^ right->match_flags) | |
| 2182 | ((left->flags ^ right->flags) & |
| 2183 | (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) |
| 2184 | return false; |
| 2185 | |
| 2186 | return memcmp(&left->outer_vid, &right->outer_vid, |
| 2187 | sizeof(struct efx_filter_spec) - |
| 2188 | offsetof(struct efx_filter_spec, outer_vid)) == 0; |
| 2189 | } |
| 2190 | |
| 2191 | static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) |
| 2192 | { |
| 2193 | BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); |
| 2194 | return jhash2((const u32 *)&spec->outer_vid, |
| 2195 | (sizeof(struct efx_filter_spec) - |
| 2196 | offsetof(struct efx_filter_spec, outer_vid)) / 4, |
| 2197 | 0); |
| 2198 | /* XXX should we randomise the initval? */ |
| 2199 | } |
| 2200 | |
| 2201 | /* Decide whether a filter should be exclusive or else should allow |
| 2202 | * delivery to additional recipients. Currently we decide that |
| 2203 | * filters for specific local unicast MAC and IP addresses are |
| 2204 | * exclusive. |
| 2205 | */ |
| 2206 | static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) |
| 2207 | { |
| 2208 | if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && |
| 2209 | !is_multicast_ether_addr(spec->loc_mac)) |
| 2210 | return true; |
| 2211 | |
| 2212 | if ((spec->match_flags & |
| 2213 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == |
| 2214 | (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { |
| 2215 | if (spec->ether_type == htons(ETH_P_IP) && |
| 2216 | !ipv4_is_multicast(spec->loc_host[0])) |
| 2217 | return true; |
| 2218 | if (spec->ether_type == htons(ETH_P_IPV6) && |
| 2219 | ((const u8 *)spec->loc_host)[0] != 0xff) |
| 2220 | return true; |
| 2221 | } |
| 2222 | |
| 2223 | return false; |
| 2224 | } |
| 2225 | |
| 2226 | static struct efx_filter_spec * |
| 2227 | efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, |
| 2228 | unsigned int filter_idx) |
| 2229 | { |
| 2230 | return (struct efx_filter_spec *)(table->entry[filter_idx].spec & |
| 2231 | ~EFX_EF10_FILTER_FLAGS); |
| 2232 | } |
| 2233 | |
| 2234 | static unsigned int |
| 2235 | efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, |
| 2236 | unsigned int filter_idx) |
| 2237 | { |
| 2238 | return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; |
| 2239 | } |
| 2240 | |
| 2241 | static void |
| 2242 | efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, |
| 2243 | unsigned int filter_idx, |
| 2244 | const struct efx_filter_spec *spec, |
| 2245 | unsigned int flags) |
| 2246 | { |
| 2247 | table->entry[filter_idx].spec = (unsigned long)spec | flags; |
| 2248 | } |
| 2249 | |
| 2250 | static void efx_ef10_filter_push_prep(struct efx_nic *efx, |
| 2251 | const struct efx_filter_spec *spec, |
| 2252 | efx_dword_t *inbuf, u64 handle, |
| 2253 | bool replacing) |
| 2254 | { |
| 2255 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 2256 | |
| 2257 | memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); |
| 2258 | |
| 2259 | if (replacing) { |
| 2260 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, |
| 2261 | MC_CMD_FILTER_OP_IN_OP_REPLACE); |
| 2262 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); |
| 2263 | } else { |
| 2264 | u32 match_fields = 0; |
| 2265 | |
| 2266 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, |
| 2267 | efx_ef10_filter_is_exclusive(spec) ? |
| 2268 | MC_CMD_FILTER_OP_IN_OP_INSERT : |
| 2269 | MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); |
| 2270 | |
| 2271 | /* Convert match flags and values. Unlike almost |
| 2272 | * everything else in MCDI, these fields are in |
| 2273 | * network byte order. |
| 2274 | */ |
| 2275 | if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) |
| 2276 | match_fields |= |
| 2277 | is_multicast_ether_addr(spec->loc_mac) ? |
| 2278 | 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : |
| 2279 | 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; |
| 2280 | #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ |
| 2281 | if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ |
| 2282 | match_fields |= \ |
| 2283 | 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ |
| 2284 | mcdi_field ## _LBN; \ |
| 2285 | BUILD_BUG_ON( \ |
| 2286 | MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ |
| 2287 | sizeof(spec->gen_field)); \ |
| 2288 | memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ |
| 2289 | &spec->gen_field, sizeof(spec->gen_field)); \ |
| 2290 | } |
| 2291 | COPY_FIELD(REM_HOST, rem_host, SRC_IP); |
| 2292 | COPY_FIELD(LOC_HOST, loc_host, DST_IP); |
| 2293 | COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); |
| 2294 | COPY_FIELD(REM_PORT, rem_port, SRC_PORT); |
| 2295 | COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); |
| 2296 | COPY_FIELD(LOC_PORT, loc_port, DST_PORT); |
| 2297 | COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); |
| 2298 | COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); |
| 2299 | COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); |
| 2300 | COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); |
| 2301 | #undef COPY_FIELD |
| 2302 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, |
| 2303 | match_fields); |
| 2304 | } |
| 2305 | |
Daniel Pieczko | 45b2449 | 2015-05-06 00:57:14 +0100 | [diff] [blame] | 2306 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2307 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, |
| 2308 | spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? |
| 2309 | MC_CMD_FILTER_OP_IN_RX_DEST_DROP : |
| 2310 | MC_CMD_FILTER_OP_IN_RX_DEST_HOST); |
Shradha Shah | e3d3629 | 2015-05-06 00:56:24 +0100 | [diff] [blame] | 2311 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2312 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, |
| 2313 | MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); |
Ben Hutchings | a0bc348 | 2013-12-16 18:56:24 +0000 | [diff] [blame] | 2314 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, |
| 2315 | spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? |
| 2316 | 0 : spec->dmaq_id); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2317 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, |
| 2318 | (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? |
| 2319 | MC_CMD_FILTER_OP_IN_RX_MODE_RSS : |
| 2320 | MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); |
| 2321 | if (spec->flags & EFX_FILTER_FLAG_RX_RSS) |
| 2322 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, |
| 2323 | spec->rss_context != |
| 2324 | EFX_FILTER_RSS_CONTEXT_DEFAULT ? |
| 2325 | spec->rss_context : nic_data->rx_rss_context); |
| 2326 | } |
| 2327 | |
| 2328 | static int efx_ef10_filter_push(struct efx_nic *efx, |
| 2329 | const struct efx_filter_spec *spec, |
| 2330 | u64 *handle, bool replacing) |
| 2331 | { |
| 2332 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); |
| 2333 | MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); |
| 2334 | int rc; |
| 2335 | |
| 2336 | efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); |
| 2337 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), |
| 2338 | outbuf, sizeof(outbuf), NULL); |
| 2339 | if (rc == 0) |
| 2340 | *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); |
Ben Hutchings | 065e64c | 2013-10-09 14:17:27 +0100 | [diff] [blame] | 2341 | if (rc == -ENOSPC) |
| 2342 | rc = -EBUSY; /* to match efx_farch_filter_insert() */ |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2343 | return rc; |
| 2344 | } |
| 2345 | |
| 2346 | static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, |
| 2347 | enum efx_filter_match_flags match_flags) |
| 2348 | { |
| 2349 | unsigned int match_pri; |
| 2350 | |
| 2351 | for (match_pri = 0; |
| 2352 | match_pri < table->rx_match_count; |
| 2353 | match_pri++) |
| 2354 | if (table->rx_match_flags[match_pri] == match_flags) |
| 2355 | return match_pri; |
| 2356 | |
| 2357 | return -EPROTONOSUPPORT; |
| 2358 | } |
| 2359 | |
| 2360 | static s32 efx_ef10_filter_insert(struct efx_nic *efx, |
| 2361 | struct efx_filter_spec *spec, |
| 2362 | bool replace_equal) |
| 2363 | { |
| 2364 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2365 | DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); |
| 2366 | struct efx_filter_spec *saved_spec; |
| 2367 | unsigned int match_pri, hash; |
| 2368 | unsigned int priv_flags; |
| 2369 | bool replacing = false; |
| 2370 | int ins_index = -1; |
| 2371 | DEFINE_WAIT(wait); |
| 2372 | bool is_mc_recip; |
| 2373 | s32 rc; |
| 2374 | |
| 2375 | /* For now, only support RX filters */ |
| 2376 | if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != |
| 2377 | EFX_FILTER_FLAG_RX) |
| 2378 | return -EINVAL; |
| 2379 | |
| 2380 | rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); |
| 2381 | if (rc < 0) |
| 2382 | return rc; |
| 2383 | match_pri = rc; |
| 2384 | |
| 2385 | hash = efx_ef10_filter_hash(spec); |
| 2386 | is_mc_recip = efx_filter_is_mc_recipient(spec); |
| 2387 | if (is_mc_recip) |
| 2388 | bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); |
| 2389 | |
| 2390 | /* Find any existing filters with the same match tuple or |
| 2391 | * else a free slot to insert at. If any of them are busy, |
| 2392 | * we have to wait and retry. |
| 2393 | */ |
| 2394 | for (;;) { |
| 2395 | unsigned int depth = 1; |
| 2396 | unsigned int i; |
| 2397 | |
| 2398 | spin_lock_bh(&efx->filter_lock); |
| 2399 | |
| 2400 | for (;;) { |
| 2401 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); |
| 2402 | saved_spec = efx_ef10_filter_entry_spec(table, i); |
| 2403 | |
| 2404 | if (!saved_spec) { |
| 2405 | if (ins_index < 0) |
| 2406 | ins_index = i; |
| 2407 | } else if (efx_ef10_filter_equal(spec, saved_spec)) { |
| 2408 | if (table->entry[i].spec & |
| 2409 | EFX_EF10_FILTER_FLAG_BUSY) |
| 2410 | break; |
| 2411 | if (spec->priority < saved_spec->priority && |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2412 | spec->priority != EFX_FILTER_PRI_AUTO) { |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2413 | rc = -EPERM; |
| 2414 | goto out_unlock; |
| 2415 | } |
| 2416 | if (!is_mc_recip) { |
| 2417 | /* This is the only one */ |
| 2418 | if (spec->priority == |
| 2419 | saved_spec->priority && |
| 2420 | !replace_equal) { |
| 2421 | rc = -EEXIST; |
| 2422 | goto out_unlock; |
| 2423 | } |
| 2424 | ins_index = i; |
| 2425 | goto found; |
| 2426 | } else if (spec->priority > |
| 2427 | saved_spec->priority || |
| 2428 | (spec->priority == |
| 2429 | saved_spec->priority && |
| 2430 | replace_equal)) { |
| 2431 | if (ins_index < 0) |
| 2432 | ins_index = i; |
| 2433 | else |
| 2434 | __set_bit(depth, mc_rem_map); |
| 2435 | } |
| 2436 | } |
| 2437 | |
| 2438 | /* Once we reach the maximum search depth, use |
| 2439 | * the first suitable slot or return -EBUSY if |
| 2440 | * there was none |
| 2441 | */ |
| 2442 | if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { |
| 2443 | if (ins_index < 0) { |
| 2444 | rc = -EBUSY; |
| 2445 | goto out_unlock; |
| 2446 | } |
| 2447 | goto found; |
| 2448 | } |
| 2449 | |
| 2450 | ++depth; |
| 2451 | } |
| 2452 | |
| 2453 | prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); |
| 2454 | spin_unlock_bh(&efx->filter_lock); |
| 2455 | schedule(); |
| 2456 | } |
| 2457 | |
| 2458 | found: |
| 2459 | /* Create a software table entry if necessary, and mark it |
| 2460 | * busy. We might yet fail to insert, but any attempt to |
| 2461 | * insert a conflicting filter while we're waiting for the |
| 2462 | * firmware must find the busy entry. |
| 2463 | */ |
| 2464 | saved_spec = efx_ef10_filter_entry_spec(table, ins_index); |
| 2465 | if (saved_spec) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2466 | if (spec->priority == EFX_FILTER_PRI_AUTO && |
| 2467 | saved_spec->priority >= EFX_FILTER_PRI_AUTO) { |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2468 | /* Just make sure it won't be removed */ |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2469 | if (saved_spec->priority > EFX_FILTER_PRI_AUTO) |
| 2470 | saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2471 | table->entry[ins_index].spec &= |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 2472 | ~EFX_EF10_FILTER_FLAG_AUTO_OLD; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2473 | rc = ins_index; |
| 2474 | goto out_unlock; |
| 2475 | } |
| 2476 | replacing = true; |
| 2477 | priv_flags = efx_ef10_filter_entry_flags(table, ins_index); |
| 2478 | } else { |
| 2479 | saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); |
| 2480 | if (!saved_spec) { |
| 2481 | rc = -ENOMEM; |
| 2482 | goto out_unlock; |
| 2483 | } |
| 2484 | *saved_spec = *spec; |
| 2485 | priv_flags = 0; |
| 2486 | } |
| 2487 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, |
| 2488 | priv_flags | EFX_EF10_FILTER_FLAG_BUSY); |
| 2489 | |
| 2490 | /* Mark lower-priority multicast recipients busy prior to removal */ |
| 2491 | if (is_mc_recip) { |
| 2492 | unsigned int depth, i; |
| 2493 | |
| 2494 | for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { |
| 2495 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); |
| 2496 | if (test_bit(depth, mc_rem_map)) |
| 2497 | table->entry[i].spec |= |
| 2498 | EFX_EF10_FILTER_FLAG_BUSY; |
| 2499 | } |
| 2500 | } |
| 2501 | |
| 2502 | spin_unlock_bh(&efx->filter_lock); |
| 2503 | |
| 2504 | rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, |
| 2505 | replacing); |
| 2506 | |
| 2507 | /* Finalise the software table entry */ |
| 2508 | spin_lock_bh(&efx->filter_lock); |
| 2509 | if (rc == 0) { |
| 2510 | if (replacing) { |
| 2511 | /* Update the fields that may differ */ |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2512 | if (saved_spec->priority == EFX_FILTER_PRI_AUTO) |
| 2513 | saved_spec->flags |= |
| 2514 | EFX_FILTER_FLAG_RX_OVER_AUTO; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2515 | saved_spec->priority = spec->priority; |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2516 | saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2517 | saved_spec->flags |= spec->flags; |
| 2518 | saved_spec->rss_context = spec->rss_context; |
| 2519 | saved_spec->dmaq_id = spec->dmaq_id; |
| 2520 | } |
| 2521 | } else if (!replacing) { |
| 2522 | kfree(saved_spec); |
| 2523 | saved_spec = NULL; |
| 2524 | } |
| 2525 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); |
| 2526 | |
| 2527 | /* Remove and finalise entries for lower-priority multicast |
| 2528 | * recipients |
| 2529 | */ |
| 2530 | if (is_mc_recip) { |
| 2531 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); |
| 2532 | unsigned int depth, i; |
| 2533 | |
| 2534 | memset(inbuf, 0, sizeof(inbuf)); |
| 2535 | |
| 2536 | for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { |
| 2537 | if (!test_bit(depth, mc_rem_map)) |
| 2538 | continue; |
| 2539 | |
| 2540 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); |
| 2541 | saved_spec = efx_ef10_filter_entry_spec(table, i); |
| 2542 | priv_flags = efx_ef10_filter_entry_flags(table, i); |
| 2543 | |
| 2544 | if (rc == 0) { |
| 2545 | spin_unlock_bh(&efx->filter_lock); |
| 2546 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, |
| 2547 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); |
| 2548 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, |
| 2549 | table->entry[i].handle); |
| 2550 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, |
| 2551 | inbuf, sizeof(inbuf), |
| 2552 | NULL, 0, NULL); |
| 2553 | spin_lock_bh(&efx->filter_lock); |
| 2554 | } |
| 2555 | |
| 2556 | if (rc == 0) { |
| 2557 | kfree(saved_spec); |
| 2558 | saved_spec = NULL; |
| 2559 | priv_flags = 0; |
| 2560 | } else { |
| 2561 | priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; |
| 2562 | } |
| 2563 | efx_ef10_filter_set_entry(table, i, saved_spec, |
| 2564 | priv_flags); |
| 2565 | } |
| 2566 | } |
| 2567 | |
| 2568 | /* If successful, return the inserted filter ID */ |
| 2569 | if (rc == 0) |
| 2570 | rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; |
| 2571 | |
| 2572 | wake_up_all(&table->waitq); |
| 2573 | out_unlock: |
| 2574 | spin_unlock_bh(&efx->filter_lock); |
| 2575 | finish_wait(&table->waitq, &wait); |
| 2576 | return rc; |
| 2577 | } |
| 2578 | |
Fengguang Wu | 9fd8095d | 2013-08-31 06:54:05 +0800 | [diff] [blame] | 2579 | static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2580 | { |
| 2581 | /* no need to do anything here on EF10 */ |
| 2582 | } |
| 2583 | |
| 2584 | /* Remove a filter. |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 2585 | * If !by_index, remove by ID |
| 2586 | * If by_index, remove by index |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2587 | * Filter ID may come from userland and must be range-checked. |
| 2588 | */ |
| 2589 | static int efx_ef10_filter_remove_internal(struct efx_nic *efx, |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 2590 | unsigned int priority_mask, |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 2591 | u32 filter_id, bool by_index) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2592 | { |
| 2593 | unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; |
| 2594 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2595 | MCDI_DECLARE_BUF(inbuf, |
| 2596 | MC_CMD_FILTER_OP_IN_HANDLE_OFST + |
| 2597 | MC_CMD_FILTER_OP_IN_HANDLE_LEN); |
| 2598 | struct efx_filter_spec *spec; |
| 2599 | DEFINE_WAIT(wait); |
| 2600 | int rc; |
| 2601 | |
| 2602 | /* Find the software table entry and mark it busy. Don't |
| 2603 | * remove it yet; any attempt to update while we're waiting |
| 2604 | * for the firmware must find the busy entry. |
| 2605 | */ |
| 2606 | for (;;) { |
| 2607 | spin_lock_bh(&efx->filter_lock); |
| 2608 | if (!(table->entry[filter_idx].spec & |
| 2609 | EFX_EF10_FILTER_FLAG_BUSY)) |
| 2610 | break; |
| 2611 | prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); |
| 2612 | spin_unlock_bh(&efx->filter_lock); |
| 2613 | schedule(); |
| 2614 | } |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2615 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2616 | spec = efx_ef10_filter_entry_spec(table, filter_idx); |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2617 | if (!spec || |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 2618 | (!by_index && |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2619 | efx_ef10_filter_rx_match_pri(table, spec->match_flags) != |
| 2620 | filter_id / HUNT_FILTER_TBL_ROWS)) { |
| 2621 | rc = -ENOENT; |
| 2622 | goto out_unlock; |
| 2623 | } |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2624 | |
| 2625 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 2626 | priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2627 | /* Just remove flags */ |
| 2628 | spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 2629 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2630 | rc = 0; |
| 2631 | goto out_unlock; |
| 2632 | } |
| 2633 | |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 2634 | if (!(priority_mask & (1U << spec->priority))) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2635 | rc = -ENOENT; |
| 2636 | goto out_unlock; |
| 2637 | } |
| 2638 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2639 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; |
| 2640 | spin_unlock_bh(&efx->filter_lock); |
| 2641 | |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2642 | if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 2643 | /* Reset to an automatic filter */ |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2644 | |
| 2645 | struct efx_filter_spec new_spec = *spec; |
| 2646 | |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2647 | new_spec.priority = EFX_FILTER_PRI_AUTO; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2648 | new_spec.flags = (EFX_FILTER_FLAG_RX | |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2649 | EFX_FILTER_FLAG_RX_RSS); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2650 | new_spec.dmaq_id = 0; |
| 2651 | new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; |
| 2652 | rc = efx_ef10_filter_push(efx, &new_spec, |
| 2653 | &table->entry[filter_idx].handle, |
| 2654 | true); |
| 2655 | |
| 2656 | spin_lock_bh(&efx->filter_lock); |
| 2657 | if (rc == 0) |
| 2658 | *spec = new_spec; |
| 2659 | } else { |
| 2660 | /* Really remove the filter */ |
| 2661 | |
| 2662 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, |
| 2663 | efx_ef10_filter_is_exclusive(spec) ? |
| 2664 | MC_CMD_FILTER_OP_IN_OP_REMOVE : |
| 2665 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); |
| 2666 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, |
| 2667 | table->entry[filter_idx].handle); |
| 2668 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, |
| 2669 | inbuf, sizeof(inbuf), NULL, 0, NULL); |
| 2670 | |
| 2671 | spin_lock_bh(&efx->filter_lock); |
| 2672 | if (rc == 0) { |
| 2673 | kfree(spec); |
| 2674 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); |
| 2675 | } |
| 2676 | } |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 2677 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2678 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; |
| 2679 | wake_up_all(&table->waitq); |
| 2680 | out_unlock: |
| 2681 | spin_unlock_bh(&efx->filter_lock); |
| 2682 | finish_wait(&table->waitq, &wait); |
| 2683 | return rc; |
| 2684 | } |
| 2685 | |
| 2686 | static int efx_ef10_filter_remove_safe(struct efx_nic *efx, |
| 2687 | enum efx_filter_priority priority, |
| 2688 | u32 filter_id) |
| 2689 | { |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 2690 | return efx_ef10_filter_remove_internal(efx, 1U << priority, |
| 2691 | filter_id, false); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2692 | } |
| 2693 | |
| 2694 | static int efx_ef10_filter_get_safe(struct efx_nic *efx, |
| 2695 | enum efx_filter_priority priority, |
| 2696 | u32 filter_id, struct efx_filter_spec *spec) |
| 2697 | { |
| 2698 | unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; |
| 2699 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2700 | const struct efx_filter_spec *saved_spec; |
| 2701 | int rc; |
| 2702 | |
| 2703 | spin_lock_bh(&efx->filter_lock); |
| 2704 | saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); |
| 2705 | if (saved_spec && saved_spec->priority == priority && |
| 2706 | efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == |
| 2707 | filter_id / HUNT_FILTER_TBL_ROWS) { |
| 2708 | *spec = *saved_spec; |
| 2709 | rc = 0; |
| 2710 | } else { |
| 2711 | rc = -ENOENT; |
| 2712 | } |
| 2713 | spin_unlock_bh(&efx->filter_lock); |
| 2714 | return rc; |
| 2715 | } |
| 2716 | |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 2717 | static int efx_ef10_filter_clear_rx(struct efx_nic *efx, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2718 | enum efx_filter_priority priority) |
| 2719 | { |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 2720 | unsigned int priority_mask; |
| 2721 | unsigned int i; |
| 2722 | int rc; |
| 2723 | |
| 2724 | priority_mask = (((1U << (priority + 1)) - 1) & |
| 2725 | ~(1U << EFX_FILTER_PRI_AUTO)); |
| 2726 | |
| 2727 | for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { |
| 2728 | rc = efx_ef10_filter_remove_internal(efx, priority_mask, |
| 2729 | i, true); |
| 2730 | if (rc && rc != -ENOENT) |
| 2731 | return rc; |
| 2732 | } |
| 2733 | |
| 2734 | return 0; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2735 | } |
| 2736 | |
| 2737 | static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, |
| 2738 | enum efx_filter_priority priority) |
| 2739 | { |
| 2740 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2741 | unsigned int filter_idx; |
| 2742 | s32 count = 0; |
| 2743 | |
| 2744 | spin_lock_bh(&efx->filter_lock); |
| 2745 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { |
| 2746 | if (table->entry[filter_idx].spec && |
| 2747 | efx_ef10_filter_entry_spec(table, filter_idx)->priority == |
| 2748 | priority) |
| 2749 | ++count; |
| 2750 | } |
| 2751 | spin_unlock_bh(&efx->filter_lock); |
| 2752 | return count; |
| 2753 | } |
| 2754 | |
| 2755 | static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) |
| 2756 | { |
| 2757 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2758 | |
| 2759 | return table->rx_match_count * HUNT_FILTER_TBL_ROWS; |
| 2760 | } |
| 2761 | |
| 2762 | static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, |
| 2763 | enum efx_filter_priority priority, |
| 2764 | u32 *buf, u32 size) |
| 2765 | { |
| 2766 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2767 | struct efx_filter_spec *spec; |
| 2768 | unsigned int filter_idx; |
| 2769 | s32 count = 0; |
| 2770 | |
| 2771 | spin_lock_bh(&efx->filter_lock); |
| 2772 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { |
| 2773 | spec = efx_ef10_filter_entry_spec(table, filter_idx); |
| 2774 | if (spec && spec->priority == priority) { |
| 2775 | if (count == size) { |
| 2776 | count = -EMSGSIZE; |
| 2777 | break; |
| 2778 | } |
| 2779 | buf[count++] = (efx_ef10_filter_rx_match_pri( |
| 2780 | table, spec->match_flags) * |
| 2781 | HUNT_FILTER_TBL_ROWS + |
| 2782 | filter_idx); |
| 2783 | } |
| 2784 | } |
| 2785 | spin_unlock_bh(&efx->filter_lock); |
| 2786 | return count; |
| 2787 | } |
| 2788 | |
| 2789 | #ifdef CONFIG_RFS_ACCEL |
| 2790 | |
| 2791 | static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; |
| 2792 | |
| 2793 | static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, |
| 2794 | struct efx_filter_spec *spec) |
| 2795 | { |
| 2796 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2797 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); |
| 2798 | struct efx_filter_spec *saved_spec; |
| 2799 | unsigned int hash, i, depth = 1; |
| 2800 | bool replacing = false; |
| 2801 | int ins_index = -1; |
| 2802 | u64 cookie; |
| 2803 | s32 rc; |
| 2804 | |
| 2805 | /* Must be an RX filter without RSS and not for a multicast |
| 2806 | * destination address (RFS only works for connected sockets). |
| 2807 | * These restrictions allow us to pass only a tiny amount of |
| 2808 | * data through to the completion function. |
| 2809 | */ |
| 2810 | EFX_WARN_ON_PARANOID(spec->flags != |
| 2811 | (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); |
| 2812 | EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); |
| 2813 | EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); |
| 2814 | |
| 2815 | hash = efx_ef10_filter_hash(spec); |
| 2816 | |
| 2817 | spin_lock_bh(&efx->filter_lock); |
| 2818 | |
| 2819 | /* Find any existing filter with the same match tuple or else |
| 2820 | * a free slot to insert at. If an existing filter is busy, |
| 2821 | * we have to give up. |
| 2822 | */ |
| 2823 | for (;;) { |
| 2824 | i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); |
| 2825 | saved_spec = efx_ef10_filter_entry_spec(table, i); |
| 2826 | |
| 2827 | if (!saved_spec) { |
| 2828 | if (ins_index < 0) |
| 2829 | ins_index = i; |
| 2830 | } else if (efx_ef10_filter_equal(spec, saved_spec)) { |
| 2831 | if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { |
| 2832 | rc = -EBUSY; |
| 2833 | goto fail_unlock; |
| 2834 | } |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 2835 | if (spec->priority < saved_spec->priority) { |
| 2836 | rc = -EPERM; |
| 2837 | goto fail_unlock; |
| 2838 | } |
| 2839 | ins_index = i; |
| 2840 | break; |
| 2841 | } |
| 2842 | |
| 2843 | /* Once we reach the maximum search depth, use the |
| 2844 | * first suitable slot or return -EBUSY if there was |
| 2845 | * none |
| 2846 | */ |
| 2847 | if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { |
| 2848 | if (ins_index < 0) { |
| 2849 | rc = -EBUSY; |
| 2850 | goto fail_unlock; |
| 2851 | } |
| 2852 | break; |
| 2853 | } |
| 2854 | |
| 2855 | ++depth; |
| 2856 | } |
| 2857 | |
| 2858 | /* Create a software table entry if necessary, and mark it |
| 2859 | * busy. We might yet fail to insert, but any attempt to |
| 2860 | * insert a conflicting filter while we're waiting for the |
| 2861 | * firmware must find the busy entry. |
| 2862 | */ |
| 2863 | saved_spec = efx_ef10_filter_entry_spec(table, ins_index); |
| 2864 | if (saved_spec) { |
| 2865 | replacing = true; |
| 2866 | } else { |
| 2867 | saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); |
| 2868 | if (!saved_spec) { |
| 2869 | rc = -ENOMEM; |
| 2870 | goto fail_unlock; |
| 2871 | } |
| 2872 | *saved_spec = *spec; |
| 2873 | } |
| 2874 | efx_ef10_filter_set_entry(table, ins_index, saved_spec, |
| 2875 | EFX_EF10_FILTER_FLAG_BUSY); |
| 2876 | |
| 2877 | spin_unlock_bh(&efx->filter_lock); |
| 2878 | |
| 2879 | /* Pack up the variables needed on completion */ |
| 2880 | cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; |
| 2881 | |
| 2882 | efx_ef10_filter_push_prep(efx, spec, inbuf, |
| 2883 | table->entry[ins_index].handle, replacing); |
| 2884 | efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), |
| 2885 | MC_CMD_FILTER_OP_OUT_LEN, |
| 2886 | efx_ef10_filter_rfs_insert_complete, cookie); |
| 2887 | |
| 2888 | return ins_index; |
| 2889 | |
| 2890 | fail_unlock: |
| 2891 | spin_unlock_bh(&efx->filter_lock); |
| 2892 | return rc; |
| 2893 | } |
| 2894 | |
| 2895 | static void |
| 2896 | efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, |
| 2897 | int rc, efx_dword_t *outbuf, |
| 2898 | size_t outlen_actual) |
| 2899 | { |
| 2900 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2901 | unsigned int ins_index, dmaq_id; |
| 2902 | struct efx_filter_spec *spec; |
| 2903 | bool replacing; |
| 2904 | |
| 2905 | /* Unpack the cookie */ |
| 2906 | replacing = cookie >> 31; |
| 2907 | ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); |
| 2908 | dmaq_id = cookie & 0xffff; |
| 2909 | |
| 2910 | spin_lock_bh(&efx->filter_lock); |
| 2911 | spec = efx_ef10_filter_entry_spec(table, ins_index); |
| 2912 | if (rc == 0) { |
| 2913 | table->entry[ins_index].handle = |
| 2914 | MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); |
| 2915 | if (replacing) |
| 2916 | spec->dmaq_id = dmaq_id; |
| 2917 | } else if (!replacing) { |
| 2918 | kfree(spec); |
| 2919 | spec = NULL; |
| 2920 | } |
| 2921 | efx_ef10_filter_set_entry(table, ins_index, spec, 0); |
| 2922 | spin_unlock_bh(&efx->filter_lock); |
| 2923 | |
| 2924 | wake_up_all(&table->waitq); |
| 2925 | } |
| 2926 | |
| 2927 | static void |
| 2928 | efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, |
| 2929 | unsigned long filter_idx, |
| 2930 | int rc, efx_dword_t *outbuf, |
| 2931 | size_t outlen_actual); |
| 2932 | |
| 2933 | static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, |
| 2934 | unsigned int filter_idx) |
| 2935 | { |
| 2936 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2937 | struct efx_filter_spec *spec = |
| 2938 | efx_ef10_filter_entry_spec(table, filter_idx); |
| 2939 | MCDI_DECLARE_BUF(inbuf, |
| 2940 | MC_CMD_FILTER_OP_IN_HANDLE_OFST + |
| 2941 | MC_CMD_FILTER_OP_IN_HANDLE_LEN); |
| 2942 | |
| 2943 | if (!spec || |
| 2944 | (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || |
| 2945 | spec->priority != EFX_FILTER_PRI_HINT || |
| 2946 | !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, |
| 2947 | flow_id, filter_idx)) |
| 2948 | return false; |
| 2949 | |
| 2950 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, |
| 2951 | MC_CMD_FILTER_OP_IN_OP_REMOVE); |
| 2952 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, |
| 2953 | table->entry[filter_idx].handle); |
| 2954 | if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, |
| 2955 | efx_ef10_filter_rfs_expire_complete, filter_idx)) |
| 2956 | return false; |
| 2957 | |
| 2958 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; |
| 2959 | return true; |
| 2960 | } |
| 2961 | |
| 2962 | static void |
| 2963 | efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, |
| 2964 | unsigned long filter_idx, |
| 2965 | int rc, efx_dword_t *outbuf, |
| 2966 | size_t outlen_actual) |
| 2967 | { |
| 2968 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 2969 | struct efx_filter_spec *spec = |
| 2970 | efx_ef10_filter_entry_spec(table, filter_idx); |
| 2971 | |
| 2972 | spin_lock_bh(&efx->filter_lock); |
| 2973 | if (rc == 0) { |
| 2974 | kfree(spec); |
| 2975 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); |
| 2976 | } |
| 2977 | table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; |
| 2978 | wake_up_all(&table->waitq); |
| 2979 | spin_unlock_bh(&efx->filter_lock); |
| 2980 | } |
| 2981 | |
| 2982 | #endif /* CONFIG_RFS_ACCEL */ |
| 2983 | |
| 2984 | static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) |
| 2985 | { |
| 2986 | int match_flags = 0; |
| 2987 | |
| 2988 | #define MAP_FLAG(gen_flag, mcdi_field) { \ |
| 2989 | u32 old_mcdi_flags = mcdi_flags; \ |
| 2990 | mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ |
| 2991 | mcdi_field ## _LBN); \ |
| 2992 | if (mcdi_flags != old_mcdi_flags) \ |
| 2993 | match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ |
| 2994 | } |
| 2995 | MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); |
| 2996 | MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); |
| 2997 | MAP_FLAG(REM_HOST, SRC_IP); |
| 2998 | MAP_FLAG(LOC_HOST, DST_IP); |
| 2999 | MAP_FLAG(REM_MAC, SRC_MAC); |
| 3000 | MAP_FLAG(REM_PORT, SRC_PORT); |
| 3001 | MAP_FLAG(LOC_MAC, DST_MAC); |
| 3002 | MAP_FLAG(LOC_PORT, DST_PORT); |
| 3003 | MAP_FLAG(ETHER_TYPE, ETHER_TYPE); |
| 3004 | MAP_FLAG(INNER_VID, INNER_VLAN); |
| 3005 | MAP_FLAG(OUTER_VID, OUTER_VLAN); |
| 3006 | MAP_FLAG(IP_PROTO, IP_PROTO); |
| 3007 | #undef MAP_FLAG |
| 3008 | |
| 3009 | /* Did we map them all? */ |
| 3010 | if (mcdi_flags) |
| 3011 | return -EINVAL; |
| 3012 | |
| 3013 | return match_flags; |
| 3014 | } |
| 3015 | |
| 3016 | static int efx_ef10_filter_table_probe(struct efx_nic *efx) |
| 3017 | { |
| 3018 | MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); |
| 3019 | MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); |
| 3020 | unsigned int pd_match_pri, pd_match_count; |
| 3021 | struct efx_ef10_filter_table *table; |
| 3022 | size_t outlen; |
| 3023 | int rc; |
| 3024 | |
| 3025 | table = kzalloc(sizeof(*table), GFP_KERNEL); |
| 3026 | if (!table) |
| 3027 | return -ENOMEM; |
| 3028 | |
| 3029 | /* Find out which RX filter types are supported, and their priorities */ |
| 3030 | MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, |
| 3031 | MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); |
| 3032 | rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, |
| 3033 | inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), |
| 3034 | &outlen); |
| 3035 | if (rc) |
| 3036 | goto fail; |
| 3037 | pd_match_count = MCDI_VAR_ARRAY_LEN( |
| 3038 | outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); |
| 3039 | table->rx_match_count = 0; |
| 3040 | |
| 3041 | for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { |
| 3042 | u32 mcdi_flags = |
| 3043 | MCDI_ARRAY_DWORD( |
| 3044 | outbuf, |
| 3045 | GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, |
| 3046 | pd_match_pri); |
| 3047 | rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); |
| 3048 | if (rc < 0) { |
| 3049 | netif_dbg(efx, probe, efx->net_dev, |
| 3050 | "%s: fw flags %#x pri %u not supported in driver\n", |
| 3051 | __func__, mcdi_flags, pd_match_pri); |
| 3052 | } else { |
| 3053 | netif_dbg(efx, probe, efx->net_dev, |
| 3054 | "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", |
| 3055 | __func__, mcdi_flags, pd_match_pri, |
| 3056 | rc, table->rx_match_count); |
| 3057 | table->rx_match_flags[table->rx_match_count++] = rc; |
| 3058 | } |
| 3059 | } |
| 3060 | |
| 3061 | table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); |
| 3062 | if (!table->entry) { |
| 3063 | rc = -ENOMEM; |
| 3064 | goto fail; |
| 3065 | } |
| 3066 | |
| 3067 | efx->filter_state = table; |
| 3068 | init_waitqueue_head(&table->waitq); |
| 3069 | return 0; |
| 3070 | |
| 3071 | fail: |
| 3072 | kfree(table); |
| 3073 | return rc; |
| 3074 | } |
| 3075 | |
| 3076 | static void efx_ef10_filter_table_restore(struct efx_nic *efx) |
| 3077 | { |
| 3078 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 3079 | struct efx_ef10_nic_data *nic_data = efx->nic_data; |
| 3080 | struct efx_filter_spec *spec; |
| 3081 | unsigned int filter_idx; |
| 3082 | bool failed = false; |
| 3083 | int rc; |
| 3084 | |
| 3085 | if (!nic_data->must_restore_filters) |
| 3086 | return; |
| 3087 | |
| 3088 | spin_lock_bh(&efx->filter_lock); |
| 3089 | |
| 3090 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { |
| 3091 | spec = efx_ef10_filter_entry_spec(table, filter_idx); |
| 3092 | if (!spec) |
| 3093 | continue; |
| 3094 | |
| 3095 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; |
| 3096 | spin_unlock_bh(&efx->filter_lock); |
| 3097 | |
| 3098 | rc = efx_ef10_filter_push(efx, spec, |
| 3099 | &table->entry[filter_idx].handle, |
| 3100 | false); |
| 3101 | if (rc) |
| 3102 | failed = true; |
| 3103 | |
| 3104 | spin_lock_bh(&efx->filter_lock); |
| 3105 | if (rc) { |
| 3106 | kfree(spec); |
| 3107 | efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); |
| 3108 | } else { |
| 3109 | table->entry[filter_idx].spec &= |
| 3110 | ~EFX_EF10_FILTER_FLAG_BUSY; |
| 3111 | } |
| 3112 | } |
| 3113 | |
| 3114 | spin_unlock_bh(&efx->filter_lock); |
| 3115 | |
| 3116 | if (failed) |
| 3117 | netif_err(efx, hw, efx->net_dev, |
| 3118 | "unable to restore all filters\n"); |
| 3119 | else |
| 3120 | nic_data->must_restore_filters = false; |
| 3121 | } |
| 3122 | |
| 3123 | static void efx_ef10_filter_table_remove(struct efx_nic *efx) |
| 3124 | { |
| 3125 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 3126 | MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); |
| 3127 | struct efx_filter_spec *spec; |
| 3128 | unsigned int filter_idx; |
| 3129 | int rc; |
| 3130 | |
| 3131 | for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { |
| 3132 | spec = efx_ef10_filter_entry_spec(table, filter_idx); |
| 3133 | if (!spec) |
| 3134 | continue; |
| 3135 | |
| 3136 | MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, |
| 3137 | efx_ef10_filter_is_exclusive(spec) ? |
| 3138 | MC_CMD_FILTER_OP_IN_OP_REMOVE : |
| 3139 | MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); |
| 3140 | MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, |
| 3141 | table->entry[filter_idx].handle); |
| 3142 | rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), |
| 3143 | NULL, 0, NULL); |
Ben Hutchings | 48ce563 | 2013-11-01 16:42:44 +0000 | [diff] [blame] | 3144 | if (rc) |
| 3145 | netdev_WARN(efx->net_dev, |
| 3146 | "filter_idx=%#x handle=%#llx\n", |
| 3147 | filter_idx, |
| 3148 | table->entry[filter_idx].handle); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3149 | kfree(spec); |
| 3150 | } |
| 3151 | |
| 3152 | vfree(table->entry); |
| 3153 | kfree(table); |
| 3154 | } |
| 3155 | |
| 3156 | static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) |
| 3157 | { |
| 3158 | struct efx_ef10_filter_table *table = efx->filter_state; |
| 3159 | struct net_device *net_dev = efx->net_dev; |
| 3160 | struct efx_filter_spec spec; |
| 3161 | bool remove_failed = false; |
| 3162 | struct netdev_hw_addr *uc; |
| 3163 | struct netdev_hw_addr *mc; |
| 3164 | unsigned int filter_idx; |
| 3165 | int i, n, rc; |
| 3166 | |
| 3167 | if (!efx_dev_registered(efx)) |
| 3168 | return; |
| 3169 | |
| 3170 | /* Mark old filters that may need to be removed */ |
| 3171 | spin_lock_bh(&efx->filter_lock); |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3172 | n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3173 | for (i = 0; i < n; i++) { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3174 | filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS; |
| 3175 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3176 | } |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3177 | n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3178 | for (i = 0; i < n; i++) { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3179 | filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS; |
| 3180 | table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3181 | } |
| 3182 | spin_unlock_bh(&efx->filter_lock); |
| 3183 | |
| 3184 | /* Copy/convert the address lists; add the primary station |
| 3185 | * address and broadcast address |
| 3186 | */ |
| 3187 | netif_addr_lock_bh(net_dev); |
| 3188 | if (net_dev->flags & IFF_PROMISC || |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3189 | netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) { |
| 3190 | table->dev_uc_count = -1; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3191 | } else { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3192 | table->dev_uc_count = 1 + netdev_uc_count(net_dev); |
Edward Cree | cd84ff4 | 2014-03-07 18:27:41 +0000 | [diff] [blame] | 3193 | ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3194 | i = 1; |
| 3195 | netdev_for_each_uc_addr(uc, net_dev) { |
Edward Cree | cd84ff4 | 2014-03-07 18:27:41 +0000 | [diff] [blame] | 3196 | ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3197 | i++; |
| 3198 | } |
| 3199 | } |
| 3200 | if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) || |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3201 | netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) { |
| 3202 | table->dev_mc_count = -1; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3203 | } else { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3204 | table->dev_mc_count = 1 + netdev_mc_count(net_dev); |
| 3205 | eth_broadcast_addr(table->dev_mc_list[0].addr); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3206 | i = 1; |
| 3207 | netdev_for_each_mc_addr(mc, net_dev) { |
Edward Cree | cd84ff4 | 2014-03-07 18:27:41 +0000 | [diff] [blame] | 3208 | ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3209 | i++; |
| 3210 | } |
| 3211 | } |
| 3212 | netif_addr_unlock_bh(net_dev); |
| 3213 | |
| 3214 | /* Insert/renew unicast filters */ |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3215 | if (table->dev_uc_count >= 0) { |
| 3216 | for (i = 0; i < table->dev_uc_count; i++) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3217 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
| 3218 | EFX_FILTER_FLAG_RX_RSS, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3219 | 0); |
| 3220 | efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3221 | table->dev_uc_list[i].addr); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3222 | rc = efx_ef10_filter_insert(efx, &spec, true); |
| 3223 | if (rc < 0) { |
| 3224 | /* Fall back to unicast-promisc */ |
| 3225 | while (i--) |
| 3226 | efx_ef10_filter_remove_safe( |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3227 | efx, EFX_FILTER_PRI_AUTO, |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3228 | table->dev_uc_list[i].id); |
| 3229 | table->dev_uc_count = -1; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3230 | break; |
| 3231 | } |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3232 | table->dev_uc_list[i].id = rc; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3233 | } |
| 3234 | } |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3235 | if (table->dev_uc_count < 0) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3236 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
| 3237 | EFX_FILTER_FLAG_RX_RSS, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3238 | 0); |
| 3239 | efx_filter_set_uc_def(&spec); |
| 3240 | rc = efx_ef10_filter_insert(efx, &spec, true); |
| 3241 | if (rc < 0) { |
| 3242 | WARN_ON(1); |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3243 | table->dev_uc_count = 0; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3244 | } else { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3245 | table->dev_uc_list[0].id = rc; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3246 | } |
| 3247 | } |
| 3248 | |
| 3249 | /* Insert/renew multicast filters */ |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3250 | if (table->dev_mc_count >= 0) { |
| 3251 | for (i = 0; i < table->dev_mc_count; i++) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3252 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
| 3253 | EFX_FILTER_FLAG_RX_RSS, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3254 | 0); |
| 3255 | efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3256 | table->dev_mc_list[i].addr); |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3257 | rc = efx_ef10_filter_insert(efx, &spec, true); |
| 3258 | if (rc < 0) { |
| 3259 | /* Fall back to multicast-promisc */ |
| 3260 | while (i--) |
| 3261 | efx_ef10_filter_remove_safe( |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3262 | efx, EFX_FILTER_PRI_AUTO, |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3263 | table->dev_mc_list[i].id); |
| 3264 | table->dev_mc_count = -1; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3265 | break; |
| 3266 | } |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3267 | table->dev_mc_list[i].id = rc; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3268 | } |
| 3269 | } |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3270 | if (table->dev_mc_count < 0) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3271 | efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, |
| 3272 | EFX_FILTER_FLAG_RX_RSS, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3273 | 0); |
| 3274 | efx_filter_set_mc_def(&spec); |
| 3275 | rc = efx_ef10_filter_insert(efx, &spec, true); |
| 3276 | if (rc < 0) { |
| 3277 | WARN_ON(1); |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3278 | table->dev_mc_count = 0; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3279 | } else { |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3280 | table->dev_mc_list[0].id = rc; |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3281 | } |
| 3282 | } |
| 3283 | |
| 3284 | /* Remove filters that weren't renewed. Since nothing else |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3285 | * changes the AUTO_OLD flag or removes these filters, we |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3286 | * don't need to hold the filter_lock while scanning for |
| 3287 | * these filters. |
| 3288 | */ |
| 3289 | for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { |
| 3290 | if (ACCESS_ONCE(table->entry[i].spec) & |
Ben Hutchings | b59e6ef | 2013-11-21 19:02:22 +0000 | [diff] [blame] | 3291 | EFX_EF10_FILTER_FLAG_AUTO_OLD) { |
Ben Hutchings | 7665d1a | 2013-11-21 19:02:18 +0000 | [diff] [blame] | 3292 | if (efx_ef10_filter_remove_internal( |
Ben Hutchings | fbd7912 | 2013-11-21 19:15:03 +0000 | [diff] [blame] | 3293 | efx, 1U << EFX_FILTER_PRI_AUTO, |
| 3294 | i, true) < 0) |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3295 | remove_failed = true; |
| 3296 | } |
| 3297 | } |
| 3298 | WARN_ON(remove_failed); |
| 3299 | } |
| 3300 | |
| 3301 | static int efx_ef10_mac_reconfigure(struct efx_nic *efx) |
| 3302 | { |
| 3303 | efx_ef10_filter_sync_rx_mode(efx); |
| 3304 | |
| 3305 | return efx_mcdi_set_mac(efx); |
| 3306 | } |
| 3307 | |
Jon Cooper | 74cd60a | 2013-09-16 14:18:51 +0100 | [diff] [blame] | 3308 | static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) |
| 3309 | { |
| 3310 | MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); |
| 3311 | |
| 3312 | MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); |
| 3313 | return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), |
| 3314 | NULL, 0, NULL); |
| 3315 | } |
| 3316 | |
| 3317 | /* MC BISTs follow a different poll mechanism to phy BISTs. |
| 3318 | * The BIST is done in the poll handler on the MC, and the MCDI command |
| 3319 | * will block until the BIST is done. |
| 3320 | */ |
| 3321 | static int efx_ef10_poll_bist(struct efx_nic *efx) |
| 3322 | { |
| 3323 | int rc; |
| 3324 | MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); |
| 3325 | size_t outlen; |
| 3326 | u32 result; |
| 3327 | |
| 3328 | rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, |
| 3329 | outbuf, sizeof(outbuf), &outlen); |
| 3330 | if (rc != 0) |
| 3331 | return rc; |
| 3332 | |
| 3333 | if (outlen < MC_CMD_POLL_BIST_OUT_LEN) |
| 3334 | return -EIO; |
| 3335 | |
| 3336 | result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); |
| 3337 | switch (result) { |
| 3338 | case MC_CMD_POLL_BIST_PASSED: |
| 3339 | netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); |
| 3340 | return 0; |
| 3341 | case MC_CMD_POLL_BIST_TIMEOUT: |
| 3342 | netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); |
| 3343 | return -EIO; |
| 3344 | case MC_CMD_POLL_BIST_FAILED: |
| 3345 | netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); |
| 3346 | return -EIO; |
| 3347 | default: |
| 3348 | netif_err(efx, hw, efx->net_dev, |
| 3349 | "BIST returned unknown result %u", result); |
| 3350 | return -EIO; |
| 3351 | } |
| 3352 | } |
| 3353 | |
| 3354 | static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) |
| 3355 | { |
| 3356 | int rc; |
| 3357 | |
| 3358 | netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); |
| 3359 | |
| 3360 | rc = efx_ef10_start_bist(efx, bist_type); |
| 3361 | if (rc != 0) |
| 3362 | return rc; |
| 3363 | |
| 3364 | return efx_ef10_poll_bist(efx); |
| 3365 | } |
| 3366 | |
| 3367 | static int |
| 3368 | efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) |
| 3369 | { |
| 3370 | int rc, rc2; |
| 3371 | |
| 3372 | efx_reset_down(efx, RESET_TYPE_WORLD); |
| 3373 | |
| 3374 | rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, |
| 3375 | NULL, 0, NULL, 0, NULL); |
| 3376 | if (rc != 0) |
| 3377 | goto out; |
| 3378 | |
| 3379 | tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; |
| 3380 | tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; |
| 3381 | |
| 3382 | rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); |
| 3383 | |
| 3384 | out: |
| 3385 | rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); |
| 3386 | return rc ? rc : rc2; |
| 3387 | } |
| 3388 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3389 | #ifdef CONFIG_SFC_MTD |
| 3390 | |
| 3391 | struct efx_ef10_nvram_type_info { |
| 3392 | u16 type, type_mask; |
| 3393 | u8 port; |
| 3394 | const char *name; |
| 3395 | }; |
| 3396 | |
| 3397 | static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { |
| 3398 | { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, |
| 3399 | { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, |
| 3400 | { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, |
| 3401 | { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, |
| 3402 | { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, |
| 3403 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, |
| 3404 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, |
| 3405 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, |
| 3406 | { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, |
Ben Hutchings | a84f3bf9 | 2013-10-09 14:14:41 +0100 | [diff] [blame] | 3407 | { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3408 | { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, |
| 3409 | }; |
| 3410 | |
| 3411 | static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, |
| 3412 | struct efx_mcdi_mtd_partition *part, |
| 3413 | unsigned int type) |
| 3414 | { |
| 3415 | MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); |
| 3416 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); |
| 3417 | const struct efx_ef10_nvram_type_info *info; |
| 3418 | size_t size, erase_size, outlen; |
| 3419 | bool protected; |
| 3420 | int rc; |
| 3421 | |
| 3422 | for (info = efx_ef10_nvram_types; ; info++) { |
| 3423 | if (info == |
| 3424 | efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) |
| 3425 | return -ENODEV; |
| 3426 | if ((type & ~info->type_mask) == info->type) |
| 3427 | break; |
| 3428 | } |
| 3429 | if (info->port != efx_port_num(efx)) |
| 3430 | return -ENODEV; |
| 3431 | |
| 3432 | rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); |
| 3433 | if (rc) |
| 3434 | return rc; |
| 3435 | if (protected) |
| 3436 | return -ENODEV; /* hide it */ |
| 3437 | |
| 3438 | part->nvram_type = type; |
| 3439 | |
| 3440 | MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); |
| 3441 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), |
| 3442 | outbuf, sizeof(outbuf), &outlen); |
| 3443 | if (rc) |
| 3444 | return rc; |
| 3445 | if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) |
| 3446 | return -EIO; |
| 3447 | if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & |
| 3448 | (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) |
| 3449 | part->fw_subtype = MCDI_DWORD(outbuf, |
| 3450 | NVRAM_METADATA_OUT_SUBTYPE); |
| 3451 | |
| 3452 | part->common.dev_type_name = "EF10 NVRAM manager"; |
| 3453 | part->common.type_name = info->name; |
| 3454 | |
| 3455 | part->common.mtd.type = MTD_NORFLASH; |
| 3456 | part->common.mtd.flags = MTD_CAP_NORFLASH; |
| 3457 | part->common.mtd.size = size; |
| 3458 | part->common.mtd.erasesize = erase_size; |
| 3459 | |
| 3460 | return 0; |
| 3461 | } |
| 3462 | |
| 3463 | static int efx_ef10_mtd_probe(struct efx_nic *efx) |
| 3464 | { |
| 3465 | MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); |
| 3466 | struct efx_mcdi_mtd_partition *parts; |
| 3467 | size_t outlen, n_parts_total, i, n_parts; |
| 3468 | unsigned int type; |
| 3469 | int rc; |
| 3470 | |
| 3471 | ASSERT_RTNL(); |
| 3472 | |
| 3473 | BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); |
| 3474 | rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, |
| 3475 | outbuf, sizeof(outbuf), &outlen); |
| 3476 | if (rc) |
| 3477 | return rc; |
| 3478 | if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) |
| 3479 | return -EIO; |
| 3480 | |
| 3481 | n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); |
| 3482 | if (n_parts_total > |
| 3483 | MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) |
| 3484 | return -EIO; |
| 3485 | |
| 3486 | parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); |
| 3487 | if (!parts) |
| 3488 | return -ENOMEM; |
| 3489 | |
| 3490 | n_parts = 0; |
| 3491 | for (i = 0; i < n_parts_total; i++) { |
| 3492 | type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, |
| 3493 | i); |
| 3494 | rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); |
| 3495 | if (rc == 0) |
| 3496 | n_parts++; |
| 3497 | else if (rc != -ENODEV) |
| 3498 | goto fail; |
| 3499 | } |
| 3500 | |
| 3501 | rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); |
| 3502 | fail: |
| 3503 | if (rc) |
| 3504 | kfree(parts); |
| 3505 | return rc; |
| 3506 | } |
| 3507 | |
| 3508 | #endif /* CONFIG_SFC_MTD */ |
| 3509 | |
| 3510 | static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) |
| 3511 | { |
| 3512 | _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); |
| 3513 | } |
| 3514 | |
Jon Cooper | bd9a265 | 2013-11-18 12:54:41 +0000 | [diff] [blame] | 3515 | static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, |
| 3516 | bool temp) |
| 3517 | { |
| 3518 | MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); |
| 3519 | int rc; |
| 3520 | |
| 3521 | if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || |
| 3522 | channel->sync_events_state == SYNC_EVENTS_VALID || |
| 3523 | (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) |
| 3524 | return 0; |
| 3525 | channel->sync_events_state = SYNC_EVENTS_REQUESTED; |
| 3526 | |
| 3527 | MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); |
| 3528 | MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); |
| 3529 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, |
| 3530 | channel->channel); |
| 3531 | |
| 3532 | rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, |
| 3533 | inbuf, sizeof(inbuf), NULL, 0, NULL); |
| 3534 | |
| 3535 | if (rc != 0) |
| 3536 | channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : |
| 3537 | SYNC_EVENTS_DISABLED; |
| 3538 | |
| 3539 | return rc; |
| 3540 | } |
| 3541 | |
| 3542 | static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, |
| 3543 | bool temp) |
| 3544 | { |
| 3545 | MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); |
| 3546 | int rc; |
| 3547 | |
| 3548 | if (channel->sync_events_state == SYNC_EVENTS_DISABLED || |
| 3549 | (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) |
| 3550 | return 0; |
| 3551 | if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { |
| 3552 | channel->sync_events_state = SYNC_EVENTS_DISABLED; |
| 3553 | return 0; |
| 3554 | } |
| 3555 | channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : |
| 3556 | SYNC_EVENTS_DISABLED; |
| 3557 | |
| 3558 | MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); |
| 3559 | MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); |
| 3560 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, |
| 3561 | MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); |
| 3562 | MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, |
| 3563 | channel->channel); |
| 3564 | |
| 3565 | rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, |
| 3566 | inbuf, sizeof(inbuf), NULL, 0, NULL); |
| 3567 | |
| 3568 | return rc; |
| 3569 | } |
| 3570 | |
| 3571 | static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, |
| 3572 | bool temp) |
| 3573 | { |
| 3574 | int (*set)(struct efx_channel *channel, bool temp); |
| 3575 | struct efx_channel *channel; |
| 3576 | |
| 3577 | set = en ? |
| 3578 | efx_ef10_rx_enable_timestamping : |
| 3579 | efx_ef10_rx_disable_timestamping; |
| 3580 | |
| 3581 | efx_for_each_channel(channel, efx) { |
| 3582 | int rc = set(channel, temp); |
| 3583 | if (en && rc != 0) { |
| 3584 | efx_ef10_ptp_set_ts_sync_events(efx, false, temp); |
| 3585 | return rc; |
| 3586 | } |
| 3587 | } |
| 3588 | |
| 3589 | return 0; |
| 3590 | } |
| 3591 | |
| 3592 | static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, |
| 3593 | struct hwtstamp_config *init) |
| 3594 | { |
| 3595 | int rc; |
| 3596 | |
| 3597 | switch (init->rx_filter) { |
| 3598 | case HWTSTAMP_FILTER_NONE: |
| 3599 | efx_ef10_ptp_set_ts_sync_events(efx, false, false); |
| 3600 | /* if TX timestamping is still requested then leave PTP on */ |
| 3601 | return efx_ptp_change_mode(efx, |
| 3602 | init->tx_type != HWTSTAMP_TX_OFF, 0); |
| 3603 | case HWTSTAMP_FILTER_ALL: |
| 3604 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
| 3605 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
| 3606 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
| 3607 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
| 3608 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
| 3609 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
| 3610 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
| 3611 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
| 3612 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
| 3613 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
| 3614 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
| 3615 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
| 3616 | init->rx_filter = HWTSTAMP_FILTER_ALL; |
| 3617 | rc = efx_ptp_change_mode(efx, true, 0); |
| 3618 | if (!rc) |
| 3619 | rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); |
| 3620 | if (rc) |
| 3621 | efx_ptp_change_mode(efx, false, 0); |
| 3622 | return rc; |
| 3623 | default: |
| 3624 | return -ERANGE; |
| 3625 | } |
| 3626 | } |
| 3627 | |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3628 | const struct efx_nic_type efx_hunt_a0_nic_type = { |
| 3629 | .mem_map_size = efx_ef10_mem_map_size, |
| 3630 | .probe = efx_ef10_probe, |
| 3631 | .remove = efx_ef10_remove, |
| 3632 | .dimension_resources = efx_ef10_dimension_resources, |
| 3633 | .init = efx_ef10_init_nic, |
| 3634 | .fini = efx_port_dummy_op_void, |
| 3635 | .map_reset_reason = efx_mcdi_map_reset_reason, |
| 3636 | .map_reset_flags = efx_ef10_map_reset_flags, |
Jon Cooper | 3e33626 | 2014-01-17 19:48:06 +0000 | [diff] [blame] | 3637 | .reset = efx_ef10_reset, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3638 | .probe_port = efx_mcdi_port_probe, |
| 3639 | .remove_port = efx_mcdi_port_remove, |
| 3640 | .fini_dmaq = efx_ef10_fini_dmaq, |
Edward Cree | e283546 | 2014-04-16 19:27:48 +0100 | [diff] [blame] | 3641 | .prepare_flr = efx_ef10_prepare_flr, |
| 3642 | .finish_flr = efx_port_dummy_op_void, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3643 | .describe_stats = efx_ef10_describe_stats, |
| 3644 | .update_stats = efx_ef10_update_stats, |
| 3645 | .start_stats = efx_mcdi_mac_start_stats, |
Jon Cooper | f8f3b5a | 2013-09-30 17:36:50 +0100 | [diff] [blame] | 3646 | .pull_stats = efx_mcdi_mac_pull_stats, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3647 | .stop_stats = efx_mcdi_mac_stop_stats, |
| 3648 | .set_id_led = efx_mcdi_set_id_led, |
| 3649 | .push_irq_moderation = efx_ef10_push_irq_moderation, |
| 3650 | .reconfigure_mac = efx_ef10_mac_reconfigure, |
| 3651 | .check_mac_fault = efx_mcdi_mac_check_fault, |
| 3652 | .reconfigure_port = efx_mcdi_port_reconfigure, |
| 3653 | .get_wol = efx_ef10_get_wol, |
| 3654 | .set_wol = efx_ef10_set_wol, |
| 3655 | .resume_wol = efx_port_dummy_op_void, |
Jon Cooper | 74cd60a | 2013-09-16 14:18:51 +0100 | [diff] [blame] | 3656 | .test_chip = efx_ef10_test_chip, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3657 | .test_nvram = efx_mcdi_nvram_test_all, |
| 3658 | .mcdi_request = efx_ef10_mcdi_request, |
| 3659 | .mcdi_poll_response = efx_ef10_mcdi_poll_response, |
| 3660 | .mcdi_read_response = efx_ef10_mcdi_read_response, |
| 3661 | .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, |
| 3662 | .irq_enable_master = efx_port_dummy_op_void, |
| 3663 | .irq_test_generate = efx_ef10_irq_test_generate, |
| 3664 | .irq_disable_non_ev = efx_port_dummy_op_void, |
| 3665 | .irq_handle_msi = efx_ef10_msi_interrupt, |
| 3666 | .irq_handle_legacy = efx_ef10_legacy_interrupt, |
| 3667 | .tx_probe = efx_ef10_tx_probe, |
| 3668 | .tx_init = efx_ef10_tx_init, |
| 3669 | .tx_remove = efx_ef10_tx_remove, |
| 3670 | .tx_write = efx_ef10_tx_write, |
Andrew Rybchenko | d43050c | 2013-11-14 09:00:27 +0400 | [diff] [blame] | 3671 | .rx_push_rss_config = efx_ef10_rx_push_rss_config, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3672 | .rx_probe = efx_ef10_rx_probe, |
| 3673 | .rx_init = efx_ef10_rx_init, |
| 3674 | .rx_remove = efx_ef10_rx_remove, |
| 3675 | .rx_write = efx_ef10_rx_write, |
| 3676 | .rx_defer_refill = efx_ef10_rx_defer_refill, |
| 3677 | .ev_probe = efx_ef10_ev_probe, |
| 3678 | .ev_init = efx_ef10_ev_init, |
| 3679 | .ev_fini = efx_ef10_ev_fini, |
| 3680 | .ev_remove = efx_ef10_ev_remove, |
| 3681 | .ev_process = efx_ef10_ev_process, |
| 3682 | .ev_read_ack = efx_ef10_ev_read_ack, |
| 3683 | .ev_test_generate = efx_ef10_ev_test_generate, |
| 3684 | .filter_table_probe = efx_ef10_filter_table_probe, |
| 3685 | .filter_table_restore = efx_ef10_filter_table_restore, |
| 3686 | .filter_table_remove = efx_ef10_filter_table_remove, |
| 3687 | .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, |
| 3688 | .filter_insert = efx_ef10_filter_insert, |
| 3689 | .filter_remove_safe = efx_ef10_filter_remove_safe, |
| 3690 | .filter_get_safe = efx_ef10_filter_get_safe, |
| 3691 | .filter_clear_rx = efx_ef10_filter_clear_rx, |
| 3692 | .filter_count_rx_used = efx_ef10_filter_count_rx_used, |
| 3693 | .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, |
| 3694 | .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, |
| 3695 | #ifdef CONFIG_RFS_ACCEL |
| 3696 | .filter_rfs_insert = efx_ef10_filter_rfs_insert, |
| 3697 | .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, |
| 3698 | #endif |
| 3699 | #ifdef CONFIG_SFC_MTD |
| 3700 | .mtd_probe = efx_ef10_mtd_probe, |
| 3701 | .mtd_rename = efx_mcdi_mtd_rename, |
| 3702 | .mtd_read = efx_mcdi_mtd_read, |
| 3703 | .mtd_erase = efx_mcdi_mtd_erase, |
| 3704 | .mtd_write = efx_mcdi_mtd_write, |
| 3705 | .mtd_sync = efx_mcdi_mtd_sync, |
| 3706 | #endif |
| 3707 | .ptp_write_host_time = efx_ef10_ptp_write_host_time, |
Jon Cooper | bd9a265 | 2013-11-18 12:54:41 +0000 | [diff] [blame] | 3708 | .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, |
| 3709 | .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, |
Shradha Shah | 7fa8d54 | 2015-05-06 00:55:13 +0100 | [diff] [blame] | 3710 | #ifdef CONFIG_SFC_SRIOV |
Shradha Shah | 834e23d | 2015-05-06 00:55:58 +0100 | [diff] [blame] | 3711 | .sriov_configure = efx_ef10_sriov_configure, |
Shradha Shah | d98a4ff | 2014-11-05 12:16:46 +0000 | [diff] [blame] | 3712 | .sriov_init = efx_ef10_sriov_init, |
| 3713 | .sriov_fini = efx_ef10_sriov_fini, |
| 3714 | .sriov_mac_address_changed = efx_ef10_sriov_mac_address_changed, |
| 3715 | .sriov_wanted = efx_ef10_sriov_wanted, |
| 3716 | .sriov_reset = efx_ef10_sriov_reset, |
Shradha Shah | 7fa8d54 | 2015-05-06 00:55:13 +0100 | [diff] [blame] | 3717 | .sriov_flr = efx_ef10_sriov_flr, |
| 3718 | .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, |
| 3719 | .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, |
| 3720 | .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, |
| 3721 | .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, |
Daniel Pieczko | 6d8aaaf | 2015-05-06 00:57:34 +0100 | [diff] [blame^] | 3722 | .vswitching_probe = efx_ef10_vswitching_probe, |
| 3723 | .vswitching_restore = efx_ef10_vswitching_restore, |
| 3724 | .vswitching_remove = efx_ef10_vswitching_remove, |
Shradha Shah | 7fa8d54 | 2015-05-06 00:55:13 +0100 | [diff] [blame] | 3725 | #endif |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3726 | |
| 3727 | .revision = EFX_REV_HUNT_A0, |
| 3728 | .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), |
| 3729 | .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, |
| 3730 | .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, |
Jon Cooper | bd9a265 | 2013-11-18 12:54:41 +0000 | [diff] [blame] | 3731 | .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3732 | .can_rx_scatter = true, |
| 3733 | .always_rx_scatter = true, |
| 3734 | .max_interrupt_mode = EFX_INT_MODE_MSIX, |
| 3735 | .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, |
| 3736 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 3737 | NETIF_F_RXHASH | NETIF_F_NTUPLE), |
| 3738 | .mcdi_max_ver = 2, |
| 3739 | .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, |
Jon Cooper | bd9a265 | 2013-11-18 12:54:41 +0000 | [diff] [blame] | 3740 | .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | |
| 3741 | 1 << HWTSTAMP_FILTER_ALL, |
Ben Hutchings | 8127d66 | 2013-08-29 19:19:29 +0100 | [diff] [blame] | 3742 | }; |