Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> |
| 3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> |
| 4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Adjustable divider clock implementation |
| 11 | */ |
| 12 | |
| 13 | #include <linux/clk-provider.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/string.h> |
| 19 | |
| 20 | /* |
| 21 | * DOC: basic adjustable divider clock that cannot gate |
| 22 | * |
| 23 | * Traits of this clock: |
| 24 | * prepare - clk_prepare only ensures that parents are prepared |
| 25 | * enable - clk_enable only ensures that parents are enabled |
| 26 | * rate - rate is adjustable. clk->rate = parent->rate / divisor |
| 27 | * parent - fixed parent. No clk_set_parent support |
| 28 | */ |
| 29 | |
| 30 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
| 31 | |
| 32 | #define div_mask(d) ((1 << (d->width)) - 1) |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 33 | #define is_power_of_two(i) !(i & ~i) |
| 34 | |
| 35 | static unsigned int _get_maxdiv(struct clk_divider *divider) |
| 36 | { |
| 37 | if (divider->flags & CLK_DIVIDER_ONE_BASED) |
| 38 | return div_mask(divider); |
| 39 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) |
| 40 | return 1 << div_mask(divider); |
| 41 | return div_mask(divider) + 1; |
| 42 | } |
| 43 | |
| 44 | static unsigned int _get_div(struct clk_divider *divider, unsigned int val) |
| 45 | { |
| 46 | if (divider->flags & CLK_DIVIDER_ONE_BASED) |
| 47 | return val; |
| 48 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) |
| 49 | return 1 << val; |
| 50 | return val + 1; |
| 51 | } |
| 52 | |
| 53 | static unsigned int _get_val(struct clk_divider *divider, u8 div) |
| 54 | { |
| 55 | if (divider->flags & CLK_DIVIDER_ONE_BASED) |
| 56 | return div; |
| 57 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) |
| 58 | return __ffs(div); |
| 59 | return div - 1; |
| 60 | } |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 61 | |
| 62 | static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, |
| 63 | unsigned long parent_rate) |
| 64 | { |
| 65 | struct clk_divider *divider = to_clk_divider(hw); |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 66 | unsigned int div, val; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 67 | |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 68 | val = readl(divider->reg) >> divider->shift; |
| 69 | val &= div_mask(divider); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 70 | |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 71 | div = _get_div(divider, val); |
| 72 | if (!div) { |
| 73 | WARN(1, "%s: Invalid divisor for clock %s\n", __func__, |
| 74 | __clk_get_name(hw->clk)); |
| 75 | return parent_rate; |
| 76 | } |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 77 | |
| 78 | return parent_rate / div; |
| 79 | } |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * The reverse of DIV_ROUND_UP: The maximum number which |
| 83 | * divided by m is r |
| 84 | */ |
| 85 | #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) |
| 86 | |
| 87 | static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, |
| 88 | unsigned long *best_parent_rate) |
| 89 | { |
| 90 | struct clk_divider *divider = to_clk_divider(hw); |
| 91 | int i, bestdiv = 0; |
| 92 | unsigned long parent_rate, best = 0, now, maxdiv; |
| 93 | |
| 94 | if (!rate) |
| 95 | rate = 1; |
| 96 | |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 97 | maxdiv = _get_maxdiv(divider); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 98 | |
Shawn Guo | 81536e0 | 2012-04-12 20:50:17 +0800 | [diff] [blame] | 99 | if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { |
| 100 | parent_rate = *best_parent_rate; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 101 | bestdiv = DIV_ROUND_UP(parent_rate, rate); |
| 102 | bestdiv = bestdiv == 0 ? 1 : bestdiv; |
| 103 | bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; |
| 104 | return bestdiv; |
| 105 | } |
| 106 | |
| 107 | /* |
| 108 | * The maximum divider we can use without overflowing |
| 109 | * unsigned long in rate * i below |
| 110 | */ |
| 111 | maxdiv = min(ULONG_MAX / rate, maxdiv); |
| 112 | |
| 113 | for (i = 1; i <= maxdiv; i++) { |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 114 | if ((divider->flags & CLK_DIVIDER_POWER_OF_TWO) |
| 115 | && (!is_power_of_two(i))) |
| 116 | continue; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 117 | parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), |
| 118 | MULT_ROUND_UP(rate, i)); |
| 119 | now = parent_rate / i; |
| 120 | if (now <= rate && now > best) { |
| 121 | bestdiv = i; |
| 122 | best = now; |
| 123 | *best_parent_rate = parent_rate; |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | if (!bestdiv) { |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 128 | bestdiv = _get_maxdiv(divider); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 129 | *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1); |
| 130 | } |
| 131 | |
| 132 | return bestdiv; |
| 133 | } |
| 134 | |
| 135 | static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, |
| 136 | unsigned long *prate) |
| 137 | { |
| 138 | int div; |
| 139 | div = clk_divider_bestdiv(hw, rate, prate); |
| 140 | |
Shawn Guo | 81536e0 | 2012-04-12 20:50:17 +0800 | [diff] [blame] | 141 | return *prate / div; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 142 | } |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 143 | |
Shawn Guo | 1c0035d | 2012-04-12 20:50:18 +0800 | [diff] [blame] | 144 | static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
| 145 | unsigned long parent_rate) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 146 | { |
| 147 | struct clk_divider *divider = to_clk_divider(hw); |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 148 | unsigned int div, value; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 149 | unsigned long flags = 0; |
| 150 | u32 val; |
| 151 | |
Shawn Guo | 1c0035d | 2012-04-12 20:50:18 +0800 | [diff] [blame] | 152 | div = parent_rate / rate; |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 153 | value = _get_val(divider, div); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 154 | |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 155 | if (value > div_mask(divider)) |
| 156 | value = div_mask(divider); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 157 | |
| 158 | if (divider->lock) |
| 159 | spin_lock_irqsave(divider->lock, flags); |
| 160 | |
| 161 | val = readl(divider->reg); |
| 162 | val &= ~(div_mask(divider) << divider->shift); |
Rajendra Nayak | 6d9252b | 2012-05-17 15:52:13 +0530 | [diff] [blame^] | 163 | val |= value << divider->shift; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 164 | writel(val, divider->reg); |
| 165 | |
| 166 | if (divider->lock) |
| 167 | spin_unlock_irqrestore(divider->lock, flags); |
| 168 | |
| 169 | return 0; |
| 170 | } |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 171 | |
Shawn Guo | 822c250 | 2012-03-27 15:23:22 +0800 | [diff] [blame] | 172 | const struct clk_ops clk_divider_ops = { |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 173 | .recalc_rate = clk_divider_recalc_rate, |
| 174 | .round_rate = clk_divider_round_rate, |
| 175 | .set_rate = clk_divider_set_rate, |
| 176 | }; |
| 177 | EXPORT_SYMBOL_GPL(clk_divider_ops); |
| 178 | |
Mike Turquette | 27d5459 | 2012-03-26 17:51:03 -0700 | [diff] [blame] | 179 | /** |
| 180 | * clk_register_divider - register a divider clock with the clock framework |
| 181 | * @dev: device registering this clock |
| 182 | * @name: name of this clock |
| 183 | * @parent_name: name of clock's parent |
| 184 | * @flags: framework-specific flags |
| 185 | * @reg: register address to adjust divider |
| 186 | * @shift: number of bits to shift the bitfield |
| 187 | * @width: width of the bitfield |
| 188 | * @clk_divider_flags: divider-specific flags for this clock |
| 189 | * @lock: shared register lock for this clock |
| 190 | */ |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 191 | struct clk *clk_register_divider(struct device *dev, const char *name, |
| 192 | const char *parent_name, unsigned long flags, |
| 193 | void __iomem *reg, u8 shift, u8 width, |
| 194 | u8 clk_divider_flags, spinlock_t *lock) |
| 195 | { |
| 196 | struct clk_divider *div; |
| 197 | struct clk *clk; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 198 | struct clk_init_data init; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 199 | |
Mike Turquette | 27d5459 | 2012-03-26 17:51:03 -0700 | [diff] [blame] | 200 | /* allocate the divider */ |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 201 | div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 202 | if (!div) { |
| 203 | pr_err("%s: could not allocate divider clk\n", __func__); |
Mike Turquette | 27d5459 | 2012-03-26 17:51:03 -0700 | [diff] [blame] | 204 | return ERR_PTR(-ENOMEM); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 205 | } |
| 206 | |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 207 | init.name = name; |
| 208 | init.ops = &clk_divider_ops; |
| 209 | init.flags = flags; |
| 210 | init.parent_names = (parent_name ? &parent_name: NULL); |
| 211 | init.num_parents = (parent_name ? 1 : 0); |
| 212 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 213 | /* struct clk_divider assignments */ |
| 214 | div->reg = reg; |
| 215 | div->shift = shift; |
| 216 | div->width = width; |
| 217 | div->flags = clk_divider_flags; |
| 218 | div->lock = lock; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 219 | div->hw.init = &init; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 220 | |
Mike Turquette | 27d5459 | 2012-03-26 17:51:03 -0700 | [diff] [blame] | 221 | /* register the clock */ |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 222 | clk = clk_register(dev, &div->hw); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 223 | |
Mike Turquette | 27d5459 | 2012-03-26 17:51:03 -0700 | [diff] [blame] | 224 | if (IS_ERR(clk)) |
| 225 | kfree(div); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 226 | |
Mike Turquette | 27d5459 | 2012-03-26 17:51:03 -0700 | [diff] [blame] | 227 | return clk; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 228 | } |