Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra30-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Thierry Reding | 6d9adf6 | 2014-09-24 15:33:44 +0200 | [diff] [blame^] | 3 | #include <dt-bindings/memory/tegra30-mc.h> |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 6 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 7 | #include "skeleton.dtsi" |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 8 | |
| 9 | / { |
| 10 | compatible = "nvidia,tegra30"; |
| 11 | interrupt-parent = <&intc>; |
| 12 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 13 | aliases { |
| 14 | serial0 = &uarta; |
| 15 | serial1 = &uartb; |
| 16 | serial2 = &uartc; |
| 17 | serial3 = &uartd; |
| 18 | serial4 = &uarte; |
| 19 | }; |
| 20 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 21 | pcie-controller@00003000 { |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 22 | compatible = "nvidia,tegra30-pcie"; |
| 23 | device_type = "pci"; |
| 24 | reg = <0x00003000 0x00000800 /* PADS registers */ |
| 25 | 0x00003800 0x00000200 /* AFI registers */ |
| 26 | 0x10000000 0x10000000>; /* configuration space */ |
| 27 | reg-names = "pads", "afi", "cs"; |
| 28 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ |
| 29 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| 30 | interrupt-names = "intr", "msi"; |
| 31 | |
Lucas Stach | 97070bd | 2014-03-05 14:25:46 +0100 | [diff] [blame] | 32 | #interrupt-cells = <1>; |
| 33 | interrupt-map-mask = <0 0 0 0>; |
| 34 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 35 | |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 36 | bus-range = <0x00 0xff>; |
| 37 | #address-cells = <3>; |
| 38 | #size-cells = <2>; |
| 39 | |
| 40 | ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ |
| 41 | 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ |
| 42 | 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ |
| 43 | 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ |
Jay Agarwal | d7283c1 | 2013-08-09 16:49:31 +0200 | [diff] [blame] | 44 | 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ |
| 45 | 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 46 | |
| 47 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, |
| 48 | <&tegra_car TEGRA30_CLK_AFI>, |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 49 | <&tegra_car TEGRA30_CLK_PLL_E>, |
| 50 | <&tegra_car TEGRA30_CLK_CML0>; |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 51 | clock-names = "pex", "afi", "pll_e", "cml"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 52 | resets = <&tegra_car 70>, |
| 53 | <&tegra_car 72>, |
| 54 | <&tegra_car 74>; |
| 55 | reset-names = "pex", "afi", "pcie_x"; |
Thierry Reding | e07e3db | 2013-08-09 16:49:26 +0200 | [diff] [blame] | 56 | status = "disabled"; |
| 57 | |
| 58 | pci@1,0 { |
| 59 | device_type = "pci"; |
| 60 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; |
| 61 | reg = <0x000800 0 0 0 0>; |
| 62 | status = "disabled"; |
| 63 | |
| 64 | #address-cells = <3>; |
| 65 | #size-cells = <2>; |
| 66 | ranges; |
| 67 | |
| 68 | nvidia,num-lanes = <2>; |
| 69 | }; |
| 70 | |
| 71 | pci@2,0 { |
| 72 | device_type = "pci"; |
| 73 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; |
| 74 | reg = <0x001000 0 0 0 0>; |
| 75 | status = "disabled"; |
| 76 | |
| 77 | #address-cells = <3>; |
| 78 | #size-cells = <2>; |
| 79 | ranges; |
| 80 | |
| 81 | nvidia,num-lanes = <2>; |
| 82 | }; |
| 83 | |
| 84 | pci@3,0 { |
| 85 | device_type = "pci"; |
| 86 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; |
| 87 | reg = <0x001800 0 0 0 0>; |
| 88 | status = "disabled"; |
| 89 | |
| 90 | #address-cells = <3>; |
| 91 | #size-cells = <2>; |
| 92 | ranges; |
| 93 | |
| 94 | nvidia,num-lanes = <2>; |
| 95 | }; |
| 96 | }; |
| 97 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 98 | host1x@50000000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 99 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
| 100 | reg = <0x50000000 0x00024000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 101 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 102 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 103 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 104 | resets = <&tegra_car 28>; |
| 105 | reset-names = "host1x"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 106 | |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <1>; |
| 109 | |
| 110 | ranges = <0x54000000 0x54000000 0x04000000>; |
| 111 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 112 | mpe@54040000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 113 | compatible = "nvidia,tegra30-mpe"; |
| 114 | reg = <0x54040000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 115 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 116 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 117 | resets = <&tegra_car 60>; |
| 118 | reset-names = "mpe"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 119 | }; |
| 120 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 121 | vi@54080000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 122 | compatible = "nvidia,tegra30-vi"; |
| 123 | reg = <0x54080000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 124 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 125 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 126 | resets = <&tegra_car 20>; |
| 127 | reset-names = "vi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 128 | }; |
| 129 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 130 | epp@540c0000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 131 | compatible = "nvidia,tegra30-epp"; |
| 132 | reg = <0x540c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 133 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 134 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 135 | resets = <&tegra_car 19>; |
| 136 | reset-names = "epp"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 137 | }; |
| 138 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 139 | isp@54100000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 140 | compatible = "nvidia,tegra30-isp"; |
| 141 | reg = <0x54100000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 142 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 143 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 144 | resets = <&tegra_car 23>; |
| 145 | reset-names = "isp"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 146 | }; |
| 147 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 148 | gr2d@54140000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 149 | compatible = "nvidia,tegra30-gr2d"; |
| 150 | reg = <0x54140000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 151 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Thierry Reding | da45d73 | 2014-01-06 16:20:42 +0100 | [diff] [blame] | 152 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 153 | resets = <&tegra_car 21>; |
| 154 | reset-names = "2d"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 155 | }; |
| 156 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 157 | gr3d@54180000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 158 | compatible = "nvidia,tegra30-gr3d"; |
| 159 | reg = <0x54180000 0x00040000>; |
Thierry Reding | c71d390 | 2013-10-15 17:28:02 +0200 | [diff] [blame] | 160 | clocks = <&tegra_car TEGRA30_CLK_GR3D |
| 161 | &tegra_car TEGRA30_CLK_GR3D2>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 162 | clock-names = "3d", "3d2"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 163 | resets = <&tegra_car 24>, |
| 164 | <&tegra_car 98>; |
| 165 | reset-names = "3d", "3d2"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | dc@54200000 { |
Thierry Reding | 05465f4 | 2013-10-15 17:27:51 +0200 | [diff] [blame] | 169 | compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 170 | reg = <0x54200000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 171 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 172 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
| 173 | <&tegra_car TEGRA30_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 174 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 175 | resets = <&tegra_car 27>; |
| 176 | reset-names = "dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 177 | |
Thierry Reding | 6d9adf6 | 2014-09-24 15:33:44 +0200 | [diff] [blame^] | 178 | iommus = <&mc TEGRA_SWGROUP_DC>; |
| 179 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 180 | nvidia,head = <0>; |
| 181 | |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 182 | rgb { |
| 183 | status = "disabled"; |
| 184 | }; |
| 185 | }; |
| 186 | |
| 187 | dc@54240000 { |
| 188 | compatible = "nvidia,tegra30-dc"; |
| 189 | reg = <0x54240000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 190 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 191 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
| 192 | <&tegra_car TEGRA30_CLK_PLL_P>; |
Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 193 | clock-names = "dc", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 194 | resets = <&tegra_car 26>; |
| 195 | reset-names = "dc"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 196 | |
Thierry Reding | 6d9adf6 | 2014-09-24 15:33:44 +0200 | [diff] [blame^] | 197 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
| 198 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 199 | nvidia,head = <1>; |
| 200 | |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 201 | rgb { |
| 202 | status = "disabled"; |
| 203 | }; |
| 204 | }; |
| 205 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 206 | hdmi@54280000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 207 | compatible = "nvidia,tegra30-hdmi"; |
| 208 | reg = <0x54280000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 209 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 210 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
| 211 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 212 | clock-names = "hdmi", "parent"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 213 | resets = <&tegra_car 51>; |
| 214 | reset-names = "hdmi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 215 | status = "disabled"; |
| 216 | }; |
| 217 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 218 | tvo@542c0000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 219 | compatible = "nvidia,tegra30-tvo"; |
| 220 | reg = <0x542c0000 0x00040000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 221 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 222 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 223 | status = "disabled"; |
| 224 | }; |
| 225 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 226 | dsi@54300000 { |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 227 | compatible = "nvidia,tegra30-dsi"; |
| 228 | reg = <0x54300000 0x00040000>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 229 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 230 | resets = <&tegra_car 48>; |
| 231 | reset-names = "dsi"; |
Thierry Reding | ed39097 | 2012-11-15 22:07:57 +0100 | [diff] [blame] | 232 | status = "disabled"; |
| 233 | }; |
| 234 | }; |
| 235 | |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 236 | timer@50004600 { |
| 237 | compatible = "arm,cortex-a9-twd-timer"; |
| 238 | reg = <0x50040600 0x20>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 239 | interrupts = <GIC_PPI 13 |
| 240 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 241 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
Stephen Warren | 73368ba | 2012-09-19 14:17:24 -0600 | [diff] [blame] | 242 | }; |
| 243 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 244 | intc: interrupt-controller@50041000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 245 | compatible = "arm,cortex-a9-gic"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 246 | reg = <0x50041000 0x1000 |
| 247 | 0x50040100 0x0100>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 248 | interrupt-controller; |
| 249 | #interrupt-cells = <3>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 250 | }; |
| 251 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 252 | cache-controller@50043000 { |
Stephen Warren | bb2c1de | 2013-01-14 10:09:16 -0700 | [diff] [blame] | 253 | compatible = "arm,pl310-cache"; |
| 254 | reg = <0x50043000 0x1000>; |
| 255 | arm,data-latency = <6 6 2>; |
| 256 | arm,tag-latency = <5 5 2>; |
| 257 | cache-unified; |
| 258 | cache-level = <2>; |
| 259 | }; |
| 260 | |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 261 | timer@60005000 { |
| 262 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| 263 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 264 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 265 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 266 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 267 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 268 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 269 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 270 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
Stephen Warren | 2f2b7fb | 2012-09-19 12:02:31 -0600 | [diff] [blame] | 271 | }; |
| 272 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 273 | tegra_car: clock@60006000 { |
Prashant Gaikwad | 9598566 | 2013-01-11 13:16:23 +0530 | [diff] [blame] | 274 | compatible = "nvidia,tegra30-car"; |
| 275 | reg = <0x60006000 0x1000>; |
| 276 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 277 | #reset-cells = <1>; |
Prashant Gaikwad | 9598566 | 2013-01-11 13:16:23 +0530 | [diff] [blame] | 278 | }; |
| 279 | |
Thierry Reding | b102313 | 2014-08-26 08:14:03 +0200 | [diff] [blame] | 280 | flow-controller@60007000 { |
| 281 | compatible = "nvidia,tegra30-flowctrl"; |
| 282 | reg = <0x60007000 0x1000>; |
| 283 | }; |
| 284 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 285 | apbdma: dma@6000a000 { |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 286 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| 287 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 288 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 289 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 290 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 291 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 292 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 293 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 294 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 295 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 296 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 297 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 298 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 299 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 300 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 301 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 302 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 303 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 304 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 305 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 306 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 307 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 308 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 309 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 310 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 311 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 312 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 313 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 314 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 315 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 316 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 317 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 318 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 319 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 320 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 321 | resets = <&tegra_car 34>; |
| 322 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 323 | #dma-cells = <1>; |
Stephen Warren | 8051b75 | 2012-01-11 16:09:54 -0700 | [diff] [blame] | 324 | }; |
| 325 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 326 | ahb: ahb@6000c004 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 327 | compatible = "nvidia,tegra30-ahb"; |
| 328 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ |
| 329 | }; |
| 330 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 331 | gpio: gpio@6000d000 { |
Laxman Dewangan | 35f210e | 2012-12-19 20:27:12 +0530 | [diff] [blame] | 332 | compatible = "nvidia,tegra30-gpio"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 333 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 334 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 335 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 336 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 337 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 338 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 339 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 340 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 341 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 342 | #gpio-cells = <2>; |
| 343 | gpio-controller; |
| 344 | #interrupt-cells = <2>; |
| 345 | interrupt-controller; |
| 346 | }; |
| 347 | |
Peter De Schrijver | 155dfc7 | 2014-06-12 18:36:38 +0300 | [diff] [blame] | 348 | apbmisc@70000800 { |
| 349 | compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; |
| 350 | reg = <0x70000800 0x64 /* Chip revision */ |
| 351 | 0x70000008 0x04>; /* Strapping options */ |
| 352 | }; |
| 353 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 354 | pinmux: pinmux@70000868 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 355 | compatible = "nvidia,tegra30-pinmux"; |
Pritesh Raithatha | 322337b | 2012-10-30 15:37:09 +0530 | [diff] [blame] | 356 | reg = <0x70000868 0xd4 /* Pad control registers */ |
| 357 | 0x70003000 0x3e4>; /* Mux registers */ |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 358 | }; |
| 359 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 360 | /* |
| 361 | * There are two serial driver i.e. 8250 based simple serial |
| 362 | * driver and APB DMA based serial driver for higher baudrate |
| 363 | * and performace. To enable the 8250 based driver, the compatible |
| 364 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable |
| 365 | * the APB DMA based serial driver, the comptible is |
| 366 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| 367 | */ |
| 368 | uarta: serial@70006000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 369 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 370 | reg = <0x70006000 0x40>; |
| 371 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 372 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 373 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 374 | resets = <&tegra_car 6>; |
| 375 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 376 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 377 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 378 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 379 | }; |
| 380 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 381 | uartb: serial@70006040 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 382 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 383 | reg = <0x70006040 0x40>; |
| 384 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 385 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 386 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 387 | resets = <&tegra_car 7>; |
| 388 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 389 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 390 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 391 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 392 | }; |
| 393 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 394 | uartc: serial@70006200 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 395 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 396 | reg = <0x70006200 0x100>; |
| 397 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 398 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 399 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 400 | resets = <&tegra_car 55>; |
| 401 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 402 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 403 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 404 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 405 | }; |
| 406 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 407 | uartd: serial@70006300 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 408 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 409 | reg = <0x70006300 0x100>; |
| 410 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 411 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 412 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 413 | resets = <&tegra_car 65>; |
| 414 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 415 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 416 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 417 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 418 | }; |
| 419 | |
Laxman Dewangan | b6551bb | 2012-12-19 12:01:11 +0530 | [diff] [blame] | 420 | uarte: serial@70006400 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 421 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 422 | reg = <0x70006400 0x100>; |
| 423 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 424 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 425 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 426 | resets = <&tegra_car 66>; |
| 427 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 428 | dmas = <&apbdma 20>, <&apbdma 20>; |
| 429 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 430 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 431 | }; |
| 432 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 433 | pwm: pwm@7000a000 { |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 434 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| 435 | reg = <0x7000a000 0x100>; |
| 436 | #pwm-cells = <2>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 437 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 438 | resets = <&tegra_car 17>; |
| 439 | reset-names = "pwm"; |
Andrew Chew | b69cd98 | 2013-03-12 16:40:51 -0700 | [diff] [blame] | 440 | status = "disabled"; |
Thierry Reding | 140fd97 | 2011-12-21 08:04:13 +0100 | [diff] [blame] | 441 | }; |
| 442 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 443 | rtc@7000e000 { |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 444 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 445 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 446 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 447 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
Stephen Warren | 380e04a | 2012-09-19 12:13:16 -0600 | [diff] [blame] | 448 | }; |
| 449 | |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 450 | i2c@7000c000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 451 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 452 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 453 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 454 | #address-cells = <1>; |
| 455 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 456 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
| 457 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 458 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 459 | resets = <&tegra_car 12>; |
| 460 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 461 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 462 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 463 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 464 | }; |
| 465 | |
| 466 | i2c@7000c400 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 467 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 468 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 469 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 470 | #address-cells = <1>; |
| 471 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 472 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
| 473 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 474 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 475 | resets = <&tegra_car 54>; |
| 476 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 477 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 478 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 479 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 480 | }; |
| 481 | |
| 482 | i2c@7000c500 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 483 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 484 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 485 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 486 | #address-cells = <1>; |
| 487 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 488 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
| 489 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 490 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 491 | resets = <&tegra_car 67>; |
| 492 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 493 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 494 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 495 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | i2c@7000c700 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 499 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 500 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 501 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 502 | #address-cells = <1>; |
| 503 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 504 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
| 505 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 506 | resets = <&tegra_car 103>; |
| 507 | reset-names = "i2c"; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 508 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 509 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 510 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 511 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 512 | }; |
| 513 | |
| 514 | i2c@7000d000 { |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 515 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
Stephen Warren | ba04c28 | 2012-05-11 16:28:59 -0600 | [diff] [blame] | 516 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 517 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 2eaab06 | 2012-05-11 17:12:52 -0600 | [diff] [blame] | 518 | #address-cells = <1>; |
| 519 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 520 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
| 521 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
Prashant Gaikwad | 1cbc733 | 2013-01-11 13:31:22 +0530 | [diff] [blame] | 522 | clock-names = "div-clk", "fast-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 523 | resets = <&tegra_car 47>; |
| 524 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 525 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 526 | dma-names = "rx", "tx"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 527 | status = "disabled"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 528 | }; |
| 529 | |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 530 | spi@7000d400 { |
| 531 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 532 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 533 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 534 | #address-cells = <1>; |
| 535 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 536 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 537 | resets = <&tegra_car 41>; |
| 538 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 539 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 540 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 541 | status = "disabled"; |
| 542 | }; |
| 543 | |
| 544 | spi@7000d600 { |
| 545 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 546 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 547 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 548 | #address-cells = <1>; |
| 549 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 550 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 551 | resets = <&tegra_car 44>; |
| 552 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 553 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 554 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | spi@7000d800 { |
| 559 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
Laxman Dewangan | 57471c8 | 2013-03-22 12:35:06 -0600 | [diff] [blame] | 560 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 561 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 562 | #address-cells = <1>; |
| 563 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 564 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 565 | resets = <&tegra_car 46>; |
| 566 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 567 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 568 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 569 | status = "disabled"; |
| 570 | }; |
| 571 | |
| 572 | spi@7000da00 { |
| 573 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 574 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 575 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 576 | #address-cells = <1>; |
| 577 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 578 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 579 | resets = <&tegra_car 68>; |
| 580 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 581 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 582 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 583 | status = "disabled"; |
| 584 | }; |
| 585 | |
| 586 | spi@7000dc00 { |
| 587 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 588 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 589 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 590 | #address-cells = <1>; |
| 591 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 592 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 593 | resets = <&tegra_car 104>; |
| 594 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 595 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 596 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 597 | status = "disabled"; |
| 598 | }; |
| 599 | |
| 600 | spi@7000de00 { |
| 601 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 602 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 603 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 604 | #address-cells = <1>; |
| 605 | #size-cells = <0>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 606 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 607 | resets = <&tegra_car 106>; |
| 608 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 609 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 610 | dma-names = "rx", "tx"; |
Laxman Dewangan | a86b0db | 2012-10-30 12:35:23 +0530 | [diff] [blame] | 611 | status = "disabled"; |
| 612 | }; |
| 613 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 614 | kbc@7000e200 { |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 615 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
| 616 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 617 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 618 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 619 | resets = <&tegra_car 36>; |
| 620 | reset-names = "kbc"; |
Laxman Dewangan | 699ed4b | 2013-01-11 19:03:03 +0530 | [diff] [blame] | 621 | status = "disabled"; |
| 622 | }; |
| 623 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 624 | pmc@7000e400 { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 625 | compatible = "nvidia,tegra30-pmc"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 626 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 627 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 628 | clock-names = "pclk", "clk32k_in"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 629 | }; |
| 630 | |
Thierry Reding | a9fe468 | 2014-07-18 12:13:28 +0200 | [diff] [blame] | 631 | mc: memory-controller@7000f000 { |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 632 | compatible = "nvidia,tegra30-mc"; |
Thierry Reding | a9fe468 | 2014-07-18 12:13:28 +0200 | [diff] [blame] | 633 | reg = <0x7000f000 0x400>; |
| 634 | clocks = <&tegra_car TEGRA30_CLK_MC>; |
| 635 | clock-names = "mc"; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 636 | |
Thierry Reding | a9fe468 | 2014-07-18 12:13:28 +0200 | [diff] [blame] | 637 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 638 | |
| 639 | #iommu-cells = <1>; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 640 | }; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 641 | |
Peter De Schrijver | 155dfc7 | 2014-06-12 18:36:38 +0300 | [diff] [blame] | 642 | fuse@7000f800 { |
| 643 | compatible = "nvidia,tegra30-efuse"; |
| 644 | reg = <0x7000f800 0x400>; |
| 645 | clocks = <&tegra_car TEGRA30_CLK_FUSE>; |
| 646 | clock-names = "fuse"; |
| 647 | resets = <&tegra_car 39>; |
| 648 | reset-names = "fuse"; |
| 649 | }; |
| 650 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 651 | ahub@70080000 { |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 652 | compatible = "nvidia,tegra30-ahub"; |
Stephen Warren | 5ff4888 | 2012-05-11 16:26:03 -0600 | [diff] [blame] | 653 | reg = <0x70080000 0x200 |
| 654 | 0x70080200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 655 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 656 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 657 | <&tegra_car TEGRA30_CLK_APBIF>; |
| 658 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 659 | resets = <&tegra_car 106>, /* d_audio */ |
| 660 | <&tegra_car 107>, /* apbif */ |
| 661 | <&tegra_car 30>, /* i2s0 */ |
| 662 | <&tegra_car 11>, /* i2s1 */ |
| 663 | <&tegra_car 18>, /* i2s2 */ |
| 664 | <&tegra_car 101>, /* i2s3 */ |
| 665 | <&tegra_car 102>, /* i2s4 */ |
| 666 | <&tegra_car 108>, /* dam0 */ |
| 667 | <&tegra_car 109>, /* dam1 */ |
| 668 | <&tegra_car 110>, /* dam2 */ |
| 669 | <&tegra_car 10>; /* spdif */ |
| 670 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 671 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 672 | "spdif"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 673 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 674 | <&apbdma 2>, <&apbdma 2>, |
| 675 | <&apbdma 3>, <&apbdma 3>, |
| 676 | <&apbdma 4>, <&apbdma 4>; |
| 677 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 678 | "rx3", "tx3"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 679 | ranges; |
| 680 | #address-cells = <1>; |
| 681 | #size-cells = <1>; |
| 682 | |
| 683 | tegra_i2s0: i2s@70080300 { |
| 684 | compatible = "nvidia,tegra30-i2s"; |
| 685 | reg = <0x70080300 0x100>; |
| 686 | nvidia,ahub-cif-ids = <4 4>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 687 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 688 | resets = <&tegra_car 30>; |
| 689 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 690 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 691 | }; |
| 692 | |
| 693 | tegra_i2s1: i2s@70080400 { |
| 694 | compatible = "nvidia,tegra30-i2s"; |
| 695 | reg = <0x70080400 0x100>; |
| 696 | nvidia,ahub-cif-ids = <5 5>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 697 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 698 | resets = <&tegra_car 11>; |
| 699 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 700 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 701 | }; |
| 702 | |
| 703 | tegra_i2s2: i2s@70080500 { |
| 704 | compatible = "nvidia,tegra30-i2s"; |
| 705 | reg = <0x70080500 0x100>; |
| 706 | nvidia,ahub-cif-ids = <6 6>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 707 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 708 | resets = <&tegra_car 18>; |
| 709 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 710 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 711 | }; |
| 712 | |
| 713 | tegra_i2s3: i2s@70080600 { |
| 714 | compatible = "nvidia,tegra30-i2s"; |
| 715 | reg = <0x70080600 0x100>; |
| 716 | nvidia,ahub-cif-ids = <7 7>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 717 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 718 | resets = <&tegra_car 101>; |
| 719 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 720 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 721 | }; |
| 722 | |
| 723 | tegra_i2s4: i2s@70080700 { |
| 724 | compatible = "nvidia,tegra30-i2s"; |
| 725 | reg = <0x70080700 0x100>; |
| 726 | nvidia,ahub-cif-ids = <8 8>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 727 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 728 | resets = <&tegra_car 102>; |
| 729 | reset-names = "i2s"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 730 | status = "disabled"; |
Stephen Warren | 9ee6a5c | 2012-03-27 12:40:53 -0600 | [diff] [blame] | 731 | }; |
| 732 | }; |
Hiroshi DOYU | 7868a9b | 2012-05-07 09:43:47 +0300 | [diff] [blame] | 733 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 734 | sdhci@78000000 { |
| 735 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 736 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 737 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 738 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 739 | resets = <&tegra_car 14>; |
| 740 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 741 | status = "disabled"; |
Hiroshi DOYU | 7868a9b | 2012-05-07 09:43:47 +0300 | [diff] [blame] | 742 | }; |
hdoyu@nvidia.com | ecf4374 | 2012-05-09 21:42:33 +0000 | [diff] [blame] | 743 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 744 | sdhci@78000200 { |
| 745 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 746 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 747 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 748 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 749 | resets = <&tegra_car 9>; |
| 750 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 751 | status = "disabled"; |
hdoyu@nvidia.com | ecf4374 | 2012-05-09 21:42:33 +0000 | [diff] [blame] | 752 | }; |
hdoyu@nvidia.com | 54174a3 | 2012-05-09 21:50:21 +0000 | [diff] [blame] | 753 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 754 | sdhci@78000400 { |
| 755 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 756 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 757 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 758 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 759 | resets = <&tegra_car 69>; |
| 760 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 761 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 762 | }; |
| 763 | |
| 764 | sdhci@78000600 { |
| 765 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 766 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 767 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | 05849c9 | 2013-05-22 19:45:34 +0300 | [diff] [blame] | 768 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 769 | resets = <&tegra_car 15>; |
| 770 | reset-names = "sdhci"; |
Roland Stigge | 223ef78 | 2012-06-11 21:09:45 +0200 | [diff] [blame] | 771 | status = "disabled"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 772 | }; |
| 773 | |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 774 | usb@7d000000 { |
| 775 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 776 | reg = <0x7d000000 0x4000>; |
| 777 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 778 | phy_type = "utmi"; |
| 779 | clocks = <&tegra_car TEGRA30_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 780 | resets = <&tegra_car 22>; |
| 781 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 782 | nvidia,needs-double-reset; |
| 783 | nvidia,phy = <&phy1>; |
| 784 | status = "disabled"; |
| 785 | }; |
| 786 | |
| 787 | phy1: usb-phy@7d000000 { |
| 788 | compatible = "nvidia,tegra30-usb-phy"; |
| 789 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 790 | phy_type = "utmi"; |
| 791 | clocks = <&tegra_car TEGRA30_CLK_USBD>, |
| 792 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 793 | <&tegra_car TEGRA30_CLK_USBD>; |
| 794 | clock-names = "reg", "pll_u", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 795 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 796 | reset-names = "usb", "utmi-pads"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 797 | nvidia,hssync-start-delay = <9>; |
| 798 | nvidia,idle-wait-delay = <17>; |
| 799 | nvidia,elastic-limit = <16>; |
| 800 | nvidia,term-range-adj = <6>; |
| 801 | nvidia,xcvr-setup = <51>; |
| 802 | nvidia.xcvr-setup-use-fuses; |
| 803 | nvidia,xcvr-lsfslew = <1>; |
| 804 | nvidia,xcvr-lsrslew = <1>; |
| 805 | nvidia,xcvr-hsslew = <32>; |
| 806 | nvidia,hssquelch-level = <2>; |
| 807 | nvidia,hsdiscon-level = <5>; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 808 | nvidia,has-utmi-pad-registers; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 809 | status = "disabled"; |
| 810 | }; |
| 811 | |
| 812 | usb@7d004000 { |
| 813 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 814 | reg = <0x7d004000 0x4000>; |
| 815 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 816 | phy_type = "utmi"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 817 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 818 | resets = <&tegra_car 58>; |
| 819 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 820 | nvidia,phy = <&phy2>; |
| 821 | status = "disabled"; |
| 822 | }; |
| 823 | |
| 824 | phy2: usb-phy@7d004000 { |
| 825 | compatible = "nvidia,tegra30-usb-phy"; |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 826 | reg = <0x7d004000 0x4000 0x7d000000 0x4000>; |
| 827 | phy_type = "utmi"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 828 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
| 829 | <&tegra_car TEGRA30_CLK_PLL_U>, |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 830 | <&tegra_car TEGRA30_CLK_USBD>; |
| 831 | clock-names = "reg", "pll_u", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 832 | resets = <&tegra_car 58>, <&tegra_car 22>; |
| 833 | reset-names = "usb", "utmi-pads"; |
Eric Brower | fd6441e | 2013-12-19 18:08:52 -0800 | [diff] [blame] | 834 | nvidia,hssync-start-delay = <9>; |
| 835 | nvidia,idle-wait-delay = <17>; |
| 836 | nvidia,elastic-limit = <16>; |
| 837 | nvidia,term-range-adj = <6>; |
| 838 | nvidia,xcvr-setup = <51>; |
| 839 | nvidia.xcvr-setup-use-fuses; |
| 840 | nvidia,xcvr-lsfslew = <2>; |
| 841 | nvidia,xcvr-lsrslew = <2>; |
| 842 | nvidia,xcvr-hsslew = <32>; |
| 843 | nvidia,hssquelch-level = <2>; |
| 844 | nvidia,hsdiscon-level = <5>; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 845 | status = "disabled"; |
| 846 | }; |
| 847 | |
| 848 | usb@7d008000 { |
| 849 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 850 | reg = <0x7d008000 0x4000>; |
| 851 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 852 | phy_type = "utmi"; |
| 853 | clocks = <&tegra_car TEGRA30_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 854 | resets = <&tegra_car 59>; |
| 855 | reset-names = "usb"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 856 | nvidia,phy = <&phy3>; |
| 857 | status = "disabled"; |
| 858 | }; |
| 859 | |
| 860 | phy3: usb-phy@7d008000 { |
| 861 | compatible = "nvidia,tegra30-usb-phy"; |
| 862 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 863 | phy_type = "utmi"; |
| 864 | clocks = <&tegra_car TEGRA30_CLK_USB3>, |
| 865 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 866 | <&tegra_car TEGRA30_CLK_USBD>; |
| 867 | clock-names = "reg", "pll_u", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 868 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 869 | reset-names = "usb", "utmi-pads"; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 870 | nvidia,hssync-start-delay = <0>; |
| 871 | nvidia,idle-wait-delay = <17>; |
| 872 | nvidia,elastic-limit = <16>; |
| 873 | nvidia,term-range-adj = <6>; |
| 874 | nvidia,xcvr-setup = <51>; |
| 875 | nvidia.xcvr-setup-use-fuses; |
| 876 | nvidia,xcvr-lsfslew = <2>; |
| 877 | nvidia,xcvr-lsrslew = <2>; |
| 878 | nvidia,xcvr-hsslew = <32>; |
| 879 | nvidia,hssquelch-level = <2>; |
| 880 | nvidia,hsdiscon-level = <5>; |
| 881 | status = "disabled"; |
| 882 | }; |
| 883 | |
Hiroshi Doyu | 7d19a34 | 2013-01-11 15:11:54 +0200 | [diff] [blame] | 884 | cpus { |
| 885 | #address-cells = <1>; |
| 886 | #size-cells = <0>; |
| 887 | |
| 888 | cpu@0 { |
| 889 | device_type = "cpu"; |
| 890 | compatible = "arm,cortex-a9"; |
| 891 | reg = <0>; |
| 892 | }; |
| 893 | |
| 894 | cpu@1 { |
| 895 | device_type = "cpu"; |
| 896 | compatible = "arm,cortex-a9"; |
| 897 | reg = <1>; |
| 898 | }; |
| 899 | |
| 900 | cpu@2 { |
| 901 | device_type = "cpu"; |
| 902 | compatible = "arm,cortex-a9"; |
| 903 | reg = <2>; |
| 904 | }; |
| 905 | |
| 906 | cpu@3 { |
| 907 | device_type = "cpu"; |
| 908 | compatible = "arm,cortex-a9"; |
| 909 | reg = <3>; |
| 910 | }; |
| 911 | }; |
| 912 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 913 | pmu { |
| 914 | compatible = "arm,cortex-a9-pmu"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 915 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| 916 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| 917 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 918 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
hdoyu@nvidia.com | 54174a3 | 2012-05-09 21:50:21 +0000 | [diff] [blame] | 919 | }; |
Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 920 | }; |