Daniel Drake | 66bb42f | 2007-11-19 16:20:12 +0000 | [diff] [blame] | 1 | /* ZD1211 USB-WLAN driver for Linux |
| 2 | * |
| 3 | * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> |
| 4 | * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | /* This file implements all the hardware specific functions for the ZD1211 |
| 22 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy |
| 23 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli |
| 24 | */ |
| 25 | |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/errno.h> |
| 28 | |
| 29 | #include "zd_def.h" |
| 30 | #include "zd_chip.h" |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 31 | #include "zd_mac.h" |
| 32 | #include "zd_rf.h" |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 33 | |
| 34 | void zd_chip_init(struct zd_chip *chip, |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 35 | struct ieee80211_hw *hw, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 36 | struct usb_interface *intf) |
| 37 | { |
| 38 | memset(chip, 0, sizeof(*chip)); |
| 39 | mutex_init(&chip->mutex); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 40 | zd_usb_init(&chip->usb, hw, intf); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 41 | zd_rf_init(&chip->rf); |
| 42 | } |
| 43 | |
| 44 | void zd_chip_clear(struct zd_chip *chip) |
| 45 | { |
Ulrich Kunitz | c48cf12 | 2006-08-12 18:00:17 +0100 | [diff] [blame] | 46 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 47 | zd_usb_clear(&chip->usb); |
| 48 | zd_rf_clear(&chip->rf); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 49 | mutex_destroy(&chip->mutex); |
Ulrich Kunitz | c48cf12 | 2006-08-12 18:00:17 +0100 | [diff] [blame] | 50 | ZD_MEMCLEAR(chip, sizeof(*chip)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 51 | } |
| 52 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 53 | static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 54 | { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 55 | u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 56 | return scnprintf(buffer, size, "%02x-%02x-%02x", |
| 57 | addr[0], addr[1], addr[2]); |
| 58 | } |
| 59 | |
| 60 | /* Prints an identifier line, which will support debugging. */ |
| 61 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) |
| 62 | { |
| 63 | int i = 0; |
| 64 | |
| 65 | i = scnprintf(buffer, size, "zd1211%s chip ", |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 66 | zd_chip_is_zd1211b(chip) ? "b" : ""); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 67 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); |
| 68 | i += scnprintf(buffer+i, size-i, " "); |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 69 | i += scnprint_mac_oui(chip, buffer+i, size-i); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 70 | i += scnprintf(buffer+i, size-i, " "); |
| 71 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); |
Daniel Drake | f2a81a1 | 2007-03-11 19:54:28 +0000 | [diff] [blame] | 72 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 73 | chip->patch_cck_gain ? 'g' : '-', |
| 74 | chip->patch_cr157 ? '7' : '-', |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 75 | chip->patch_6m_band_edge ? '6' : '-', |
Daniel Drake | f2a81a1 | 2007-03-11 19:54:28 +0000 | [diff] [blame] | 76 | chip->new_phy_layout ? 'N' : '-', |
| 77 | chip->al2230s_bit ? 'S' : '-'); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 78 | return i; |
| 79 | } |
| 80 | |
| 81 | static void print_id(struct zd_chip *chip) |
| 82 | { |
| 83 | char buffer[80]; |
| 84 | |
| 85 | scnprint_id(chip, buffer, sizeof(buffer)); |
| 86 | buffer[sizeof(buffer)-1] = 0; |
| 87 | dev_info(zd_chip_dev(chip), "%s\n", buffer); |
| 88 | } |
| 89 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 90 | static zd_addr_t inc_addr(zd_addr_t addr) |
| 91 | { |
| 92 | u16 a = (u16)addr; |
| 93 | /* Control registers use byte addressing, but everything else uses word |
| 94 | * addressing. */ |
| 95 | if ((a & 0xf000) == CR_START) |
| 96 | a += 2; |
| 97 | else |
| 98 | a += 1; |
| 99 | return (zd_addr_t)a; |
| 100 | } |
| 101 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 102 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
| 103 | * exceed USB_MAX_IOREAD32_COUNT. |
| 104 | */ |
| 105 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, |
| 106 | unsigned int count) |
| 107 | { |
| 108 | int r; |
| 109 | int i; |
Jesper Juhl | fa46081 | 2007-08-31 00:30:31 +0200 | [diff] [blame] | 110 | zd_addr_t *a16; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 111 | u16 *v16; |
| 112 | unsigned int count16; |
| 113 | |
| 114 | if (count > USB_MAX_IOREAD32_COUNT) |
| 115 | return -EINVAL; |
| 116 | |
| 117 | /* Allocate a single memory block for values and addresses. */ |
| 118 | count16 = 2*count; |
Daniel Drake | 4495685 | 2007-02-10 01:27:18 +0000 | [diff] [blame] | 119 | a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)), |
Ulrich Kunitz | 35c3404 | 2007-02-18 20:28:23 +0000 | [diff] [blame] | 120 | GFP_KERNEL); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 121 | if (!a16) { |
| 122 | dev_dbg_f(zd_chip_dev(chip), |
| 123 | "error ENOMEM in allocation of a16\n"); |
| 124 | r = -ENOMEM; |
| 125 | goto out; |
| 126 | } |
| 127 | v16 = (u16 *)(a16 + count16); |
| 128 | |
| 129 | for (i = 0; i < count; i++) { |
| 130 | int j = 2*i; |
| 131 | /* We read the high word always first. */ |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 132 | a16[j] = inc_addr(addr[i]); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 133 | a16[j+1] = addr[i]; |
| 134 | } |
| 135 | |
| 136 | r = zd_ioread16v_locked(chip, v16, a16, count16); |
| 137 | if (r) { |
| 138 | dev_dbg_f(zd_chip_dev(chip), |
| 139 | "error: zd_ioread16v_locked. Error number %d\n", r); |
| 140 | goto out; |
| 141 | } |
| 142 | |
| 143 | for (i = 0; i < count; i++) { |
| 144 | int j = 2*i; |
| 145 | values[i] = (v16[j] << 16) | v16[j+1]; |
| 146 | } |
| 147 | |
| 148 | out: |
| 149 | kfree((void *)a16); |
| 150 | return r; |
| 151 | } |
| 152 | |
| 153 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, |
| 154 | unsigned int count) |
| 155 | { |
| 156 | int i, j, r; |
| 157 | struct zd_ioreq16 *ioreqs16; |
| 158 | unsigned int count16; |
| 159 | |
| 160 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 161 | |
| 162 | if (count == 0) |
| 163 | return 0; |
| 164 | if (count > USB_MAX_IOWRITE32_COUNT) |
| 165 | return -EINVAL; |
| 166 | |
| 167 | /* Allocate a single memory block for values and addresses. */ |
| 168 | count16 = 2*count; |
Ulrich Kunitz | 35c3404 | 2007-02-18 20:28:23 +0000 | [diff] [blame] | 169 | ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 170 | if (!ioreqs16) { |
| 171 | r = -ENOMEM; |
| 172 | dev_dbg_f(zd_chip_dev(chip), |
| 173 | "error %d in ioreqs16 allocation\n", r); |
| 174 | goto out; |
| 175 | } |
| 176 | |
| 177 | for (i = 0; i < count; i++) { |
| 178 | j = 2*i; |
| 179 | /* We write the high word always first. */ |
| 180 | ioreqs16[j].value = ioreqs[i].value >> 16; |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 181 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 182 | ioreqs16[j+1].value = ioreqs[i].value; |
| 183 | ioreqs16[j+1].addr = ioreqs[i].addr; |
| 184 | } |
| 185 | |
| 186 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); |
| 187 | #ifdef DEBUG |
| 188 | if (r) { |
| 189 | dev_dbg_f(zd_chip_dev(chip), |
| 190 | "error %d in zd_usb_write16v\n", r); |
| 191 | } |
| 192 | #endif /* DEBUG */ |
| 193 | out: |
| 194 | kfree(ioreqs16); |
| 195 | return r; |
| 196 | } |
| 197 | |
| 198 | int zd_iowrite16a_locked(struct zd_chip *chip, |
| 199 | const struct zd_ioreq16 *ioreqs, unsigned int count) |
| 200 | { |
| 201 | int r; |
| 202 | unsigned int i, j, t, max; |
| 203 | |
| 204 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 205 | for (i = 0; i < count; i += j + t) { |
| 206 | t = 0; |
| 207 | max = count-i; |
| 208 | if (max > USB_MAX_IOWRITE16_COUNT) |
| 209 | max = USB_MAX_IOWRITE16_COUNT; |
| 210 | for (j = 0; j < max; j++) { |
| 211 | if (!ioreqs[i+j].addr) { |
| 212 | t = 1; |
| 213 | break; |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); |
| 218 | if (r) { |
| 219 | dev_dbg_f(zd_chip_dev(chip), |
| 220 | "error zd_usb_iowrite16v. Error number %d\n", |
| 221 | r); |
| 222 | return r; |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | /* Writes a variable number of 32 bit registers. The functions will split |
| 230 | * that in several USB requests. A split can be forced by inserting an IO |
| 231 | * request with an zero address field. |
| 232 | */ |
| 233 | int zd_iowrite32a_locked(struct zd_chip *chip, |
| 234 | const struct zd_ioreq32 *ioreqs, unsigned int count) |
| 235 | { |
| 236 | int r; |
| 237 | unsigned int i, j, t, max; |
| 238 | |
| 239 | for (i = 0; i < count; i += j + t) { |
| 240 | t = 0; |
| 241 | max = count-i; |
| 242 | if (max > USB_MAX_IOWRITE32_COUNT) |
| 243 | max = USB_MAX_IOWRITE32_COUNT; |
| 244 | for (j = 0; j < max; j++) { |
| 245 | if (!ioreqs[i+j].addr) { |
| 246 | t = 1; |
| 247 | break; |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); |
| 252 | if (r) { |
| 253 | dev_dbg_f(zd_chip_dev(chip), |
| 254 | "error _zd_iowrite32v_locked." |
| 255 | " Error number %d\n", r); |
| 256 | return r; |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | return 0; |
| 261 | } |
| 262 | |
| 263 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) |
| 264 | { |
| 265 | int r; |
| 266 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 267 | mutex_lock(&chip->mutex); |
| 268 | r = zd_ioread16_locked(chip, value, addr); |
| 269 | mutex_unlock(&chip->mutex); |
| 270 | return r; |
| 271 | } |
| 272 | |
| 273 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) |
| 274 | { |
| 275 | int r; |
| 276 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 277 | mutex_lock(&chip->mutex); |
| 278 | r = zd_ioread32_locked(chip, value, addr); |
| 279 | mutex_unlock(&chip->mutex); |
| 280 | return r; |
| 281 | } |
| 282 | |
| 283 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) |
| 284 | { |
| 285 | int r; |
| 286 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 287 | mutex_lock(&chip->mutex); |
| 288 | r = zd_iowrite16_locked(chip, value, addr); |
| 289 | mutex_unlock(&chip->mutex); |
| 290 | return r; |
| 291 | } |
| 292 | |
| 293 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) |
| 294 | { |
| 295 | int r; |
| 296 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 297 | mutex_lock(&chip->mutex); |
| 298 | r = zd_iowrite32_locked(chip, value, addr); |
| 299 | mutex_unlock(&chip->mutex); |
| 300 | return r; |
| 301 | } |
| 302 | |
| 303 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, |
| 304 | u32 *values, unsigned int count) |
| 305 | { |
| 306 | int r; |
| 307 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 308 | mutex_lock(&chip->mutex); |
| 309 | r = zd_ioread32v_locked(chip, values, addresses, count); |
| 310 | mutex_unlock(&chip->mutex); |
| 311 | return r; |
| 312 | } |
| 313 | |
| 314 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, |
| 315 | unsigned int count) |
| 316 | { |
| 317 | int r; |
| 318 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 319 | mutex_lock(&chip->mutex); |
| 320 | r = zd_iowrite32a_locked(chip, ioreqs, count); |
| 321 | mutex_unlock(&chip->mutex); |
| 322 | return r; |
| 323 | } |
| 324 | |
| 325 | static int read_pod(struct zd_chip *chip, u8 *rf_type) |
| 326 | { |
| 327 | int r; |
| 328 | u32 value; |
| 329 | |
| 330 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 331 | r = zd_ioread32_locked(chip, &value, E2P_POD); |
| 332 | if (r) |
| 333 | goto error; |
| 334 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); |
| 335 | |
| 336 | /* FIXME: AL2230 handling (Bit 7 in POD) */ |
| 337 | *rf_type = value & 0x0f; |
| 338 | chip->pa_type = (value >> 16) & 0x0f; |
| 339 | chip->patch_cck_gain = (value >> 8) & 0x1; |
| 340 | chip->patch_cr157 = (value >> 13) & 0x1; |
| 341 | chip->patch_6m_band_edge = (value >> 21) & 0x1; |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 342 | chip->new_phy_layout = (value >> 31) & 0x1; |
Daniel Drake | ae6ead4 | 2007-03-11 19:54:11 +0000 | [diff] [blame] | 343 | chip->al2230s_bit = (value >> 7) & 0x1; |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 344 | chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; |
| 345 | chip->supports_tx_led = 1; |
| 346 | if (value & (1 << 24)) { /* LED scenario */ |
| 347 | if (value & (1 << 29)) |
| 348 | chip->supports_tx_led = 0; |
| 349 | } |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 350 | |
| 351 | dev_dbg_f(zd_chip_dev(chip), |
| 352 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 353 | "patch 6M %d new PHY %d link LED%d tx led %d\n", |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 354 | zd_rf_name(*rf_type), *rf_type, |
| 355 | chip->pa_type, chip->patch_cck_gain, |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 356 | chip->patch_cr157, chip->patch_6m_band_edge, |
| 357 | chip->new_phy_layout, |
| 358 | chip->link_led == LED1 ? 1 : 2, |
| 359 | chip->supports_tx_led); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 360 | return 0; |
| 361 | error: |
| 362 | *rf_type = 0; |
| 363 | chip->pa_type = 0; |
| 364 | chip->patch_cck_gain = 0; |
| 365 | chip->patch_cr157 = 0; |
| 366 | chip->patch_6m_band_edge = 0; |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 367 | chip->new_phy_layout = 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 368 | return r; |
| 369 | } |
| 370 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 371 | /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and |
| 372 | * CR_MAC_ADDR_P2 must be overwritten |
| 373 | */ |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 374 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) |
| 375 | { |
| 376 | int r; |
| 377 | struct zd_ioreq32 reqs[2] = { |
| 378 | [0] = { .addr = CR_MAC_ADDR_P1 }, |
| 379 | [1] = { .addr = CR_MAC_ADDR_P2 }, |
| 380 | }; |
Joe Perches | 0795af5 | 2007-10-03 17:59:30 -0700 | [diff] [blame] | 381 | DECLARE_MAC_BUF(mac); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 382 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 383 | if (mac_addr) { |
| 384 | reqs[0].value = (mac_addr[3] << 24) |
| 385 | | (mac_addr[2] << 16) |
| 386 | | (mac_addr[1] << 8) |
| 387 | | mac_addr[0]; |
| 388 | reqs[1].value = (mac_addr[5] << 8) |
| 389 | | mac_addr[4]; |
| 390 | dev_dbg_f(zd_chip_dev(chip), |
| 391 | "mac addr %s\n", print_mac(mac, mac_addr)); |
| 392 | } else { |
| 393 | dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n"); |
| 394 | } |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 395 | |
| 396 | mutex_lock(&chip->mutex); |
| 397 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 398 | mutex_unlock(&chip->mutex); |
| 399 | return r; |
| 400 | } |
| 401 | |
| 402 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) |
| 403 | { |
| 404 | int r; |
| 405 | u32 value; |
| 406 | |
| 407 | mutex_lock(&chip->mutex); |
| 408 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); |
| 409 | mutex_unlock(&chip->mutex); |
| 410 | if (r) |
| 411 | return r; |
| 412 | |
| 413 | *regdomain = value >> 16; |
| 414 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); |
| 415 | |
| 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, |
| 420 | zd_addr_t e2p_addr, u32 guard) |
| 421 | { |
| 422 | int r; |
| 423 | int i; |
| 424 | u32 v; |
| 425 | |
| 426 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 427 | for (i = 0;;) { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 428 | r = zd_ioread32_locked(chip, &v, |
| 429 | (zd_addr_t)((u16)e2p_addr+i/2)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 430 | if (r) |
| 431 | return r; |
| 432 | v -= guard; |
| 433 | if (i+4 < count) { |
| 434 | values[i++] = v; |
| 435 | values[i++] = v >> 8; |
| 436 | values[i++] = v >> 16; |
| 437 | values[i++] = v >> 24; |
| 438 | continue; |
| 439 | } |
| 440 | for (;i < count; i++) |
| 441 | values[i] = v >> (8*(i%3)); |
| 442 | return 0; |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | static int read_pwr_cal_values(struct zd_chip *chip) |
| 447 | { |
| 448 | return read_values(chip, chip->pwr_cal_values, |
| 449 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, |
| 450 | 0); |
| 451 | } |
| 452 | |
| 453 | static int read_pwr_int_values(struct zd_chip *chip) |
| 454 | { |
| 455 | return read_values(chip, chip->pwr_int_values, |
| 456 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, |
| 457 | E2P_PWR_INT_GUARD); |
| 458 | } |
| 459 | |
| 460 | static int read_ofdm_cal_values(struct zd_chip *chip) |
| 461 | { |
| 462 | int r; |
| 463 | int i; |
| 464 | static const zd_addr_t addresses[] = { |
| 465 | E2P_36M_CAL_VALUE1, |
| 466 | E2P_48M_CAL_VALUE1, |
| 467 | E2P_54M_CAL_VALUE1, |
| 468 | }; |
| 469 | |
| 470 | for (i = 0; i < 3; i++) { |
| 471 | r = read_values(chip, chip->ofdm_cal_values[i], |
| 472 | E2P_CHANNEL_COUNT, addresses[i], 0); |
| 473 | if (r) |
| 474 | return r; |
| 475 | } |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static int read_cal_int_tables(struct zd_chip *chip) |
| 480 | { |
| 481 | int r; |
| 482 | |
| 483 | r = read_pwr_cal_values(chip); |
| 484 | if (r) |
| 485 | return r; |
| 486 | r = read_pwr_int_values(chip); |
| 487 | if (r) |
| 488 | return r; |
| 489 | r = read_ofdm_cal_values(chip); |
| 490 | if (r) |
| 491 | return r; |
| 492 | return 0; |
| 493 | } |
| 494 | |
| 495 | /* phy means physical registers */ |
| 496 | int zd_chip_lock_phy_regs(struct zd_chip *chip) |
| 497 | { |
| 498 | int r; |
| 499 | u32 tmp; |
| 500 | |
| 501 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 502 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); |
| 503 | if (r) { |
| 504 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); |
| 505 | return r; |
| 506 | } |
| 507 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 508 | tmp &= ~UNLOCK_PHY_REGS; |
| 509 | |
| 510 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); |
| 511 | if (r) |
| 512 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); |
| 513 | return r; |
| 514 | } |
| 515 | |
| 516 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) |
| 517 | { |
| 518 | int r; |
| 519 | u32 tmp; |
| 520 | |
| 521 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 522 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); |
| 523 | if (r) { |
| 524 | dev_err(zd_chip_dev(chip), |
| 525 | "error ioread32(CR_REG1): %d\n", r); |
| 526 | return r; |
| 527 | } |
| 528 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 529 | tmp |= UNLOCK_PHY_REGS; |
| 530 | |
| 531 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); |
| 532 | if (r) |
| 533 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); |
| 534 | return r; |
| 535 | } |
| 536 | |
Daniel Drake | 92b3e2e | 2007-04-03 23:17:37 +0100 | [diff] [blame] | 537 | /* CR157 can be optionally patched by the EEPROM for original ZD1211 */ |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 538 | static int patch_cr157(struct zd_chip *chip) |
| 539 | { |
| 540 | int r; |
Daniel Drake | 92b3e2e | 2007-04-03 23:17:37 +0100 | [diff] [blame] | 541 | u16 value; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 542 | |
| 543 | if (!chip->patch_cr157) |
| 544 | return 0; |
| 545 | |
Daniel Drake | 92b3e2e | 2007-04-03 23:17:37 +0100 | [diff] [blame] | 546 | r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 547 | if (r) |
| 548 | return r; |
| 549 | |
| 550 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); |
| 551 | return zd_iowrite32_locked(chip, value >> 8, CR157); |
| 552 | } |
| 553 | |
| 554 | /* |
| 555 | * 6M band edge can be optionally overwritten for certain RF's |
| 556 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge |
| 557 | * bit (for AL2230, AL2230S) |
| 558 | */ |
Daniel Drake | 72018b22 | 2007-04-07 16:00:15 +0100 | [diff] [blame] | 559 | static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) |
| 560 | { |
| 561 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 562 | if (!chip->patch_6m_band_edge) |
| 563 | return 0; |
| 564 | |
| 565 | return zd_rf_patch_6m_band_edge(&chip->rf, channel); |
| 566 | } |
| 567 | |
| 568 | /* Generic implementation of 6M band edge patching, used by most RFs via |
| 569 | * zd_rf_generic_patch_6m() */ |
| 570 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 571 | { |
| 572 | struct zd_ioreq16 ioreqs[] = { |
| 573 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, |
| 574 | { CR47, 0x1e }, |
| 575 | }; |
| 576 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 577 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ |
| 578 | if (channel == 1 || channel == 11) |
| 579 | ioreqs[0].value = 0x12; |
| 580 | |
| 581 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); |
| 582 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 583 | } |
| 584 | |
| 585 | static int zd1211_hw_reset_phy(struct zd_chip *chip) |
| 586 | { |
| 587 | static const struct zd_ioreq16 ioreqs[] = { |
| 588 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, |
| 589 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, |
| 590 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, |
| 591 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, |
| 592 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, |
| 593 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, |
| 594 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, |
| 595 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, |
| 596 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, |
| 597 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
| 598 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, |
| 599 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, |
| 600 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, |
| 601 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, |
| 602 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, |
| 603 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, |
| 604 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, |
| 605 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, |
| 606 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, |
| 607 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, |
| 608 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, |
| 609 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, |
| 610 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, |
| 611 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, |
| 612 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, |
| 613 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, |
| 614 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, |
| 615 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, |
| 616 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, |
| 617 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, |
| 618 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, |
| 619 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, |
| 620 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, |
| 621 | { }, |
| 622 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, |
| 623 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, |
| 624 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, |
| 625 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, |
| 626 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, |
| 627 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, |
| 628 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, |
| 629 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, |
| 630 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, |
| 631 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, |
| 632 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, |
| 633 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, |
| 634 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, |
| 635 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, |
Daniel Drake | dc536a7 | 2007-04-03 23:17:10 +0100 | [diff] [blame] | 636 | { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 }, |
| 637 | { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C }, |
| 638 | { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 }, |
| 639 | { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 }, |
| 640 | { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c }, |
| 641 | { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 }, |
| 642 | { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe }, |
| 643 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, |
| 644 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, |
| 645 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, |
| 646 | { CR170, 0xba }, { CR171, 0xba }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 647 | /* Note: CR204 must lead the CR203 */ |
| 648 | { CR204, 0x7d }, |
| 649 | { }, |
| 650 | { CR203, 0x30 }, |
| 651 | }; |
| 652 | |
| 653 | int r, t; |
| 654 | |
| 655 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 656 | |
| 657 | r = zd_chip_lock_phy_regs(chip); |
| 658 | if (r) |
| 659 | goto out; |
| 660 | |
| 661 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 662 | if (r) |
| 663 | goto unlock; |
| 664 | |
| 665 | r = patch_cr157(chip); |
| 666 | unlock: |
| 667 | t = zd_chip_unlock_phy_regs(chip); |
| 668 | if (t && !r) |
| 669 | r = t; |
| 670 | out: |
| 671 | return r; |
| 672 | } |
| 673 | |
| 674 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) |
| 675 | { |
| 676 | static const struct zd_ioreq16 ioreqs[] = { |
| 677 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, |
| 678 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, |
| 679 | { CR10, 0x81 }, |
| 680 | /* power control { { CR11, 1 << 6 }, */ |
| 681 | { CR11, 0x00 }, |
| 682 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, |
| 683 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, |
| 684 | { CR18, 0x0a }, { CR19, 0x48 }, |
| 685 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ |
| 686 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, |
| 687 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, |
| 688 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, |
Daniel Drake | fe7215c | 2006-08-12 17:59:12 +0100 | [diff] [blame] | 689 | { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 690 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
| 691 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, |
| 692 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, |
| 693 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, |
| 694 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, |
| 695 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, |
| 696 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, |
| 697 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, |
| 698 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, |
| 699 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, |
| 700 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, |
| 701 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, |
| 702 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, |
| 703 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, |
| 704 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, |
| 705 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, |
| 706 | { CR94, 0x01 }, |
| 707 | { CR95, 0x20 }, /* ZD1211B */ |
| 708 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, |
| 709 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, |
| 710 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, |
| 711 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, |
| 712 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, |
| 713 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, |
| 714 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, |
| 715 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, |
| 716 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, |
| 717 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, |
| 718 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, |
| 719 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, |
| 720 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, |
| 721 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, |
| 722 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ |
| 723 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ |
| 724 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, |
| 725 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, |
| 726 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, |
| 727 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, |
| 728 | { CR170, 0xba }, { CR171, 0xba }, |
| 729 | /* Note: CR204 must lead the CR203 */ |
| 730 | { CR204, 0x7d }, |
| 731 | {}, |
| 732 | { CR203, 0x30 }, |
| 733 | }; |
| 734 | |
| 735 | int r, t; |
| 736 | |
| 737 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 738 | |
| 739 | r = zd_chip_lock_phy_regs(chip); |
| 740 | if (r) |
| 741 | goto out; |
| 742 | |
| 743 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 744 | t = zd_chip_unlock_phy_regs(chip); |
| 745 | if (t && !r) |
| 746 | r = t; |
| 747 | out: |
| 748 | return r; |
| 749 | } |
| 750 | |
| 751 | static int hw_reset_phy(struct zd_chip *chip) |
| 752 | { |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 753 | return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) : |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 754 | zd1211_hw_reset_phy(chip); |
| 755 | } |
| 756 | |
| 757 | static int zd1211_hw_init_hmac(struct zd_chip *chip) |
| 758 | { |
| 759 | static const struct zd_ioreq32 ioreqs[] = { |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 760 | { CR_ZD1211_RETRY_MAX, 0x2 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 761 | { CR_RX_THRESHOLD, 0x000c0640 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 762 | }; |
| 763 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 764 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 765 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 766 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) |
| 770 | { |
| 771 | static const struct zd_ioreq32 ioreqs[] = { |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 772 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, |
Javier Cardona | e51c683 | 2008-02-08 18:41:17 -0800 | [diff] [blame] | 773 | { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f }, |
| 774 | { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f }, |
| 775 | { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f }, |
| 776 | { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 777 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, |
| 778 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, |
| 779 | { CR_ZD1211B_TXOP, 0x01800824 }, |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 780 | { CR_RX_THRESHOLD, 0x000c0eff, }, |
| 781 | }; |
| 782 | |
| 783 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 784 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 785 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 786 | } |
| 787 | |
| 788 | static int hw_init_hmac(struct zd_chip *chip) |
| 789 | { |
| 790 | int r; |
| 791 | static const struct zd_ioreq32 ioreqs[] = { |
| 792 | { CR_ACK_TIMEOUT_EXT, 0x20 }, |
| 793 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 794 | { CR_SNIFFER_ON, 0 }, |
Ulrich Kunitz | fde627b | 2006-08-01 23:43:35 +0200 | [diff] [blame] | 795 | { CR_RX_FILTER, STA_RX_FILTER }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 796 | { CR_GROUP_HASH_P1, 0x00 }, |
| 797 | { CR_GROUP_HASH_P2, 0x80000000 }, |
| 798 | { CR_REG1, 0xa4 }, |
| 799 | { CR_ADDA_PWR_DWN, 0x7f }, |
| 800 | { CR_BCN_PLCP_CFG, 0x00f00401 }, |
| 801 | { CR_PHY_DELAY, 0x00 }, |
| 802 | { CR_ACK_TIMEOUT_EXT, 0x80 }, |
| 803 | { CR_ADDA_PWR_DWN, 0x00 }, |
| 804 | { CR_ACK_TIME_80211, 0x100 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 805 | { CR_RX_PE_DELAY, 0x70 }, |
| 806 | { CR_PS_CTRL, 0x10000000 }, |
| 807 | { CR_RTS_CTS_RATE, 0x02030203 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 808 | { CR_AFTER_PNP, 0x1 }, |
| 809 | { CR_WEP_PROTECT, 0x114 }, |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 810 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, |
Luis Carlos Cobo | 72e77a8 | 2008-03-03 12:32:15 -0800 | [diff] [blame] | 811 | { CR_CAM_MODE, MODE_AP_WDS}, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 812 | }; |
| 813 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 814 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 815 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 816 | if (r) |
| 817 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 818 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 819 | return zd_chip_is_zd1211b(chip) ? |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 820 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); |
| 821 | } |
| 822 | |
| 823 | struct aw_pt_bi { |
| 824 | u32 atim_wnd_period; |
| 825 | u32 pre_tbtt; |
| 826 | u32 beacon_interval; |
| 827 | }; |
| 828 | |
| 829 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) |
| 830 | { |
| 831 | int r; |
| 832 | static const zd_addr_t aw_pt_bi_addr[] = |
| 833 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; |
| 834 | u32 values[3]; |
| 835 | |
| 836 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, |
| 837 | ARRAY_SIZE(aw_pt_bi_addr)); |
| 838 | if (r) { |
| 839 | memset(s, 0, sizeof(*s)); |
| 840 | return r; |
| 841 | } |
| 842 | |
| 843 | s->atim_wnd_period = values[0]; |
| 844 | s->pre_tbtt = values[1]; |
| 845 | s->beacon_interval = values[2]; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 846 | return 0; |
| 847 | } |
| 848 | |
| 849 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) |
| 850 | { |
| 851 | struct zd_ioreq32 reqs[3]; |
| 852 | |
| 853 | if (s->beacon_interval <= 5) |
| 854 | s->beacon_interval = 5; |
| 855 | if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval) |
| 856 | s->pre_tbtt = s->beacon_interval - 1; |
| 857 | if (s->atim_wnd_period >= s->pre_tbtt) |
| 858 | s->atim_wnd_period = s->pre_tbtt - 1; |
| 859 | |
| 860 | reqs[0].addr = CR_ATIM_WND_PERIOD; |
| 861 | reqs[0].value = s->atim_wnd_period; |
| 862 | reqs[1].addr = CR_PRE_TBTT; |
| 863 | reqs[1].value = s->pre_tbtt; |
| 864 | reqs[2].addr = CR_BCN_INTERVAL; |
| 865 | reqs[2].value = s->beacon_interval; |
| 866 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 867 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); |
| 868 | } |
| 869 | |
| 870 | |
| 871 | static int set_beacon_interval(struct zd_chip *chip, u32 interval) |
| 872 | { |
| 873 | int r; |
| 874 | struct aw_pt_bi s; |
| 875 | |
| 876 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 877 | r = get_aw_pt_bi(chip, &s); |
| 878 | if (r) |
| 879 | return r; |
| 880 | s.beacon_interval = interval; |
| 881 | return set_aw_pt_bi(chip, &s); |
| 882 | } |
| 883 | |
| 884 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval) |
| 885 | { |
| 886 | int r; |
| 887 | |
| 888 | mutex_lock(&chip->mutex); |
| 889 | r = set_beacon_interval(chip, interval); |
| 890 | mutex_unlock(&chip->mutex); |
| 891 | return r; |
| 892 | } |
| 893 | |
| 894 | static int hw_init(struct zd_chip *chip) |
| 895 | { |
| 896 | int r; |
| 897 | |
| 898 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 899 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 900 | r = hw_reset_phy(chip); |
| 901 | if (r) |
| 902 | return r; |
| 903 | |
| 904 | r = hw_init_hmac(chip); |
| 905 | if (r) |
| 906 | return r; |
Daniel Drake | 98227a9 | 2006-08-12 17:59:22 +0100 | [diff] [blame] | 907 | |
Daniel Drake | 98227a9 | 2006-08-12 17:59:22 +0100 | [diff] [blame] | 908 | return set_beacon_interval(chip, 100); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 909 | } |
| 910 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 911 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) |
| 912 | { |
| 913 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); |
| 914 | } |
| 915 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 916 | #ifdef DEBUG |
| 917 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, |
| 918 | const char *addr_string) |
| 919 | { |
| 920 | int r; |
| 921 | u32 value; |
| 922 | |
| 923 | r = zd_ioread32_locked(chip, &value, addr); |
| 924 | if (r) { |
| 925 | dev_dbg_f(zd_chip_dev(chip), |
| 926 | "error reading %s. Error number %d\n", addr_string, r); |
| 927 | return r; |
| 928 | } |
| 929 | |
| 930 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", |
| 931 | addr_string, (unsigned int)value); |
| 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static int test_init(struct zd_chip *chip) |
| 936 | { |
| 937 | int r; |
| 938 | |
| 939 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); |
| 940 | if (r) |
| 941 | return r; |
| 942 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); |
| 943 | if (r) |
| 944 | return r; |
| 945 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); |
| 946 | } |
| 947 | |
| 948 | static void dump_fw_registers(struct zd_chip *chip) |
| 949 | { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 950 | const zd_addr_t addr[4] = { |
| 951 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), |
| 952 | fw_reg_addr(chip, FW_REG_USB_SPEED), |
| 953 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), |
| 954 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 955 | }; |
| 956 | |
| 957 | int r; |
| 958 | u16 values[4]; |
| 959 | |
| 960 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, |
| 961 | ARRAY_SIZE(addr)); |
| 962 | if (r) { |
| 963 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", |
| 964 | r); |
| 965 | return; |
| 966 | } |
| 967 | |
| 968 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); |
| 969 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); |
| 970 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); |
| 971 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); |
| 972 | } |
| 973 | #endif /* DEBUG */ |
| 974 | |
| 975 | static int print_fw_version(struct zd_chip *chip) |
| 976 | { |
| 977 | int r; |
| 978 | u16 version; |
| 979 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 980 | r = zd_ioread16_locked(chip, &version, |
| 981 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 982 | if (r) |
| 983 | return r; |
| 984 | |
| 985 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); |
| 986 | return 0; |
| 987 | } |
| 988 | |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 989 | static int set_mandatory_rates(struct zd_chip *chip, int gmode) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 990 | { |
| 991 | u32 rates; |
| 992 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 993 | /* This sets the mandatory rates, which only depend from the standard |
| 994 | * that the device is supporting. Until further notice we should try |
| 995 | * to support 802.11g also for full speed USB. |
| 996 | */ |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 997 | if (!gmode) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 998 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 999 | else |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1000 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| |
| 1001 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1002 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1003 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); |
| 1004 | } |
| 1005 | |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1006 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1007 | int preamble) |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1008 | { |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1009 | u32 value = 0; |
| 1010 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1011 | dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble); |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1012 | value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; |
| 1013 | value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; |
| 1014 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1015 | /* We always send 11M RTS/self-CTS messages, like the vendor driver. */ |
| 1016 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE; |
| 1017 | value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1018 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE; |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1019 | value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; |
| 1020 | |
| 1021 | return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); |
| 1022 | } |
| 1023 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1024 | int zd_chip_enable_hwint(struct zd_chip *chip) |
| 1025 | { |
| 1026 | int r; |
| 1027 | |
| 1028 | mutex_lock(&chip->mutex); |
| 1029 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); |
| 1030 | mutex_unlock(&chip->mutex); |
| 1031 | return r; |
| 1032 | } |
| 1033 | |
| 1034 | static int disable_hwint(struct zd_chip *chip) |
| 1035 | { |
| 1036 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); |
| 1037 | } |
| 1038 | |
| 1039 | int zd_chip_disable_hwint(struct zd_chip *chip) |
| 1040 | { |
| 1041 | int r; |
| 1042 | |
| 1043 | mutex_lock(&chip->mutex); |
| 1044 | r = disable_hwint(chip); |
| 1045 | mutex_unlock(&chip->mutex); |
| 1046 | return r; |
| 1047 | } |
| 1048 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1049 | static int read_fw_regs_offset(struct zd_chip *chip) |
| 1050 | { |
| 1051 | int r; |
| 1052 | |
| 1053 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1054 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, |
| 1055 | FWRAW_REGS_ADDR); |
| 1056 | if (r) |
| 1057 | return r; |
| 1058 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", |
| 1059 | (u16)chip->fw_regs_base); |
| 1060 | |
| 1061 | return 0; |
| 1062 | } |
| 1063 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 1064 | /* Read mac address using pre-firmware interface */ |
| 1065 | int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr) |
| 1066 | { |
| 1067 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 1068 | return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr, |
| 1069 | ETH_ALEN); |
| 1070 | } |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1071 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 1072 | int zd_chip_init_hw(struct zd_chip *chip) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1073 | { |
| 1074 | int r; |
| 1075 | u8 rf_type; |
| 1076 | |
| 1077 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 1078 | |
| 1079 | mutex_lock(&chip->mutex); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1080 | |
| 1081 | #ifdef DEBUG |
| 1082 | r = test_init(chip); |
| 1083 | if (r) |
| 1084 | goto out; |
| 1085 | #endif |
| 1086 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); |
| 1087 | if (r) |
| 1088 | goto out; |
| 1089 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1090 | r = read_fw_regs_offset(chip); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1091 | if (r) |
| 1092 | goto out; |
| 1093 | |
| 1094 | /* GPI is always disabled, also in the other driver. |
| 1095 | */ |
| 1096 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); |
| 1097 | if (r) |
| 1098 | goto out; |
| 1099 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); |
| 1100 | if (r) |
| 1101 | goto out; |
| 1102 | /* Currently we support IEEE 802.11g for full and high speed USB. |
| 1103 | * It might be discussed, whether we should suppport pure b mode for |
| 1104 | * full speed USB. |
| 1105 | */ |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1106 | r = set_mandatory_rates(chip, 1); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1107 | if (r) |
| 1108 | goto out; |
| 1109 | /* Disabling interrupts is certainly a smart thing here. |
| 1110 | */ |
| 1111 | r = disable_hwint(chip); |
| 1112 | if (r) |
| 1113 | goto out; |
| 1114 | r = read_pod(chip, &rf_type); |
| 1115 | if (r) |
| 1116 | goto out; |
| 1117 | r = hw_init(chip); |
| 1118 | if (r) |
| 1119 | goto out; |
| 1120 | r = zd_rf_init_hw(&chip->rf, rf_type); |
| 1121 | if (r) |
| 1122 | goto out; |
| 1123 | |
| 1124 | r = print_fw_version(chip); |
| 1125 | if (r) |
| 1126 | goto out; |
| 1127 | |
| 1128 | #ifdef DEBUG |
| 1129 | dump_fw_registers(chip); |
| 1130 | r = test_init(chip); |
| 1131 | if (r) |
| 1132 | goto out; |
| 1133 | #endif /* DEBUG */ |
| 1134 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1135 | r = read_cal_int_tables(chip); |
| 1136 | if (r) |
| 1137 | goto out; |
| 1138 | |
| 1139 | print_id(chip); |
| 1140 | out: |
| 1141 | mutex_unlock(&chip->mutex); |
| 1142 | return r; |
| 1143 | } |
| 1144 | |
| 1145 | static int update_pwr_int(struct zd_chip *chip, u8 channel) |
| 1146 | { |
| 1147 | u8 value = chip->pwr_int_values[channel - 1]; |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1148 | return zd_iowrite16_locked(chip, value, CR31); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1149 | } |
| 1150 | |
| 1151 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) |
| 1152 | { |
| 1153 | u8 value = chip->pwr_cal_values[channel-1]; |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1154 | return zd_iowrite16_locked(chip, value, CR68); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1155 | } |
| 1156 | |
| 1157 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) |
| 1158 | { |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1159 | struct zd_ioreq16 ioreqs[3]; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1160 | |
| 1161 | ioreqs[0].addr = CR67; |
| 1162 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; |
| 1163 | ioreqs[1].addr = CR66; |
| 1164 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; |
| 1165 | ioreqs[2].addr = CR65; |
| 1166 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; |
| 1167 | |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1168 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1169 | } |
| 1170 | |
| 1171 | static int update_channel_integration_and_calibration(struct zd_chip *chip, |
| 1172 | u8 channel) |
| 1173 | { |
| 1174 | int r; |
| 1175 | |
Daniel Drake | 9c8fc71 | 2007-05-24 01:06:41 +0100 | [diff] [blame] | 1176 | if (!zd_rf_should_update_pwr_int(&chip->rf)) |
| 1177 | return 0; |
| 1178 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1179 | r = update_pwr_int(chip, channel); |
| 1180 | if (r) |
| 1181 | return r; |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 1182 | if (zd_chip_is_zd1211b(chip)) { |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1183 | static const struct zd_ioreq16 ioreqs[] = { |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1184 | { CR69, 0x28 }, |
| 1185 | {}, |
| 1186 | { CR69, 0x2a }, |
| 1187 | }; |
| 1188 | |
| 1189 | r = update_ofdm_cal(chip, channel); |
| 1190 | if (r) |
| 1191 | return r; |
| 1192 | r = update_pwr_cal(chip, channel); |
| 1193 | if (r) |
| 1194 | return r; |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1195 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1196 | if (r) |
| 1197 | return r; |
| 1198 | } |
| 1199 | |
| 1200 | return 0; |
| 1201 | } |
| 1202 | |
| 1203 | /* The CCK baseband gain can be optionally patched by the EEPROM */ |
| 1204 | static int patch_cck_gain(struct zd_chip *chip) |
| 1205 | { |
| 1206 | int r; |
| 1207 | u32 value; |
| 1208 | |
Daniel Drake | aaf83d4 | 2007-05-24 01:07:15 +0100 | [diff] [blame] | 1209 | if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1210 | return 0; |
| 1211 | |
| 1212 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1213 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); |
| 1214 | if (r) |
| 1215 | return r; |
| 1216 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1217 | return zd_iowrite16_locked(chip, value & 0xff, CR47); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1218 | } |
| 1219 | |
| 1220 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) |
| 1221 | { |
| 1222 | int r, t; |
| 1223 | |
| 1224 | mutex_lock(&chip->mutex); |
| 1225 | r = zd_chip_lock_phy_regs(chip); |
| 1226 | if (r) |
| 1227 | goto out; |
| 1228 | r = zd_rf_set_channel(&chip->rf, channel); |
| 1229 | if (r) |
| 1230 | goto unlock; |
| 1231 | r = update_channel_integration_and_calibration(chip, channel); |
| 1232 | if (r) |
| 1233 | goto unlock; |
| 1234 | r = patch_cck_gain(chip); |
| 1235 | if (r) |
| 1236 | goto unlock; |
| 1237 | r = patch_6m_band_edge(chip, channel); |
| 1238 | if (r) |
| 1239 | goto unlock; |
| 1240 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); |
| 1241 | unlock: |
| 1242 | t = zd_chip_unlock_phy_regs(chip); |
| 1243 | if (t && !r) |
| 1244 | r = t; |
| 1245 | out: |
| 1246 | mutex_unlock(&chip->mutex); |
| 1247 | return r; |
| 1248 | } |
| 1249 | |
| 1250 | u8 zd_chip_get_channel(struct zd_chip *chip) |
| 1251 | { |
| 1252 | u8 channel; |
| 1253 | |
| 1254 | mutex_lock(&chip->mutex); |
| 1255 | channel = chip->rf.channel; |
| 1256 | mutex_unlock(&chip->mutex); |
| 1257 | return channel; |
| 1258 | } |
| 1259 | |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1260 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1261 | { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1262 | const zd_addr_t a[] = { |
| 1263 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1264 | CR_LED, |
| 1265 | }; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1266 | |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1267 | int r; |
| 1268 | u16 v[ARRAY_SIZE(a)]; |
| 1269 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1270 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1271 | [1] = { CR_LED }, |
| 1272 | }; |
| 1273 | u16 other_led; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1274 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1275 | mutex_lock(&chip->mutex); |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1276 | r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1277 | if (r) |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1278 | goto out; |
| 1279 | |
| 1280 | other_led = chip->link_led == LED1 ? LED2 : LED1; |
| 1281 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1282 | switch (status) { |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1283 | case LED_OFF: |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1284 | ioreqs[0].value = FW_LINK_OFF; |
| 1285 | ioreqs[1].value = v[1] & ~(LED1|LED2); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1286 | break; |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1287 | case LED_SCANNING: |
| 1288 | ioreqs[0].value = FW_LINK_OFF; |
| 1289 | ioreqs[1].value = v[1] & ~other_led; |
| 1290 | if (get_seconds() % 3 == 0) { |
| 1291 | ioreqs[1].value &= ~chip->link_led; |
| 1292 | } else { |
| 1293 | ioreqs[1].value |= chip->link_led; |
| 1294 | } |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1295 | break; |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1296 | case LED_ASSOCIATED: |
| 1297 | ioreqs[0].value = FW_LINK_TX; |
| 1298 | ioreqs[1].value = v[1] & ~other_led; |
| 1299 | ioreqs[1].value |= chip->link_led; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1300 | break; |
| 1301 | default: |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1302 | r = -EINVAL; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1303 | goto out; |
| 1304 | } |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1305 | |
| 1306 | if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { |
| 1307 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 1308 | if (r) |
| 1309 | goto out; |
| 1310 | } |
| 1311 | r = 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1312 | out: |
| 1313 | mutex_unlock(&chip->mutex); |
| 1314 | return r; |
| 1315 | } |
| 1316 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1317 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1318 | { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1319 | int r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1320 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1321 | if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) |
| 1322 | return -EINVAL; |
| 1323 | |
| 1324 | mutex_lock(&chip->mutex); |
| 1325 | r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); |
| 1326 | mutex_unlock(&chip->mutex); |
| 1327 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1328 | } |
| 1329 | |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1330 | static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1331 | { |
| 1332 | static const u16 constants[] = { |
| 1333 | 715, 655, 585, 540, 470, 410, 360, 315, |
| 1334 | 270, 235, 205, 175, 150, 125, 105, 85, |
| 1335 | 65, 50, 40, 25, 15 |
| 1336 | }; |
| 1337 | |
| 1338 | int i; |
| 1339 | u32 x; |
| 1340 | |
| 1341 | /* It seems that their quality parameter is somehow per signal |
| 1342 | * and is now transferred per bit. |
| 1343 | */ |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1344 | switch (zd_rate) { |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1345 | case ZD_OFDM_RATE_6M: |
| 1346 | case ZD_OFDM_RATE_12M: |
| 1347 | case ZD_OFDM_RATE_24M: |
| 1348 | size *= 2; |
| 1349 | break; |
| 1350 | case ZD_OFDM_RATE_9M: |
| 1351 | case ZD_OFDM_RATE_18M: |
| 1352 | case ZD_OFDM_RATE_36M: |
| 1353 | case ZD_OFDM_RATE_54M: |
| 1354 | size *= 4; |
| 1355 | size /= 3; |
| 1356 | break; |
| 1357 | case ZD_OFDM_RATE_48M: |
| 1358 | size *= 3; |
| 1359 | size /= 2; |
| 1360 | break; |
| 1361 | default: |
| 1362 | return -EINVAL; |
| 1363 | } |
| 1364 | |
| 1365 | x = (10000 * status_quality)/size; |
| 1366 | for (i = 0; i < ARRAY_SIZE(constants); i++) { |
| 1367 | if (x > constants[i]) |
| 1368 | break; |
| 1369 | } |
| 1370 | |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1371 | switch (zd_rate) { |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1372 | case ZD_OFDM_RATE_6M: |
| 1373 | case ZD_OFDM_RATE_9M: |
| 1374 | i += 3; |
| 1375 | break; |
| 1376 | case ZD_OFDM_RATE_12M: |
| 1377 | case ZD_OFDM_RATE_18M: |
| 1378 | i += 5; |
| 1379 | break; |
| 1380 | case ZD_OFDM_RATE_24M: |
| 1381 | case ZD_OFDM_RATE_36M: |
| 1382 | i += 9; |
| 1383 | break; |
| 1384 | case ZD_OFDM_RATE_48M: |
| 1385 | case ZD_OFDM_RATE_54M: |
| 1386 | i += 15; |
| 1387 | break; |
| 1388 | default: |
| 1389 | return -EINVAL; |
| 1390 | } |
| 1391 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1392 | return i; |
| 1393 | } |
| 1394 | |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1395 | static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size) |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1396 | { |
| 1397 | int r; |
| 1398 | |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1399 | r = ofdm_qual_db(status_quality, zd_rate, size); |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1400 | ZD_ASSERT(r >= 0); |
| 1401 | if (r < 0) |
| 1402 | r = 0; |
| 1403 | |
| 1404 | r = (r * 100)/29; |
| 1405 | return r <= 100 ? r : 100; |
| 1406 | } |
| 1407 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1408 | static unsigned int log10times100(unsigned int x) |
| 1409 | { |
| 1410 | static const u8 log10[] = { |
| 1411 | 0, |
| 1412 | 0, 30, 47, 60, 69, 77, 84, 90, 95, 100, |
| 1413 | 104, 107, 111, 114, 117, 120, 123, 125, 127, 130, |
| 1414 | 132, 134, 136, 138, 139, 141, 143, 144, 146, 147, |
| 1415 | 149, 150, 151, 153, 154, 155, 156, 157, 159, 160, |
| 1416 | 161, 162, 163, 164, 165, 166, 167, 168, 169, 169, |
| 1417 | 170, 171, 172, 173, 174, 174, 175, 176, 177, 177, |
| 1418 | 178, 179, 179, 180, 181, 181, 182, 183, 183, 184, |
| 1419 | 185, 185, 186, 186, 187, 188, 188, 189, 189, 190, |
| 1420 | 190, 191, 191, 192, 192, 193, 193, 194, 194, 195, |
| 1421 | 195, 196, 196, 197, 197, 198, 198, 199, 199, 200, |
| 1422 | 200, 200, 201, 201, 202, 202, 202, 203, 203, 204, |
| 1423 | 204, 204, 205, 205, 206, 206, 206, 207, 207, 207, |
| 1424 | 208, 208, 208, 209, 209, 210, 210, 210, 211, 211, |
| 1425 | 211, 212, 212, 212, 213, 213, 213, 213, 214, 214, |
| 1426 | 214, 215, 215, 215, 216, 216, 216, 217, 217, 217, |
| 1427 | 217, 218, 218, 218, 219, 219, 219, 219, 220, 220, |
| 1428 | 220, 220, 221, 221, 221, 222, 222, 222, 222, 223, |
| 1429 | 223, 223, 223, 224, 224, 224, 224, |
| 1430 | }; |
| 1431 | |
| 1432 | return x < ARRAY_SIZE(log10) ? log10[x] : 225; |
| 1433 | } |
| 1434 | |
| 1435 | enum { |
| 1436 | MAX_CCK_EVM_DB = 45, |
| 1437 | }; |
| 1438 | |
| 1439 | static int cck_evm_db(u8 status_quality) |
| 1440 | { |
| 1441 | return (20 * log10times100(status_quality)) / 100; |
| 1442 | } |
| 1443 | |
| 1444 | static int cck_snr_db(u8 status_quality) |
| 1445 | { |
| 1446 | int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality); |
| 1447 | ZD_ASSERT(r >= 0); |
| 1448 | return r; |
| 1449 | } |
| 1450 | |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1451 | static int cck_qual_percent(u8 status_quality) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1452 | { |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1453 | int r; |
| 1454 | |
| 1455 | r = cck_snr_db(status_quality); |
| 1456 | r = (100*r)/17; |
| 1457 | return r <= 100 ? r : 100; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1458 | } |
| 1459 | |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1460 | static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame) |
| 1461 | { |
| 1462 | return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame); |
| 1463 | } |
| 1464 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1465 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, |
| 1466 | const struct rx_status *status) |
| 1467 | { |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1468 | return (status->frame_status&ZD_RX_OFDM) ? |
| 1469 | ofdm_qual_percent(status->signal_quality_ofdm, |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1470 | zd_rate_from_ofdm_plcp_header(rx_frame), |
Ulrich Kunitz | db888ae | 2006-08-29 23:50:29 +0100 | [diff] [blame] | 1471 | size) : |
| 1472 | cck_qual_percent(status->signal_quality_cck); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1473 | } |
| 1474 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1475 | /** |
| 1476 | * zd_rx_rate - report zd-rate |
| 1477 | * @rx_frame - received frame |
| 1478 | * @rx_status - rx_status as given by the device |
| 1479 | * |
| 1480 | * This function converts the rate as encoded in the received packet to the |
| 1481 | * zd-rate, we are using on other places in the driver. |
| 1482 | */ |
| 1483 | u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1484 | { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1485 | u8 zd_rate; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1486 | if (status->frame_status & ZD_RX_OFDM) { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1487 | zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1488 | } else { |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1489 | switch (zd_cck_plcp_header_signal(rx_frame)) { |
| 1490 | case ZD_CCK_PLCP_SIGNAL_1M: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1491 | zd_rate = ZD_CCK_RATE_1M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1492 | break; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1493 | case ZD_CCK_PLCP_SIGNAL_2M: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1494 | zd_rate = ZD_CCK_RATE_2M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1495 | break; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1496 | case ZD_CCK_PLCP_SIGNAL_5M5: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1497 | zd_rate = ZD_CCK_RATE_5_5M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1498 | break; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1499 | case ZD_CCK_PLCP_SIGNAL_11M: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1500 | zd_rate = ZD_CCK_RATE_11M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1501 | break; |
| 1502 | default: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1503 | zd_rate = 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1504 | } |
| 1505 | } |
| 1506 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1507 | return zd_rate; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1508 | } |
| 1509 | |
| 1510 | int zd_chip_switch_radio_on(struct zd_chip *chip) |
| 1511 | { |
| 1512 | int r; |
| 1513 | |
| 1514 | mutex_lock(&chip->mutex); |
| 1515 | r = zd_switch_radio_on(&chip->rf); |
| 1516 | mutex_unlock(&chip->mutex); |
| 1517 | return r; |
| 1518 | } |
| 1519 | |
| 1520 | int zd_chip_switch_radio_off(struct zd_chip *chip) |
| 1521 | { |
| 1522 | int r; |
| 1523 | |
| 1524 | mutex_lock(&chip->mutex); |
| 1525 | r = zd_switch_radio_off(&chip->rf); |
| 1526 | mutex_unlock(&chip->mutex); |
| 1527 | return r; |
| 1528 | } |
| 1529 | |
| 1530 | int zd_chip_enable_int(struct zd_chip *chip) |
| 1531 | { |
| 1532 | int r; |
| 1533 | |
| 1534 | mutex_lock(&chip->mutex); |
| 1535 | r = zd_usb_enable_int(&chip->usb); |
| 1536 | mutex_unlock(&chip->mutex); |
| 1537 | return r; |
| 1538 | } |
| 1539 | |
| 1540 | void zd_chip_disable_int(struct zd_chip *chip) |
| 1541 | { |
| 1542 | mutex_lock(&chip->mutex); |
| 1543 | zd_usb_disable_int(&chip->usb); |
| 1544 | mutex_unlock(&chip->mutex); |
| 1545 | } |
| 1546 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1547 | int zd_chip_enable_rxtx(struct zd_chip *chip) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1548 | { |
| 1549 | int r; |
| 1550 | |
| 1551 | mutex_lock(&chip->mutex); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1552 | zd_usb_enable_tx(&chip->usb); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1553 | r = zd_usb_enable_rx(&chip->usb); |
| 1554 | mutex_unlock(&chip->mutex); |
| 1555 | return r; |
| 1556 | } |
| 1557 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1558 | void zd_chip_disable_rxtx(struct zd_chip *chip) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1559 | { |
| 1560 | mutex_lock(&chip->mutex); |
| 1561 | zd_usb_disable_rx(&chip->usb); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1562 | zd_usb_disable_tx(&chip->usb); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1563 | mutex_unlock(&chip->mutex); |
| 1564 | } |
| 1565 | |
| 1566 | int zd_rfwritev_locked(struct zd_chip *chip, |
| 1567 | const u32* values, unsigned int count, u8 bits) |
| 1568 | { |
| 1569 | int r; |
| 1570 | unsigned int i; |
| 1571 | |
| 1572 | for (i = 0; i < count; i++) { |
| 1573 | r = zd_rfwrite_locked(chip, values[i], bits); |
| 1574 | if (r) |
| 1575 | return r; |
| 1576 | } |
| 1577 | |
| 1578 | return 0; |
| 1579 | } |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 1580 | |
| 1581 | /* |
| 1582 | * We can optionally program the RF directly through CR regs, if supported by |
| 1583 | * the hardware. This is much faster than the older method. |
| 1584 | */ |
Daniel Drake | ec62bd9 | 2006-08-12 17:59:46 +0100 | [diff] [blame] | 1585 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 1586 | { |
| 1587 | struct zd_ioreq16 ioreqs[] = { |
| 1588 | { CR244, (value >> 16) & 0xff }, |
| 1589 | { CR243, (value >> 8) & 0xff }, |
| 1590 | { CR242, value & 0xff }, |
| 1591 | }; |
| 1592 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1593 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 1594 | } |
| 1595 | |
| 1596 | int zd_rfwritev_cr_locked(struct zd_chip *chip, |
| 1597 | const u32 *values, unsigned int count) |
| 1598 | { |
| 1599 | int r; |
| 1600 | unsigned int i; |
| 1601 | |
| 1602 | for (i = 0; i < count; i++) { |
| 1603 | r = zd_rfwrite_cr_locked(chip, values[i]); |
| 1604 | if (r) |
| 1605 | return r; |
| 1606 | } |
| 1607 | |
| 1608 | return 0; |
| 1609 | } |
Ulrich Kunitz | 9cdac96 | 2006-12-01 00:58:07 +0000 | [diff] [blame] | 1610 | |
| 1611 | int zd_chip_set_multicast_hash(struct zd_chip *chip, |
| 1612 | struct zd_mc_hash *hash) |
| 1613 | { |
| 1614 | struct zd_ioreq32 ioreqs[] = { |
| 1615 | { CR_GROUP_HASH_P1, hash->low }, |
| 1616 | { CR_GROUP_HASH_P2, hash->high }, |
| 1617 | }; |
| 1618 | |
Ulrich Kunitz | 9cdac96 | 2006-12-01 00:58:07 +0000 | [diff] [blame] | 1619 | return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 1620 | } |