Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. |
| 3 | * |
| 4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * Copyright (c) 2012 Linaro Ltd |
| 7 | * http://www.linaro.org |
| 8 | * |
| 9 | * Author: Thomas Abraham <thomas.ab@samsung.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This file contains the Samsung Exynos specific information required by the |
| 17 | * the Samsung pinctrl/gpiolib driver. It also includes the implementation of |
| 18 | * external gpio and wakeup interrupt support. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/irqdomain.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/err.h> |
| 30 | |
| 31 | #include <asm/mach/irq.h> |
| 32 | |
| 33 | #include "pinctrl-samsung.h" |
| 34 | #include "pinctrl-exynos.h" |
| 35 | |
| 36 | /* list of external wakeup controllers supported */ |
| 37 | static const struct of_device_id exynos_wkup_irq_ids[] = { |
| 38 | { .compatible = "samsung,exynos4210-wakeup-eint", }, |
| 39 | }; |
| 40 | |
| 41 | static void exynos_gpio_irq_unmask(struct irq_data *irqd) |
| 42 | { |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 43 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
| 44 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
| 45 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 46 | unsigned long mask; |
| 47 | |
| 48 | mask = readl(d->virt_base + reg_mask); |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 49 | mask &= ~(1 << irqd->hwirq); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 50 | writel(mask, d->virt_base + reg_mask); |
| 51 | } |
| 52 | |
| 53 | static void exynos_gpio_irq_mask(struct irq_data *irqd) |
| 54 | { |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 55 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
| 56 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
| 57 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 58 | unsigned long mask; |
| 59 | |
| 60 | mask = readl(d->virt_base + reg_mask); |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 61 | mask |= 1 << irqd->hwirq; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 62 | writel(mask, d->virt_base + reg_mask); |
| 63 | } |
| 64 | |
| 65 | static void exynos_gpio_irq_ack(struct irq_data *irqd) |
| 66 | { |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 67 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
| 68 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
| 69 | unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 70 | |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 71 | writel(1 << irqd->hwirq, d->virt_base + reg_pend); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) |
| 75 | { |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 76 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
| 77 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 78 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 79 | unsigned int pin = irqd->hwirq; |
| 80 | unsigned int shift = EXYNOS_EINT_CON_LEN * pin; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 81 | unsigned int con, trig_type; |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 82 | unsigned long reg_con = ctrl->geint_con + bank->eint_offset; |
Tomasz Figa | ee2f573 | 2012-09-21 07:33:48 +0900 | [diff] [blame] | 83 | unsigned int mask; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 84 | |
| 85 | switch (type) { |
| 86 | case IRQ_TYPE_EDGE_RISING: |
| 87 | trig_type = EXYNOS_EINT_EDGE_RISING; |
| 88 | break; |
| 89 | case IRQ_TYPE_EDGE_FALLING: |
| 90 | trig_type = EXYNOS_EINT_EDGE_FALLING; |
| 91 | break; |
| 92 | case IRQ_TYPE_EDGE_BOTH: |
| 93 | trig_type = EXYNOS_EINT_EDGE_BOTH; |
| 94 | break; |
| 95 | case IRQ_TYPE_LEVEL_HIGH: |
| 96 | trig_type = EXYNOS_EINT_LEVEL_HIGH; |
| 97 | break; |
| 98 | case IRQ_TYPE_LEVEL_LOW: |
| 99 | trig_type = EXYNOS_EINT_LEVEL_LOW; |
| 100 | break; |
| 101 | default: |
| 102 | pr_err("unsupported external interrupt type\n"); |
| 103 | return -EINVAL; |
| 104 | } |
| 105 | |
| 106 | if (type & IRQ_TYPE_EDGE_BOTH) |
| 107 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); |
| 108 | else |
| 109 | __irq_set_handler_locked(irqd->irq, handle_level_irq); |
| 110 | |
| 111 | con = readl(d->virt_base + reg_con); |
| 112 | con &= ~(EXYNOS_EINT_CON_MASK << shift); |
| 113 | con |= trig_type << shift; |
| 114 | writel(con, d->virt_base + reg_con); |
Tomasz Figa | ee2f573 | 2012-09-21 07:33:48 +0900 | [diff] [blame] | 115 | |
| 116 | reg_con = bank->pctl_offset; |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 117 | shift = pin * bank->func_width; |
Tomasz Figa | ee2f573 | 2012-09-21 07:33:48 +0900 | [diff] [blame] | 118 | mask = (1 << bank->func_width) - 1; |
| 119 | |
| 120 | con = readl(d->virt_base + reg_con); |
| 121 | con &= ~(mask << shift); |
| 122 | con |= EXYNOS_EINT_FUNC << shift; |
| 123 | writel(con, d->virt_base + reg_con); |
| 124 | |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * irq_chip for gpio interrupts. |
| 130 | */ |
| 131 | static struct irq_chip exynos_gpio_irq_chip = { |
| 132 | .name = "exynos_gpio_irq_chip", |
| 133 | .irq_unmask = exynos_gpio_irq_unmask, |
| 134 | .irq_mask = exynos_gpio_irq_mask, |
| 135 | .irq_ack = exynos_gpio_irq_ack, |
| 136 | .irq_set_type = exynos_gpio_irq_set_type, |
| 137 | }; |
| 138 | |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 139 | static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
| 140 | irq_hw_number_t hw) |
| 141 | { |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 142 | struct samsung_pin_bank *b = h->host_data; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 143 | |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 144 | irq_set_chip_data(virq, b); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 145 | irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, |
| 146 | handle_level_irq); |
| 147 | set_irq_flags(virq, IRQF_VALID); |
| 148 | return 0; |
| 149 | } |
| 150 | |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 151 | /* |
| 152 | * irq domain callbacks for external gpio interrupt controller. |
| 153 | */ |
| 154 | static const struct irq_domain_ops exynos_gpio_irqd_ops = { |
| 155 | .map = exynos_gpio_irq_map, |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 156 | .xlate = irq_domain_xlate_twocell, |
| 157 | }; |
| 158 | |
| 159 | static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) |
| 160 | { |
| 161 | struct samsung_pinctrl_drv_data *d = data; |
| 162 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
| 163 | struct samsung_pin_bank *bank = ctrl->pin_banks; |
| 164 | unsigned int svc, group, pin, virq; |
| 165 | |
| 166 | svc = readl(d->virt_base + ctrl->svc); |
| 167 | group = EXYNOS_SVC_GROUP(svc); |
| 168 | pin = svc & EXYNOS_SVC_NUM_MASK; |
| 169 | |
| 170 | if (!group) |
| 171 | return IRQ_HANDLED; |
| 172 | bank += (group - 1); |
| 173 | |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 174 | virq = irq_linear_revmap(bank->irq_domain, pin); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 175 | if (!virq) |
| 176 | return IRQ_NONE; |
| 177 | generic_handle_irq(virq); |
| 178 | return IRQ_HANDLED; |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * exynos_eint_gpio_init() - setup handling of external gpio interrupts. |
| 183 | * @d: driver data of samsung pinctrl driver. |
| 184 | */ |
| 185 | static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) |
| 186 | { |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 187 | struct samsung_pin_bank *bank; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 188 | struct device *dev = d->dev; |
| 189 | unsigned int ret; |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 190 | unsigned int i; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 191 | |
| 192 | if (!d->irq) { |
| 193 | dev_err(dev, "irq number not available\n"); |
| 194 | return -EINVAL; |
| 195 | } |
| 196 | |
| 197 | ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, |
| 198 | 0, dev_name(dev), d); |
| 199 | if (ret) { |
| 200 | dev_err(dev, "irq request failed\n"); |
| 201 | return -ENXIO; |
| 202 | } |
| 203 | |
Tomasz Figa | 595be72 | 2012-10-11 10:11:16 +0200 | [diff] [blame] | 204 | bank = d->ctrl->pin_banks; |
| 205 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { |
| 206 | if (bank->eint_type != EINT_TYPE_GPIO) |
| 207 | continue; |
| 208 | bank->irq_domain = irq_domain_add_linear(bank->of_node, |
| 209 | bank->nr_pins, &exynos_gpio_irqd_ops, bank); |
| 210 | if (!bank->irq_domain) { |
| 211 | dev_err(dev, "gpio irq domain add failed\n"); |
| 212 | return -ENXIO; |
| 213 | } |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | static void exynos_wkup_irq_unmask(struct irq_data *irqd) |
| 220 | { |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 221 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
| 222 | struct samsung_pinctrl_drv_data *d = b->drvdata; |
| 223 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 224 | unsigned long mask; |
| 225 | |
| 226 | mask = readl(d->virt_base + reg_mask); |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 227 | mask &= ~(1 << irqd->hwirq); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 228 | writel(mask, d->virt_base + reg_mask); |
| 229 | } |
| 230 | |
| 231 | static void exynos_wkup_irq_mask(struct irq_data *irqd) |
| 232 | { |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 233 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
| 234 | struct samsung_pinctrl_drv_data *d = b->drvdata; |
| 235 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 236 | unsigned long mask; |
| 237 | |
| 238 | mask = readl(d->virt_base + reg_mask); |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 239 | mask |= 1 << irqd->hwirq; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 240 | writel(mask, d->virt_base + reg_mask); |
| 241 | } |
| 242 | |
| 243 | static void exynos_wkup_irq_ack(struct irq_data *irqd) |
| 244 | { |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 245 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
| 246 | struct samsung_pinctrl_drv_data *d = b->drvdata; |
| 247 | unsigned long pend = d->ctrl->weint_pend + b->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 248 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 249 | writel(1 << irqd->hwirq, d->virt_base + pend); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) |
| 253 | { |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 254 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
| 255 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
| 256 | unsigned int pin = irqd->hwirq; |
| 257 | unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 258 | unsigned long shift = EXYNOS_EINT_CON_LEN * pin; |
| 259 | unsigned long con, trig_type; |
Tomasz Figa | 22b9ba0 | 2012-10-11 10:11:19 +0200 | [diff] [blame] | 260 | unsigned int mask; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 261 | |
| 262 | switch (type) { |
| 263 | case IRQ_TYPE_EDGE_RISING: |
| 264 | trig_type = EXYNOS_EINT_EDGE_RISING; |
| 265 | break; |
| 266 | case IRQ_TYPE_EDGE_FALLING: |
| 267 | trig_type = EXYNOS_EINT_EDGE_FALLING; |
| 268 | break; |
| 269 | case IRQ_TYPE_EDGE_BOTH: |
| 270 | trig_type = EXYNOS_EINT_EDGE_BOTH; |
| 271 | break; |
| 272 | case IRQ_TYPE_LEVEL_HIGH: |
| 273 | trig_type = EXYNOS_EINT_LEVEL_HIGH; |
| 274 | break; |
| 275 | case IRQ_TYPE_LEVEL_LOW: |
| 276 | trig_type = EXYNOS_EINT_LEVEL_LOW; |
| 277 | break; |
| 278 | default: |
| 279 | pr_err("unsupported external interrupt type\n"); |
| 280 | return -EINVAL; |
| 281 | } |
| 282 | |
| 283 | if (type & IRQ_TYPE_EDGE_BOTH) |
| 284 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); |
| 285 | else |
| 286 | __irq_set_handler_locked(irqd->irq, handle_level_irq); |
| 287 | |
| 288 | con = readl(d->virt_base + reg_con); |
| 289 | con &= ~(EXYNOS_EINT_CON_MASK << shift); |
| 290 | con |= trig_type << shift; |
| 291 | writel(con, d->virt_base + reg_con); |
Tomasz Figa | 22b9ba0 | 2012-10-11 10:11:19 +0200 | [diff] [blame] | 292 | |
| 293 | reg_con = bank->pctl_offset; |
| 294 | shift = pin * bank->func_width; |
| 295 | mask = (1 << bank->func_width) - 1; |
| 296 | |
| 297 | con = readl(d->virt_base + reg_con); |
| 298 | con &= ~(mask << shift); |
| 299 | con |= EXYNOS_EINT_FUNC << shift; |
| 300 | writel(con, d->virt_base + reg_con); |
| 301 | |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 302 | return 0; |
| 303 | } |
| 304 | |
| 305 | /* |
| 306 | * irq_chip for wakeup interrupts |
| 307 | */ |
| 308 | static struct irq_chip exynos_wkup_irq_chip = { |
| 309 | .name = "exynos_wkup_irq_chip", |
| 310 | .irq_unmask = exynos_wkup_irq_unmask, |
| 311 | .irq_mask = exynos_wkup_irq_mask, |
| 312 | .irq_ack = exynos_wkup_irq_ack, |
| 313 | .irq_set_type = exynos_wkup_irq_set_type, |
| 314 | }; |
| 315 | |
| 316 | /* interrupt handler for wakeup interrupts 0..15 */ |
| 317 | static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) |
| 318 | { |
| 319 | struct exynos_weint_data *eintd = irq_get_handler_data(irq); |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 320 | struct samsung_pin_bank *bank = eintd->bank; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 321 | struct irq_chip *chip = irq_get_chip(irq); |
| 322 | int eint_irq; |
| 323 | |
| 324 | chained_irq_enter(chip, desc); |
| 325 | chip->irq_mask(&desc->irq_data); |
| 326 | |
| 327 | if (chip->irq_ack) |
| 328 | chip->irq_ack(&desc->irq_data); |
| 329 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 330 | eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 331 | generic_handle_irq(eint_irq); |
| 332 | chip->irq_unmask(&desc->irq_data); |
| 333 | chained_irq_exit(chip, desc); |
| 334 | } |
| 335 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 336 | static inline void exynos_irq_demux_eint(unsigned long pend, |
| 337 | struct irq_domain *domain) |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 338 | { |
| 339 | unsigned int irq; |
| 340 | |
| 341 | while (pend) { |
| 342 | irq = fls(pend) - 1; |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 343 | generic_handle_irq(irq_find_mapping(domain, irq)); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 344 | pend &= ~(1 << irq); |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | /* interrupt handler for wakeup interrupt 16 */ |
| 349 | static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) |
| 350 | { |
| 351 | struct irq_chip *chip = irq_get_chip(irq); |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 352 | struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); |
| 353 | struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; |
| 354 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 355 | unsigned long pend; |
Tomasz Figa | de59049 | 2012-09-21 07:33:55 +0900 | [diff] [blame] | 356 | unsigned long mask; |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 357 | int i; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 358 | |
| 359 | chained_irq_enter(chip, desc); |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 360 | |
| 361 | for (i = 0; i < eintd->nr_banks; ++i) { |
| 362 | struct samsung_pin_bank *b = eintd->banks[i]; |
| 363 | pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); |
| 364 | mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); |
| 365 | exynos_irq_demux_eint(pend & ~mask, b->irq_domain); |
| 366 | } |
| 367 | |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 368 | chained_irq_exit(chip, desc); |
| 369 | } |
| 370 | |
| 371 | static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, |
| 372 | irq_hw_number_t hw) |
| 373 | { |
| 374 | irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); |
| 375 | irq_set_chip_data(virq, h->host_data); |
| 376 | set_irq_flags(virq, IRQF_VALID); |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | /* |
| 381 | * irq domain callbacks for external wakeup interrupt controller. |
| 382 | */ |
| 383 | static const struct irq_domain_ops exynos_wkup_irqd_ops = { |
| 384 | .map = exynos_wkup_irq_map, |
| 385 | .xlate = irq_domain_xlate_twocell, |
| 386 | }; |
| 387 | |
| 388 | /* |
| 389 | * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. |
| 390 | * @d: driver data of samsung pinctrl driver. |
| 391 | */ |
| 392 | static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) |
| 393 | { |
| 394 | struct device *dev = d->dev; |
Tomasz Figa | c3ad056 | 2012-09-21 07:34:01 +0900 | [diff] [blame] | 395 | struct device_node *wkup_np = NULL; |
| 396 | struct device_node *np; |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 397 | struct samsung_pin_bank *bank; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 398 | struct exynos_weint_data *weint_data; |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 399 | struct exynos_muxed_weint_data *muxed_data; |
| 400 | unsigned int muxed_banks = 0; |
| 401 | unsigned int i; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 402 | int idx, irq; |
| 403 | |
Tomasz Figa | c3ad056 | 2012-09-21 07:34:01 +0900 | [diff] [blame] | 404 | for_each_child_of_node(dev->of_node, np) { |
| 405 | if (of_match_node(exynos_wkup_irq_ids, np)) { |
| 406 | wkup_np = np; |
| 407 | break; |
| 408 | } |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 409 | } |
Tomasz Figa | c3ad056 | 2012-09-21 07:34:01 +0900 | [diff] [blame] | 410 | if (!wkup_np) |
| 411 | return -ENODEV; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 412 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 413 | bank = d->ctrl->pin_banks; |
| 414 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { |
| 415 | if (bank->eint_type != EINT_TYPE_WKUP) |
| 416 | continue; |
| 417 | |
| 418 | bank->irq_domain = irq_domain_add_linear(bank->of_node, |
| 419 | bank->nr_pins, &exynos_wkup_irqd_ops, bank); |
| 420 | if (!bank->irq_domain) { |
| 421 | dev_err(dev, "wkup irq domain add failed\n"); |
| 422 | return -ENXIO; |
| 423 | } |
| 424 | |
| 425 | if (!of_find_property(bank->of_node, "interrupts", NULL)) { |
| 426 | bank->eint_type = EINT_TYPE_WKUP_MUX; |
| 427 | ++muxed_banks; |
| 428 | continue; |
| 429 | } |
| 430 | |
| 431 | weint_data = devm_kzalloc(dev, bank->nr_pins |
| 432 | * sizeof(*weint_data), GFP_KERNEL); |
| 433 | if (!weint_data) { |
| 434 | dev_err(dev, "could not allocate memory for weint_data\n"); |
| 435 | return -ENOMEM; |
| 436 | } |
| 437 | |
| 438 | for (idx = 0; idx < bank->nr_pins; ++idx) { |
| 439 | irq = irq_of_parse_and_map(bank->of_node, idx); |
| 440 | if (!irq) { |
| 441 | dev_err(dev, "irq number for eint-%s-%d not found\n", |
| 442 | bank->name, idx); |
| 443 | continue; |
| 444 | } |
| 445 | weint_data[idx].irq = idx; |
| 446 | weint_data[idx].bank = bank; |
| 447 | irq_set_handler_data(irq, &weint_data[idx]); |
| 448 | irq_set_chained_handler(irq, exynos_irq_eint0_15); |
| 449 | } |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 450 | } |
| 451 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 452 | if (!muxed_banks) |
| 453 | return 0; |
| 454 | |
| 455 | irq = irq_of_parse_and_map(wkup_np, 0); |
| 456 | if (!irq) { |
| 457 | dev_err(dev, "irq number for muxed EINTs not found\n"); |
| 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) |
| 462 | + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); |
| 463 | if (!muxed_data) { |
| 464 | dev_err(dev, "could not allocate memory for muxed_data\n"); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 465 | return -ENOMEM; |
| 466 | } |
| 467 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 468 | irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); |
| 469 | irq_set_handler_data(irq, muxed_data); |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 470 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 471 | bank = d->ctrl->pin_banks; |
| 472 | idx = 0; |
| 473 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { |
| 474 | if (bank->eint_type != EINT_TYPE_WKUP_MUX) |
| 475 | continue; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 476 | |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 477 | muxed_data->banks[idx++] = bank; |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 478 | } |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 479 | muxed_data->nr_banks = muxed_banks; |
| 480 | |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | /* pin banks of exynos4210 pin-controller 0 */ |
| 485 | static struct samsung_pin_bank exynos4210_pin_banks0[] = { |
Tomasz Figa | 1b6056d | 2012-10-11 10:11:15 +0200 | [diff] [blame] | 486 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
| 487 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), |
| 488 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), |
| 489 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), |
| 490 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), |
| 491 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), |
| 492 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), |
| 493 | EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), |
| 494 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), |
| 495 | EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), |
| 496 | EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), |
| 497 | EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), |
| 498 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), |
| 499 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), |
| 500 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), |
| 501 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 502 | }; |
| 503 | |
| 504 | /* pin banks of exynos4210 pin-controller 1 */ |
| 505 | static struct samsung_pin_bank exynos4210_pin_banks1[] = { |
Tomasz Figa | 1b6056d | 2012-10-11 10:11:15 +0200 | [diff] [blame] | 506 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), |
| 507 | EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), |
| 508 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), |
| 509 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), |
| 510 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), |
| 511 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), |
| 512 | EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), |
| 513 | EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), |
| 514 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), |
Tomasz Figa | 40ba622 | 2012-10-11 10:11:09 +0200 | [diff] [blame] | 515 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), |
| 516 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), |
| 517 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), |
| 518 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), |
| 519 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), |
| 520 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), |
| 521 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), |
Tomasz Figa | a04b07c | 2012-10-11 10:11:18 +0200 | [diff] [blame] | 522 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), |
| 523 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), |
| 524 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), |
| 525 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 526 | }; |
| 527 | |
| 528 | /* pin banks of exynos4210 pin-controller 2 */ |
| 529 | static struct samsung_pin_bank exynos4210_pin_banks2[] = { |
Tomasz Figa | 40ba622 | 2012-10-11 10:11:09 +0200 | [diff] [blame] | 530 | EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 531 | }; |
| 532 | |
| 533 | /* |
| 534 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes |
| 535 | * three gpio/pin-mux/pinconfig controllers. |
| 536 | */ |
| 537 | struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { |
| 538 | { |
| 539 | /* pin-controller instance 0 data */ |
| 540 | .pin_banks = exynos4210_pin_banks0, |
| 541 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 542 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
| 543 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, |
| 544 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, |
| 545 | .svc = EXYNOS_SVC_OFFSET, |
| 546 | .eint_gpio_init = exynos_eint_gpio_init, |
| 547 | .label = "exynos4210-gpio-ctrl0", |
| 548 | }, { |
| 549 | /* pin-controller instance 1 data */ |
| 550 | .pin_banks = exynos4210_pin_banks1, |
| 551 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 552 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
| 553 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, |
| 554 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, |
| 555 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, |
| 556 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, |
| 557 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, |
| 558 | .svc = EXYNOS_SVC_OFFSET, |
| 559 | .eint_gpio_init = exynos_eint_gpio_init, |
| 560 | .eint_wkup_init = exynos_eint_wkup_init, |
| 561 | .label = "exynos4210-gpio-ctrl1", |
| 562 | }, { |
| 563 | /* pin-controller instance 2 data */ |
| 564 | .pin_banks = exynos4210_pin_banks2, |
| 565 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), |
Thomas Abraham | 43b169d | 2012-09-07 06:07:19 +0900 | [diff] [blame] | 566 | .label = "exynos4210-gpio-ctrl2", |
| 567 | }, |
| 568 | }; |
Tomasz Figa | 6edc794 | 2012-11-07 08:44:59 +0900 | [diff] [blame] | 569 | |
| 570 | /* pin banks of exynos4x12 pin-controller 0 */ |
| 571 | static struct samsung_pin_bank exynos4x12_pin_banks0[] = { |
| 572 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
| 573 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), |
| 574 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), |
| 575 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), |
| 576 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), |
| 577 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), |
| 578 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), |
| 579 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), |
| 580 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), |
| 581 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), |
| 582 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), |
| 583 | EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), |
| 584 | EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), |
| 585 | }; |
| 586 | |
| 587 | /* pin banks of exynos4x12 pin-controller 1 */ |
| 588 | static struct samsung_pin_bank exynos4x12_pin_banks1[] = { |
| 589 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), |
| 590 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), |
| 591 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), |
| 592 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), |
| 593 | EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), |
| 594 | EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), |
| 595 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), |
| 596 | EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), |
| 597 | EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), |
| 598 | EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), |
| 599 | EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), |
| 600 | EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), |
| 601 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), |
| 602 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), |
| 603 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), |
| 604 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), |
| 605 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), |
| 606 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), |
| 607 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), |
| 608 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), |
| 609 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), |
| 610 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), |
| 611 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), |
| 612 | }; |
| 613 | |
| 614 | /* pin banks of exynos4x12 pin-controller 2 */ |
| 615 | static struct samsung_pin_bank exynos4x12_pin_banks2[] = { |
| 616 | EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), |
| 617 | }; |
| 618 | |
| 619 | /* pin banks of exynos4x12 pin-controller 3 */ |
| 620 | static struct samsung_pin_bank exynos4x12_pin_banks3[] = { |
| 621 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), |
| 622 | EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), |
| 623 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), |
| 624 | EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), |
| 625 | EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), |
| 626 | }; |
| 627 | |
| 628 | /* |
| 629 | * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes |
| 630 | * four gpio/pin-mux/pinconfig controllers. |
| 631 | */ |
| 632 | struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { |
| 633 | { |
| 634 | /* pin-controller instance 0 data */ |
| 635 | .pin_banks = exynos4x12_pin_banks0, |
| 636 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), |
| 637 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
| 638 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, |
| 639 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, |
| 640 | .svc = EXYNOS_SVC_OFFSET, |
| 641 | .eint_gpio_init = exynos_eint_gpio_init, |
| 642 | .label = "exynos4x12-gpio-ctrl0", |
| 643 | }, { |
| 644 | /* pin-controller instance 1 data */ |
| 645 | .pin_banks = exynos4x12_pin_banks1, |
| 646 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), |
| 647 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
| 648 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, |
| 649 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, |
| 650 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, |
| 651 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, |
| 652 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, |
| 653 | .svc = EXYNOS_SVC_OFFSET, |
| 654 | .eint_gpio_init = exynos_eint_gpio_init, |
| 655 | .eint_wkup_init = exynos_eint_wkup_init, |
| 656 | .label = "exynos4x12-gpio-ctrl1", |
| 657 | }, { |
| 658 | /* pin-controller instance 2 data */ |
| 659 | .pin_banks = exynos4x12_pin_banks2, |
| 660 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), |
| 661 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
| 662 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, |
| 663 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, |
| 664 | .svc = EXYNOS_SVC_OFFSET, |
| 665 | .eint_gpio_init = exynos_eint_gpio_init, |
| 666 | .label = "exynos4x12-gpio-ctrl2", |
| 667 | }, { |
| 668 | /* pin-controller instance 3 data */ |
| 669 | .pin_banks = exynos4x12_pin_banks3, |
| 670 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), |
| 671 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
| 672 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, |
| 673 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, |
| 674 | .svc = EXYNOS_SVC_OFFSET, |
| 675 | .eint_gpio_init = exynos_eint_gpio_init, |
| 676 | .label = "exynos4x12-gpio-ctrl3", |
| 677 | }, |
| 678 | }; |