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Andrew Victor1a0ed732006-12-01 09:04:47 +01001/*
Andrew Victorad48ce72008-04-16 20:43:49 +01002 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
Andrew Victor1a0ed732006-12-01 09:04:47 +01003 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
Andrew Victorad48ce72008-04-16 20:43:49 +01006 * Converted to ClockSource/ClockEvents by David Brownell.
Andrew Victor1a0ed732006-12-01 09:04:47 +01007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Andrew Victor1a0ed732006-12-01 09:04:47 +010012#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/kernel.h>
Andrew Victorad48ce72008-04-16 20:43:49 +010015#include <linux/clk.h>
16#include <linux/clockchips.h>
Andrew Victor1a0ed732006-12-01 09:04:47 +010017
Andrew Victor1a0ed732006-12-01 09:04:47 +010018#include <asm/mach/time.h>
19
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/at91_pit.h>
Andrew Victor1a0ed732006-12-01 09:04:47 +010021
22
23#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
24#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
25
Andrew Victorad48ce72008-04-16 20:43:49 +010026static u32 pit_cycle; /* write-once */
27static u32 pit_cnt; /* access only w/system irq blocked */
28
29
Andrew Victor1a0ed732006-12-01 09:04:47 +010030/*
Andrew Victorad48ce72008-04-16 20:43:49 +010031 * Clocksource: just a monotonic counter of MCK/16 cycles.
32 * We don't care whether or not PIT irqs are enabled.
Andrew Victor1a0ed732006-12-01 09:04:47 +010033 */
Andrew Victorad48ce72008-04-16 20:43:49 +010034static cycle_t read_pit_clk(void)
Andrew Victor1a0ed732006-12-01 09:04:47 +010035{
Andrew Victorad48ce72008-04-16 20:43:49 +010036 unsigned long flags;
37 u32 elapsed;
38 u32 t;
Andrew Victor1a0ed732006-12-01 09:04:47 +010039
Andrew Victorad48ce72008-04-16 20:43:49 +010040 raw_local_irq_save(flags);
41 elapsed = pit_cnt;
42 t = at91_sys_read(AT91_PIT_PIIR);
43 raw_local_irq_restore(flags);
Andrew Victor1a0ed732006-12-01 09:04:47 +010044
Andrew Victorad48ce72008-04-16 20:43:49 +010045 elapsed += PIT_PICNT(t) * pit_cycle;
46 elapsed += PIT_CPIV(t);
47 return elapsed;
Andrew Victor1a0ed732006-12-01 09:04:47 +010048}
49
Andrew Victorad48ce72008-04-16 20:43:49 +010050static struct clocksource pit_clk = {
51 .name = "pit",
52 .rating = 175,
53 .read = read_pit_clk,
54 .shift = 20,
55 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
56};
57
58
59/*
60 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
61 */
62static void
63pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
64{
65 unsigned long flags;
66
67 switch (mode) {
68 case CLOCK_EVT_MODE_PERIODIC:
69 /* update clocksource counter, then enable the IRQ */
70 raw_local_irq_save(flags);
71 pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
72 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
73 | AT91_PIT_PITIEN);
74 raw_local_irq_restore(flags);
75 break;
76 case CLOCK_EVT_MODE_ONESHOT:
77 BUG();
78 /* FALLTHROUGH */
79 case CLOCK_EVT_MODE_SHUTDOWN:
80 case CLOCK_EVT_MODE_UNUSED:
81 /* disable irq, leaving the clocksource active */
82 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
83 break;
84 case CLOCK_EVT_MODE_RESUME:
85 break;
86 }
87}
88
89static struct clock_event_device pit_clkevt = {
90 .name = "pit",
91 .features = CLOCK_EVT_FEAT_PERIODIC,
92 .shift = 32,
93 .rating = 100,
94 .cpumask = CPU_MASK_CPU0,
95 .set_mode = pit_clkevt_mode,
96};
97
98
Andrew Victor1a0ed732006-12-01 09:04:47 +010099/*
100 * IRQ handler for the timer.
101 */
Andrew Victorad48ce72008-04-16 20:43:49 +0100102static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100103{
Andrew Victor1a0ed732006-12-01 09:04:47 +0100104
Andrew Victorad48ce72008-04-16 20:43:49 +0100105 /* The PIT interrupt may be disabled, and is shared */
106 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
107 && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
108 unsigned nr_ticks;
109
110 /* Get number of ticks performed before irq, and ack it */
Andrew Victor1a0ed732006-12-01 09:04:47 +0100111 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
112 do {
Andrew Victorad48ce72008-04-16 20:43:49 +0100113 pit_cnt += pit_cycle;
114 pit_clkevt.event_handler(&pit_clkevt);
Andrew Victor1a0ed732006-12-01 09:04:47 +0100115 nr_ticks--;
116 } while (nr_ticks);
117
Andrew Victor1a0ed732006-12-01 09:04:47 +0100118 return IRQ_HANDLED;
Andrew Victorad48ce72008-04-16 20:43:49 +0100119 }
120
121 return IRQ_NONE;
Andrew Victor1a0ed732006-12-01 09:04:47 +0100122}
123
Andrew Victorad48ce72008-04-16 20:43:49 +0100124static struct irqaction at91sam926x_pit_irq = {
Andrew Victor1a0ed732006-12-01 09:04:47 +0100125 .name = "at91_tick",
Bernhard Walleb30faba2007-05-08 00:35:39 -0700126 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Andrew Victorad48ce72008-04-16 20:43:49 +0100127 .handler = at91sam926x_pit_interrupt
Andrew Victor1a0ed732006-12-01 09:04:47 +0100128};
129
Andrew Victorad48ce72008-04-16 20:43:49 +0100130static void at91sam926x_pit_reset(void)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100131{
Andrew Victorad48ce72008-04-16 20:43:49 +0100132 /* Disable timer and irqs */
Andrew Victor1a0ed732006-12-01 09:04:47 +0100133 at91_sys_write(AT91_PIT_MR, 0);
134
Andrew Victorad48ce72008-04-16 20:43:49 +0100135 /* Clear any pending interrupts, wait for PIT to stop counting */
136 while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
137 cpu_relax();
Andrew Victor1a0ed732006-12-01 09:04:47 +0100138
Andrew Victorad48ce72008-04-16 20:43:49 +0100139 /* Start PIT but don't enable IRQ */
140 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
Andrew Victor1a0ed732006-12-01 09:04:47 +0100141}
142
143/*
Andrew Victorad48ce72008-04-16 20:43:49 +0100144 * Set up both clocksource and clockevent support.
Andrew Victor1a0ed732006-12-01 09:04:47 +0100145 */
Andrew Victorad48ce72008-04-16 20:43:49 +0100146static void __init at91sam926x_pit_init(void)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100147{
Andrew Victorad48ce72008-04-16 20:43:49 +0100148 unsigned long pit_rate;
149 unsigned bits;
Andrew Victor1a0ed732006-12-01 09:04:47 +0100150
Andrew Victorad48ce72008-04-16 20:43:49 +0100151 /*
152 * Use our actual MCK to figure out how many MCK/16 ticks per
153 * 1/HZ period (instead of a compile-time constant LATCH).
154 */
155 pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
156 pit_cycle = (pit_rate + HZ/2) / HZ;
157 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
158
159 /* Initialize and enable the timer */
160 at91sam926x_pit_reset();
161
162 /*
163 * Register clocksource. The high order bits of PIV are unused,
164 * so this isn't a 32-bit counter unless we get clockevent irqs.
165 */
166 pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
167 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
168 pit_clk.mask = CLOCKSOURCE_MASK(bits);
169 clocksource_register(&pit_clk);
170
171 /* Set up irq handler */
172 setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
173
174 /* Set up and register clockevents */
175 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
176 clockevents_register_device(&pit_clkevt);
Andrew Victor1a0ed732006-12-01 09:04:47 +0100177}
178
Andrew Victorad48ce72008-04-16 20:43:49 +0100179static void at91sam926x_pit_suspend(void)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100180{
181 /* Disable timer */
182 at91_sys_write(AT91_PIT_MR, 0);
183}
Andrew Victor1a0ed732006-12-01 09:04:47 +0100184
185struct sys_timer at91sam926x_timer = {
Andrew Victorad48ce72008-04-16 20:43:49 +0100186 .init = at91sam926x_pit_init,
187 .suspend = at91sam926x_pit_suspend,
188 .resume = at91sam926x_pit_reset,
Andrew Victor1a0ed732006-12-01 09:04:47 +0100189};