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Andrew Victor1e6c9c22006-01-10 16:59:27 +00001/*
Guennadi Liakhovetskifa3218d2008-01-29 15:43:13 +01002 * include/linux/atmel_serial.h
Andrew Victor1e6c9c22006-01-10 16:59:27 +00003 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * USART registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
Haavard Skinnemoen7192f922006-10-04 16:02:05 +020016#ifndef ATMEL_SERIAL_H
17#define ATMEL_SERIAL_H
Andrew Victor1e6c9c22006-01-10 16:59:27 +000018
Cyrille Pitchen3fad3862015-07-02 15:18:10 +020019#define ATMEL_US_CR 0x00 /* Control Register */
20#define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */
21#define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */
22#define ATMEL_US_RXEN BIT(4) /* Receiver Enable */
23#define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */
24#define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */
25#define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */
26#define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */
27#define ATMEL_US_STTBRK BIT(9) /* Start Break */
28#define ATMEL_US_STPBRK BIT(10) /* Stop Break */
29#define ATMEL_US_STTTO BIT(11) /* Start Time-out */
30#define ATMEL_US_SENDA BIT(12) /* Send Address */
31#define ATMEL_US_RSTIT BIT(13) /* Reset Iterations */
32#define ATMEL_US_RSTNACK BIT(14) /* Reset Non Acknowledge */
33#define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
34#define ATMEL_US_DTREN BIT(16) /* Data Terminal Ready Enable */
35#define ATMEL_US_DTRDIS BIT(17) /* Data Terminal Ready Disable */
36#define ATMEL_US_RTSEN BIT(18) /* Request To Send Enable */
37#define ATMEL_US_RTSDIS BIT(19) /* Request To Send Disable */
Cyrille Pitchenb5199d42015-07-02 15:18:12 +020038#define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */
39#define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */
40#define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */
41#define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */
42#define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */
Andrew Victor1e6c9c22006-01-10 16:59:27 +000043
Cyrille Pitchen3fad3862015-07-02 15:18:10 +020044#define ATMEL_US_MR 0x04 /* Mode Register */
45#define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */
46#define ATMEL_US_USMODE_NORMAL 0
47#define ATMEL_US_USMODE_RS485 1
48#define ATMEL_US_USMODE_HWHS 2
49#define ATMEL_US_USMODE_MODEM 3
50#define ATMEL_US_USMODE_ISO7816_T0 4
51#define ATMEL_US_USMODE_ISO7816_T1 6
52#define ATMEL_US_USMODE_IRDA 8
53#define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */
54#define ATMEL_US_USCLKS_MCK (0 << 4)
55#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
56#define ATMEL_US_USCLKS_SCK (3 << 4)
57#define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */
58#define ATMEL_US_CHRL_5 (0 << 6)
59#define ATMEL_US_CHRL_6 (1 << 6)
60#define ATMEL_US_CHRL_7 (2 << 6)
61#define ATMEL_US_CHRL_8 (3 << 6)
62#define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */
63#define ATMEL_US_PAR GENMASK(11, 9) /* Parity Type */
64#define ATMEL_US_PAR_EVEN (0 << 9)
65#define ATMEL_US_PAR_ODD (1 << 9)
66#define ATMEL_US_PAR_SPACE (2 << 9)
67#define ATMEL_US_PAR_MARK (3 << 9)
68#define ATMEL_US_PAR_NONE (4 << 9)
69#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
70#define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */
71#define ATMEL_US_NBSTOP_1 (0 << 12)
72#define ATMEL_US_NBSTOP_1_5 (1 << 12)
73#define ATMEL_US_NBSTOP_2 (2 << 12)
74#define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */
75#define ATMEL_US_CHMODE_NORMAL (0 << 14)
76#define ATMEL_US_CHMODE_ECHO (1 << 14)
77#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
78#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
79#define ATMEL_US_MSBF BIT(16) /* Bit Order */
80#define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
81#define ATMEL_US_CLKO BIT(18) /* Clock Output Select */
82#define ATMEL_US_OVER BIT(19) /* Oversampling Mode */
83#define ATMEL_US_INACK BIT(20) /* Inhibit Non Acknowledge */
84#define ATMEL_US_DSNACK BIT(21) /* Disable Successive NACK */
85#define ATMEL_US_MAX_ITER GENMASK(26, 24) /* Max Iterations */
86#define ATMEL_US_FILTER BIT(28) /* Infrared Receive Line Filter */
Andrew Victor1e6c9c22006-01-10 16:59:27 +000087
Cyrille Pitchen3fad3862015-07-02 15:18:10 +020088#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
89#define ATMEL_US_RXRDY BIT(0) /* Receiver Ready */
90#define ATMEL_US_TXRDY BIT(1) /* Transmitter Ready */
91#define ATMEL_US_RXBRK BIT(2) /* Break Received / End of Break */
92#define ATMEL_US_ENDRX BIT(3) /* End of Receiver Transfer */
93#define ATMEL_US_ENDTX BIT(4) /* End of Transmitter Transfer */
94#define ATMEL_US_OVRE BIT(5) /* Overrun Error */
95#define ATMEL_US_FRAME BIT(6) /* Framing Error */
96#define ATMEL_US_PARE BIT(7) /* Parity Error */
97#define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */
98#define ATMEL_US_TXEMPTY BIT(9) /* Transmitter Empty */
99#define ATMEL_US_ITERATION BIT(10) /* Max number of Repetitions Reached */
100#define ATMEL_US_TXBUFE BIT(11) /* Transmission Buffer Empty */
101#define ATMEL_US_RXBUFF BIT(12) /* Reception Buffer Full */
102#define ATMEL_US_NACK BIT(13) /* Non Acknowledge */
103#define ATMEL_US_RIIC BIT(16) /* Ring Indicator Input Change */
104#define ATMEL_US_DSRIC BIT(17) /* Data Set Ready Input Change */
105#define ATMEL_US_DCDIC BIT(18) /* Data Carrier Detect Input Change */
106#define ATMEL_US_CTSIC BIT(19) /* Clear to Send Input Change */
107#define ATMEL_US_RI BIT(20) /* RI */
108#define ATMEL_US_DSR BIT(21) /* DSR */
109#define ATMEL_US_DCD BIT(22) /* DCD */
110#define ATMEL_US_CTS BIT(23) /* CTS */
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000111
Cyrille Pitchen3fad3862015-07-02 15:18:10 +0200112#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
113#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
114#define ATMEL_US_CSR 0x14 /* Channel Status Register */
115#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
116#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
117#define ATMEL_US_SYNH BIT(15) /* Transmit/Receive Sync */
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000118
Cyrille Pitchen3fad3862015-07-02 15:18:10 +0200119#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
120#define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000121
Cyrille Pitchen3fad3862015-07-02 15:18:10 +0200122#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
123#define ATMEL_US_TO GENMASK(15, 0) /* Time-out Value */
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000124
Cyrille Pitchen3fad3862015-07-02 15:18:10 +0200125#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
126#define ATMEL_US_TG GENMASK(7, 0) /* Timeguard Value */
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000127
Cyrille Pitchen3fad3862015-07-02 15:18:10 +0200128#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
129#define ATMEL_US_NER 0x44 /* Number of Errors Register */
130#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000131
Cyrille Pitchenb5199d42015-07-02 15:18:12 +0200132#define ATMEL_US_CMPR 0x90 /* Comparaison Register */
133#define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */
134#define ATMEL_US_TXRDYM(data) (((data) & 0x3) << 0) /* TX Ready Mode */
135#define ATMEL_US_RXRDYM(data) (((data) & 0x3) << 4) /* RX Ready Mode */
136#define ATMEL_US_ONE_DATA 0x0
137#define ATMEL_US_TWO_DATA 0x1
138#define ATMEL_US_FOUR_DATA 0x2
139#define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */
140#define ATMEL_US_TXFTHRES(thr) (((thr) & 0x3f) << 8) /* TX FIFO Threshold */
141#define ATMEL_US_RXFTHRES(thr) (((thr) & 0x3f) << 16) /* RX FIFO Threshold */
142#define ATMEL_US_RXFTHRES2(thr) (((thr) & 0x3f) << 24) /* RX FIFO Threshold2 */
143
144#define ATMEL_US_FLR 0xa4 /* FIFO Level Register */
145#define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO Level */
146#define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO Level */
147
148#define ATMEL_US_FIER 0xa8 /* FIFO Interrupt Enable Register */
149#define ATMEL_US_FIDR 0xac /* FIFO Interrupt Disable Register */
150#define ATMEL_US_FIMR 0xb0 /* FIFO Interrupt Mask Register */
151#define ATMEL_US_FESR 0xb4 /* FIFO Event Status Register */
152#define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */
153#define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */
154#define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag */
155#define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */
156#define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */
157#define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag */
158#define ATMEL_US_TXFPTEF BIT(6) /* Transmit FIFO Pointer Error Flag */
159#define ATMEL_US_RXFPTEF BIT(7) /* Receive FIFO Pointer Error Flag */
160#define ATMEL_US_TXFLOCK BIT(8) /* Transmit FIFO Lock (FESR only) */
161#define ATMEL_US_RXFTHF2 BIT(9) /* Receive FIFO Threshold Flag 2 */
162
Cyrille Pitchen3fad3862015-07-02 15:18:10 +0200163#define ATMEL_US_NAME 0xf0 /* Ip Name */
164#define ATMEL_US_VERSION 0xfc /* Ip Version */
Elen Song055560b2013-07-22 16:30:29 +0800165
Andrew Victor1e6c9c22006-01-10 16:59:27 +0000166#endif