blob: d28258652e2532a5f0cdf10084df6f4949178bf2 [file] [log] [blame]
Pratap Nirujogi6e759912018-01-17 17:51:17 +05301/* Copyright (c) 2009-2012, 2014-2016, 2018, The Linux Foundation.
2 * All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14#ifndef __UAPI_MSM_CAMERA_H
15#define __UAPI_MSM_CAMERA_H
16
17#include <linux/videodev2.h>
18#include <linux/types.h>
19#include <linux/ioctl.h>
20
21#include <linux/msm_ion.h>
22
23#define BIT(nr) (1UL << (nr))
24
25#define MSM_CAM_IOCTL_MAGIC 'm'
26
27#define MAX_SERVER_PAYLOAD_LENGTH 8192
28
29#define MSM_CAM_IOCTL_GET_SENSOR_INFO \
30 _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *)
31
32#define MSM_CAM_IOCTL_REGISTER_PMEM \
33 _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *)
34
35#define MSM_CAM_IOCTL_UNREGISTER_PMEM \
36 _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned int)
37
38#define MSM_CAM_IOCTL_CTRL_COMMAND \
39 _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *)
40
41#define MSM_CAM_IOCTL_CONFIG_VFE \
42 _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *)
43
44#define MSM_CAM_IOCTL_GET_STATS \
45 _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *)
46
47#define MSM_CAM_IOCTL_GETFRAME \
48 _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *)
49
50#define MSM_CAM_IOCTL_ENABLE_VFE \
51 _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *)
52
53#define MSM_CAM_IOCTL_CTRL_CMD_DONE \
54 _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *)
55
56#define MSM_CAM_IOCTL_CONFIG_CMD \
57 _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *)
58
59#define MSM_CAM_IOCTL_DISABLE_VFE \
60 _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *)
61
62#define MSM_CAM_IOCTL_PAD_REG_RESET2 \
63 _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *)
64
65#define MSM_CAM_IOCTL_VFE_APPS_RESET \
66 _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *)
67
68#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \
69 _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *)
70
71#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \
72 _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *)
73
74#define MSM_CAM_IOCTL_AXI_CONFIG \
75 _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *)
76
77#define MSM_CAM_IOCTL_GET_PICTURE \
78 _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *)
79
80#define MSM_CAM_IOCTL_SET_CROP \
81 _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *)
82
83#define MSM_CAM_IOCTL_PICT_PP \
84 _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *)
85
86#define MSM_CAM_IOCTL_PICT_PP_DONE \
87 _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *)
88
89#define MSM_CAM_IOCTL_SENSOR_IO_CFG \
90 _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *)
91
92#define MSM_CAM_IOCTL_FLASH_LED_CFG \
93 _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned int *)
94
95#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \
96 _IO(MSM_CAM_IOCTL_MAGIC, 23)
97
98#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \
99 _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *)
100
101#define MSM_CAM_IOCTL_AF_CTRL \
102 _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *)
103
104#define MSM_CAM_IOCTL_AF_CTRL_DONE \
105 _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *)
106
107#define MSM_CAM_IOCTL_CONFIG_VPE \
108 _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *)
109
110#define MSM_CAM_IOCTL_AXI_VPE_CONFIG \
111 _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *)
112
113#define MSM_CAM_IOCTL_STROBE_FLASH_CFG \
114 _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *)
115
116#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE \
117 _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *)
118
119#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE \
120 _IO(MSM_CAM_IOCTL_MAGIC, 31)
121
122#define MSM_CAM_IOCTL_FLASH_CTRL \
123 _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *)
124
125#define MSM_CAM_IOCTL_ERROR_CONFIG \
126 _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *)
127
128#define MSM_CAM_IOCTL_ABORT_CAPTURE \
129 _IO(MSM_CAM_IOCTL_MAGIC, 34)
130
131#define MSM_CAM_IOCTL_SET_FD_ROI \
132 _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *)
133
134#define MSM_CAM_IOCTL_GET_CAMERA_INFO \
135 _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *)
136
137#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME \
138 _IO(MSM_CAM_IOCTL_MAGIC, 37)
139
140#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER \
141 _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *)
142
143#define MSM_CAM_IOCTL_PUT_ST_FRAME \
144 _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *)
145
146#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY \
147 _IOW(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event_and_payload)
148
149#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO \
150 _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *)
151
152#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG \
153 _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *)
154
155#define MSM_CAM_IOCTL_MCTL_POST_PROC \
156 _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *)
157
158#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME \
159 _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *)
160
161#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME \
162 _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *)
163
164#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE \
165 _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *)
166
167#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL \
168 _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control)
169
170#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL \
171 _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl)
172
173#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME \
174 _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *)
175
176#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE \
177 _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *)
178
179#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE \
180 _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *)
181
182#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO \
183 _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *)
184
185#define MSM_CAM_IOCTL_EEPROM_IO_CFG \
186 _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *)
187
188#define MSM_CAM_IOCTL_ISPIF_IO_CFG \
189 _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *)
190
191#define MSM_CAM_IOCTL_STATS_REQBUF \
192 _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *)
193
194#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF \
195 _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *)
196
197#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ \
198 _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *)
199
200#define MSM_CAM_IOCTL_SET_MCTL_SDEV \
201 _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *)
202
203#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV \
204 _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *)
205
206#define MSM_CAM_IOCTL_GET_INST_HANDLE \
207 _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *)
208
209#define MSM_CAM_IOCTL_STATS_UNREG_BUF \
210 _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *)
211
212#define MSM_CAM_IOCTL_CSIC_IO_CFG \
213 _IOWR(MSM_CAM_IOCTL_MAGIC, 62, struct csic_cfg_data *)
214
215#define MSM_CAM_IOCTL_CSID_IO_CFG \
216 _IOWR(MSM_CAM_IOCTL_MAGIC, 63, struct csid_cfg_data *)
217
218#define MSM_CAM_IOCTL_CSIPHY_IO_CFG \
219 _IOR(MSM_CAM_IOCTL_MAGIC, 64, struct csiphy_cfg_data *)
220
221#define MSM_CAM_IOCTL_OEM \
222 _IOW(MSM_CAM_IOCTL_MAGIC, 65, struct sensor_cfg_data *)
223
224#define MSM_CAM_IOCTL_AXI_INIT \
225 _IOWR(MSM_CAM_IOCTL_MAGIC, 66, uint8_t *)
226
227#define MSM_CAM_IOCTL_AXI_RELEASE \
228 _IO(MSM_CAM_IOCTL_MAGIC, 67)
229
230struct v4l2_event_and_payload {
231 struct v4l2_event evt;
232 uint32_t payload_length;
233 uint32_t transaction_id;
234 void *payload;
235};
236
237struct msm_stats_reqbuf {
238 int num_buf; /* how many buffers requested */
239 int stats_type; /* stats type */
240};
241
242struct msm_stats_flush_bufq {
243 int stats_type; /* enum msm_stats_enum_type */
244};
245
246struct msm_mctl_pp_cmd {
247 int32_t id;
248 uint16_t length;
249 void *value;
250};
251
252struct msm_mctl_post_proc_cmd {
253 int32_t type;
254 struct msm_mctl_pp_cmd cmd;
255};
256
257#define MSM_CAMERA_LED_OFF 0
258#define MSM_CAMERA_LED_LOW 1
259#define MSM_CAMERA_LED_HIGH 2
260#define MSM_CAMERA_LED_INIT 3
261#define MSM_CAMERA_LED_RELEASE 4
262
263#define MSM_CAMERA_STROBE_FLASH_NONE 0
264#define MSM_CAMERA_STROBE_FLASH_XENON 1
265
266#define MSM_MAX_CAMERA_SENSORS 5
267#define MAX_SENSOR_NAME 32
268#define MAX_CAM_NAME_SIZE 32
269#define MAX_ACT_MOD_NAME_SIZE 32
270#define MAX_ACT_NAME_SIZE 32
271#define NUM_ACTUATOR_DIR 2
272#define MAX_ACTUATOR_SCENARIO 8
273#define MAX_ACTUATOR_REGION 5
274#define MAX_ACTUATOR_INIT_SET 12
275#define MAX_ACTUATOR_TYPE_SIZE 32
276#define MAX_ACTUATOR_REG_TBL_SIZE 8
277
278
279#define MSM_MAX_CAMERA_CONFIGS 2
280
281#define PP_SNAP 0x01
282#define PP_RAW_SNAP ((0x01)<<1)
283#define PP_PREV ((0x01)<<2)
284#define PP_THUMB ((0x01)<<3)
285#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB)
286
287#define MSM_CAM_CTRL_CMD_DONE 0
288#define MSM_CAM_SENSOR_VFE_CMD 1
289
290/* Should be same as VIDEO_MAX_PLANES in videodev2.h */
291#define MAX_PLANES 8
292
293/*****************************************************
294 * structure
295 *****************************************************/
296
297/* define five type of structures for userspace <==> kernel
298 * space communication:
299 * command 1 - 2 are from userspace ==> kernel
300 * command 3 - 4 are from kernel ==> userspace
301 *
302 * 1. control command: control command(from control thread),
303 * control status (from config thread);
304 */
305struct msm_ctrl_cmd {
306 uint16_t type;
307 uint16_t length;
308 void *value;
309 uint16_t status;
310 uint32_t timeout_ms;
311 int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */
312 int vnode_id; /* video dev id. Can we overload resp_fd? */
313 int queue_idx;
314 uint32_t evt_id;
315 uint32_t stream_type; /* used to pass value to qcamera server */
316 int config_ident; /*used as identifier for config node*/
317};
318
319struct msm_cam_evt_msg {
320 unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */
321 unsigned short msg_id;
322 unsigned int len; /* size in, number of bytes out */
323 uint32_t frame_id;
324 void *data;
325 struct timespec timestamp;
326};
327
328struct msm_pp_frame_sp {
329 /* phy addr of the buffer */
330 unsigned long phy_addr;
331 uint32_t y_off;
332 uint32_t cbcr_off;
333 /* buffer length */
334 uint32_t length;
335 int32_t fd;
336 uint32_t addr_offset;
337 /* mapped addr */
338 unsigned long vaddr;
339};
340
341struct msm_pp_frame_mp {
342 /* phy addr of the plane */
343 unsigned long phy_addr;
344 /* offset of plane data */
345 uint32_t data_offset;
346 /* plane length */
347 uint32_t length;
348 int32_t fd;
349 uint32_t addr_offset;
350 /* mapped addr */
351 unsigned long vaddr;
352};
353
354struct msm_pp_frame {
355 uint32_t handle; /* stores vb cookie */
356 uint32_t frame_id;
357 unsigned short buf_idx;
358 int path;
359 unsigned short image_type;
360 unsigned short num_planes; /* 1 for sp */
361 struct timeval timestamp;
362 union {
363 struct msm_pp_frame_sp sp;
364 struct msm_pp_frame_mp mp[MAX_PLANES];
365 };
366 int node_type;
367 uint32_t inst_handle;
368};
369
370struct msm_pp_crop {
371 uint32_t src_x;
372 uint32_t src_y;
373 uint32_t src_w;
374 uint32_t src_h;
375 uint32_t dst_x;
376 uint32_t dst_y;
377 uint32_t dst_w;
378 uint32_t dst_h;
379 uint8_t update_flag;
380};
381
382struct msm_mctl_pp_frame_cmd {
383 uint32_t cookie;
384 uint8_t vpe_output_action;
385 struct msm_pp_frame src_frame;
386 struct msm_pp_frame dest_frame;
387 struct msm_pp_crop crop;
388 int path;
389};
390
391struct msm_cam_evt_divert_frame {
392 unsigned short image_mode;
393 unsigned short op_mode;
394 unsigned short inst_idx;
395 unsigned short node_idx;
396 struct msm_pp_frame frame;
397 int do_pp;
398};
399
400struct msm_mctl_pp_cmd_ack_event {
401 uint32_t cmd; /* VPE_CMD_ZOOM? */
402 int status; /* 0 done, < 0 err */
403 uint32_t cookie; /* daemon's cookie */
404};
405
406struct msm_mctl_pp_event_info {
407 int32_t event;
408 union {
409 struct msm_mctl_pp_cmd_ack_event ack;
410 };
411};
412
413struct msm_isp_event_ctrl {
414 unsigned short resptype;
415 union {
416 struct msm_cam_evt_msg isp_msg;
417 struct msm_ctrl_cmd ctrl;
418 struct msm_cam_evt_divert_frame div_frame;
419 struct msm_mctl_pp_event_info pp_event_info;
420 } isp_data;
421};
422
423#define MSM_CAM_RESP_CTRL 0
424#define MSM_CAM_RESP_STAT_EVT_MSG 1
425#define MSM_CAM_RESP_STEREO_OP_1 2
426#define MSM_CAM_RESP_STEREO_OP_2 3
427#define MSM_CAM_RESP_V4L2 4
428#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5
429#define MSM_CAM_RESP_DONE_EVENT 6
430#define MSM_CAM_RESP_MCTL_PP_EVENT 7
431#define MSM_CAM_RESP_MAX 8
432
433#define MSM_CAM_APP_NOTIFY_EVENT 0
434#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1
435
436/* this one is used to send ctrl/status up to config thread */
437
438struct msm_stats_event_ctrl {
439 /* 0 - ctrl_cmd from control thread,
440 * 1 - stats/event kernel,
441 * 2 - V4L control or read request
442 */
443 int resptype;
444 int timeout_ms;
445 struct msm_ctrl_cmd ctrl_cmd;
446 /* struct vfe_event_t stats_event; */
447 struct msm_cam_evt_msg stats_event;
448};
449
450/* 2. config command: config command(from config thread); */
451struct msm_camera_cfg_cmd {
452 /* what to config:
453 * 1 - sensor config, 2 - vfe config
454 */
455 uint16_t cfg_type;
456
457 /* sensor config type */
458 uint16_t cmd_type;
459 uint16_t queue;
460 uint16_t length;
461 void *value;
462};
463
464#define CMD_GENERAL 0
465#define CMD_AXI_CFG_OUT1 1
466#define CMD_AXI_CFG_SNAP_O1_AND_O2 2
467#define CMD_AXI_CFG_OUT2 3
468#define CMD_PICT_T_AXI_CFG 4
469#define CMD_PICT_M_AXI_CFG 5
470#define CMD_RAW_PICT_AXI_CFG 6
471
472#define CMD_FRAME_BUF_RELEASE 7
473#define CMD_PREV_BUF_CFG 8
474#define CMD_SNAP_BUF_RELEASE 9
475#define CMD_SNAP_BUF_CFG 10
476#define CMD_STATS_DISABLE 11
477#define CMD_STATS_AEC_AWB_ENABLE 12
478#define CMD_STATS_AF_ENABLE 13
479#define CMD_STATS_AEC_ENABLE 14
480#define CMD_STATS_AWB_ENABLE 15
481#define CMD_STATS_ENABLE 16
482
483#define CMD_STATS_AXI_CFG 17
484#define CMD_STATS_AEC_AXI_CFG 18
485#define CMD_STATS_AF_AXI_CFG 19
486#define CMD_STATS_AWB_AXI_CFG 20
487#define CMD_STATS_RS_AXI_CFG 21
488#define CMD_STATS_CS_AXI_CFG 22
489#define CMD_STATS_IHIST_AXI_CFG 23
490#define CMD_STATS_SKIN_AXI_CFG 24
491
492#define CMD_STATS_BUF_RELEASE 25
493#define CMD_STATS_AEC_BUF_RELEASE 26
494#define CMD_STATS_AF_BUF_RELEASE 27
495#define CMD_STATS_AWB_BUF_RELEASE 28
496#define CMD_STATS_RS_BUF_RELEASE 29
497#define CMD_STATS_CS_BUF_RELEASE 30
498#define CMD_STATS_IHIST_BUF_RELEASE 31
499#define CMD_STATS_SKIN_BUF_RELEASE 32
500
501#define UPDATE_STATS_INVALID 33
502#define CMD_AXI_CFG_SNAP_GEMINI 34
503#define CMD_AXI_CFG_SNAP 35
504#define CMD_AXI_CFG_PREVIEW 36
505#define CMD_AXI_CFG_VIDEO 37
506
507#define CMD_STATS_IHIST_ENABLE 38
508#define CMD_STATS_RS_ENABLE 39
509#define CMD_STATS_CS_ENABLE 40
510#define CMD_VPE 41
511#define CMD_AXI_CFG_VPE 42
512#define CMD_AXI_CFG_ZSL 43
513#define CMD_AXI_CFG_SNAP_VPE 44
514#define CMD_AXI_CFG_SNAP_THUMB_VPE 45
515
516#define CMD_CONFIG_PING_ADDR 46
517#define CMD_CONFIG_PONG_ADDR 47
518#define CMD_CONFIG_FREE_BUF_ADDR 48
519#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49
520#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50
521#define CMD_VFE_BUFFER_RELEASE 51
522#define CMD_VFE_PROCESS_IRQ 52
523#define CMD_STATS_BG_ENABLE 53
524#define CMD_STATS_BF_ENABLE 54
525#define CMD_STATS_BHIST_ENABLE 55
526#define CMD_STATS_BG_BUF_RELEASE 56
527#define CMD_STATS_BF_BUF_RELEASE 57
528#define CMD_STATS_BHIST_BUF_RELEASE 58
529#define CMD_VFE_PIX_SOF_COUNT_UPDATE 59
530#define CMD_VFE_COUNT_PIX_SOF_ENABLE 60
531#define CMD_STATS_BE_ENABLE 61
532#define CMD_STATS_BE_BUF_RELEASE 62
533
534#define CMD_AXI_CFG_PRIM BIT(8)
535#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9)
536#define CMD_AXI_CFG_SEC BIT(10)
537#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11)
538#define CMD_AXI_CFG_TERT1 BIT(12)
539#define CMD_AXI_CFG_TERT2 BIT(13)
540
541#define CMD_AXI_START 0xE1
542#define CMD_AXI_STOP 0xE2
543#define CMD_AXI_RESET 0xE3
544#define CMD_AXI_ABORT 0xE4
545
546
547
548#define AXI_CMD_PREVIEW BIT(0)
549#define AXI_CMD_CAPTURE BIT(1)
550#define AXI_CMD_RECORD BIT(2)
551#define AXI_CMD_ZSL BIT(3)
552#define AXI_CMD_RAW_CAPTURE BIT(4)
553#define AXI_CMD_LIVESHOT BIT(5)
554
555/* vfe config command: config command(from config thread)*/
556struct msm_vfe_cfg_cmd {
557 int cmd_type;
558 uint16_t length;
559 void *value;
560};
561
562struct msm_vpe_cfg_cmd {
563 int cmd_type;
564 uint16_t length;
565 void *value;
566};
567
568#define MAX_CAMERA_ENABLE_NAME_LEN 32
569struct camera_enable_cmd {
570 char name[MAX_CAMERA_ENABLE_NAME_LEN];
571};
572
573#define MSM_PMEM_OUTPUT1 0
574#define MSM_PMEM_OUTPUT2 1
575#define MSM_PMEM_OUTPUT1_OUTPUT2 2
576#define MSM_PMEM_THUMBNAIL 3
577#define MSM_PMEM_MAINIMG 4
578#define MSM_PMEM_RAW_MAINIMG 5
579#define MSM_PMEM_AEC_AWB 6
580#define MSM_PMEM_AF 7
581#define MSM_PMEM_AEC 8
582#define MSM_PMEM_AWB 9
583#define MSM_PMEM_RS 10
584#define MSM_PMEM_CS 11
585#define MSM_PMEM_IHIST 12
586#define MSM_PMEM_SKIN 13
587#define MSM_PMEM_VIDEO 14
588#define MSM_PMEM_PREVIEW 15
589#define MSM_PMEM_VIDEO_VPE 16
590#define MSM_PMEM_C2D 17
591#define MSM_PMEM_MAINIMG_VPE 18
592#define MSM_PMEM_THUMBNAIL_VPE 19
593#define MSM_PMEM_BAYER_GRID 20
594#define MSM_PMEM_BAYER_FOCUS 21
595#define MSM_PMEM_BAYER_HIST 22
596#define MSM_PMEM_BAYER_EXPOSURE 23
597#define MSM_PMEM_MAX 24
598
599#define STAT_AEAW 0
600#define STAT_AEC 1
601#define STAT_AF 2
602#define STAT_AWB 3
603#define STAT_RS 4
604#define STAT_CS 5
605#define STAT_IHIST 6
606#define STAT_SKIN 7
607#define STAT_BG 8
608#define STAT_BF 9
609#define STAT_BE 10
610#define STAT_BHIST 11
611#define STAT_MAX 12
612
613#define FRAME_PREVIEW_OUTPUT1 0
614#define FRAME_PREVIEW_OUTPUT2 1
615#define FRAME_SNAPSHOT 2
616#define FRAME_THUMBNAIL 3
617#define FRAME_RAW_SNAPSHOT 4
618#define FRAME_MAX 5
619
620enum msm_stats_enum_type {
621 MSM_STATS_TYPE_AEC, /* legacy based AEC */
622 MSM_STATS_TYPE_AF, /* legacy based AF */
623 MSM_STATS_TYPE_AWB, /* legacy based AWB */
624 MSM_STATS_TYPE_RS, /* legacy based RS */
625 MSM_STATS_TYPE_CS, /* legacy based CS */
626 MSM_STATS_TYPE_IHIST, /* legacy based HIST */
627 MSM_STATS_TYPE_SKIN, /* legacy based SKIN */
628 MSM_STATS_TYPE_BG, /* Bayer Grids */
629 MSM_STATS_TYPE_BF, /* Bayer Focus */
630 MSM_STATS_TYPE_BE, /* Bayer Exposure*/
631 MSM_STATS_TYPE_BHIST, /* Bayer Hist */
632 MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/
633 MSM_STATS_TYPE_COMP, /* Composite stats */
634 MSM_STATS_TYPE_MAX /* MAX */
635};
636
637struct msm_stats_buf_info {
638 int type; /* msm_stats_enum_type */
639 int fd;
640 void *vaddr;
641 uint32_t offset;
642 uint32_t len;
643 uint32_t y_off;
644 uint32_t cbcr_off;
645 uint32_t planar0_off;
646 uint32_t planar1_off;
647 uint32_t planar2_off;
648 uint8_t active;
649 int buf_idx;
650};
651
652struct msm_pmem_info {
653 int type;
654 int fd;
655 void *vaddr;
656 uint32_t offset;
657 uint32_t len;
658 uint32_t y_off;
659 uint32_t cbcr_off;
660 uint32_t planar0_off;
661 uint32_t planar1_off;
662 uint32_t planar2_off;
663 uint8_t active;
664};
665
666struct outputCfg {
667 uint32_t height;
668 uint32_t width;
669
670 uint32_t window_height_firstline;
671 uint32_t window_height_lastline;
672};
673
674#define VIDEO_NODE 0
675#define MCTL_NODE 1
676
677#define OUTPUT_1 0
678#define OUTPUT_2 1
679#define OUTPUT_1_AND_2 2 /* snapshot only */
680#define OUTPUT_1_AND_3 3 /* video */
681#define CAMIF_TO_AXI_VIA_OUTPUT_2 4
682#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5
683#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6
684#define OUTPUT_1_2_AND_3 7
685#define OUTPUT_ALL_CHNLS 8
686#define OUTPUT_VIDEO_ALL_CHNLS 9
687#define OUTPUT_ZSL_ALL_CHNLS 10
688#define LAST_AXI_OUTPUT_MODE_ENUM OUTPUT_ZSL_ALL_CHNLS
689
690#define OUTPUT_PRIM BIT(8)
691#define OUTPUT_PRIM_ALL_CHNLS BIT(9)
692#define OUTPUT_SEC BIT(10)
693#define OUTPUT_SEC_ALL_CHNLS BIT(11)
694#define OUTPUT_TERT1 BIT(12)
695#define OUTPUT_TERT2 BIT(13)
696
697
698
699#define MSM_FRAME_PREV_1 0
700#define MSM_FRAME_PREV_2 1
701#define MSM_FRAME_ENC 2
702
703#define OUTPUT_TYPE_P BIT(0)
704#define OUTPUT_TYPE_T BIT(1)
705#define OUTPUT_TYPE_S BIT(2)
706#define OUTPUT_TYPE_V BIT(3)
707#define OUTPUT_TYPE_L BIT(4)
708#define OUTPUT_TYPE_ST_L BIT(5)
709#define OUTPUT_TYPE_ST_R BIT(6)
710#define OUTPUT_TYPE_ST_D BIT(7)
711#define OUTPUT_TYPE_R BIT(8)
712#define OUTPUT_TYPE_R1 BIT(9)
713#define OUTPUT_TYPE_SAEC BIT(10)
714#define OUTPUT_TYPE_SAFC BIT(11)
715#define OUTPUT_TYPE_SAWB BIT(12)
716#define OUTPUT_TYPE_IHST BIT(13)
717#define OUTPUT_TYPE_CSTA BIT(14)
718
719struct fd_roi_info {
720 void *info;
721 int info_len;
722};
723
724struct msm_mem_map_info {
725 uint32_t cookie;
726 uint32_t length;
727 uint32_t mem_type;
728};
729
730#define MSM_MEM_MMAP 0
731#define MSM_MEM_USERPTR 1
732#define MSM_PLANE_MAX 8
733#define MSM_PLANE_Y 0
734#define MSM_PLANE_UV 1
735
736struct msm_frame {
737 struct timespec ts;
738 int path;
739 int type;
740 unsigned long buffer;
741 uint32_t phy_offset;
742 uint32_t y_off;
743 uint32_t cbcr_off;
744 uint32_t planar0_off;
745 uint32_t planar1_off;
746 uint32_t planar2_off;
747 int fd;
748
749 void *cropinfo;
750 int croplen;
751 uint32_t error_code;
752 struct fd_roi_info roi_info;
753 uint32_t frame_id;
754 int stcam_quality_ind;
755 uint32_t stcam_conv_value;
756
757 struct ion_allocation_data ion_alloc;
758 struct ion_fd_data fd_data;
759 int ion_dev_fd;
760};
761
762enum msm_st_frame_packing {
763 SIDE_BY_SIDE_HALF,
764 SIDE_BY_SIDE_FULL,
765 TOP_DOWN_HALF,
766 TOP_DOWN_FULL,
767};
768
769struct msm_st_crop {
770 uint32_t in_w;
771 uint32_t in_h;
772 uint32_t out_w;
773 uint32_t out_h;
774};
775
776struct msm_st_half {
777 uint32_t buf_p0_off;
778 uint32_t buf_p1_off;
779 uint32_t buf_p0_stride;
780 uint32_t buf_p1_stride;
781 uint32_t pix_x_off;
782 uint32_t pix_y_off;
783 struct msm_st_crop stCropInfo;
784};
785
786struct msm_st_frame {
787 struct msm_frame buf_info;
788 int type;
789 enum msm_st_frame_packing packing;
790 struct msm_st_half L;
791 struct msm_st_half R;
792 int frame_id;
793};
794
795#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1)
796
797struct stats_buff {
798 unsigned long buff;
799 int fd;
800};
801
802struct msm_stats_buf {
803 uint8_t awb_ymin;
804 struct stats_buff aec;
805 struct stats_buff awb;
806 struct stats_buff af;
807 struct stats_buff be;
808 struct stats_buff ihist;
809 struct stats_buff rs;
810 struct stats_buff cs;
811 struct stats_buff skin;
812 int type;
813 uint32_t status_bits;
814 unsigned long buffer;
815 int fd;
816 int length;
817 struct ion_handle *handle;
818 uint32_t frame_id;
819 int buf_idx;
820};
821#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0
822/* video capture mode in VIDIOC_S_PARM */
823#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW \
824 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1)
825/* extendedmode for video recording in VIDIOC_S_PARM */
826#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO \
827 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2)
828/* extendedmode for the full size main image in VIDIOC_S_PARM */
829#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3)
830/* extendedmode for the thumb nail image in VIDIOC_S_PARM */
831#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL \
832 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4)
833/* ISP_PIX_OUTPUT1: no pp, directly send output1 buf to user */
834#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT1 \
835 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5)
836/* ISP_PIX_OUTPUT2: no pp, directly send output2 buf to user */
837#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT2 \
838 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+6)
839/* raw image type */
840#define MSM_V4L2_EXT_CAPTURE_MODE_RAW \
841 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+7)
842/* RDI dump */
843#define MSM_V4L2_EXT_CAPTURE_MODE_RDI \
844 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+8)
845/* RDI dump 1 */
846#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 \
847 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+9)
848/* RDI dump 2 */
849#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 \
850 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+10)
851#define MSM_V4L2_EXT_CAPTURE_MODE_AEC \
852 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+11)
853#define MSM_V4L2_EXT_CAPTURE_MODE_AWB \
854 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+12)
855#define MSM_V4L2_EXT_CAPTURE_MODE_AF \
856 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+13)
857#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST \
858 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+14)
859#define MSM_V4L2_EXT_CAPTURE_MODE_CS \
860 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+15)
861#define MSM_V4L2_EXT_CAPTURE_MODE_RS \
862 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+16)
863#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA \
864 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+17)
865#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT \
866 (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18)
867#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+19)
868
869
870#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE
871#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1)
872#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE+2)
873#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE+3)
874#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE+4)
875#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE+5)
876#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE+6)
877#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE+7)
878#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE+8)
879#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE+9)
880#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE+10)
881#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE+11)
882#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE+12)
883#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE+13)
884#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE+14)
885#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE+15)
886#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE+16)
887#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE+17)
888#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE+18)
889#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO
890
891/* camera operation mode for video recording - two frame output queues */
892#define MSM_V4L2_CAM_OP_DEFAULT 0
893/* camera operation mode for video recording - two frame output queues */
894#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT+1)
895/* camera operation mode for video recording - two frame output queues */
896#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT+2)
897/* camera operation mode for standard shapshot - two frame output queues */
898#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+3)
899/* camera operation mode for zsl shapshot - three output queues */
900#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4)
901/* camera operation mode for raw snapshot - one frame output queue */
902#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5)
903/* camera operation mode for jpeg snapshot - one frame output queue */
904#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6)
905
906
907#define MSM_V4L2_VID_CAP_TYPE 0
908#define MSM_V4L2_STREAM_ON 1
909#define MSM_V4L2_STREAM_OFF 2
910#define MSM_V4L2_SNAPSHOT 3
911#define MSM_V4L2_QUERY_CTRL 4
912#define MSM_V4L2_GET_CTRL 5
913#define MSM_V4L2_SET_CTRL 6
914#define MSM_V4L2_QUERY 7
915#define MSM_V4L2_GET_CROP 8
916#define MSM_V4L2_SET_CROP 9
917#define MSM_V4L2_OPEN 10
918#define MSM_V4L2_CLOSE 11
919#define MSM_V4L2_SET_CTRL_CMD 12
920#define MSM_V4L2_EVT_SUB_MASK 13
921#define MSM_V4L2_PRIVATE_CMD 14
922#define MSM_V4L2_MAX 15
923#define V4L2_CAMERA_EXIT 43
924
925struct crop_info {
926 void *info;
927 int len;
928};
929
930struct msm_postproc {
931 int ftnum;
932 struct msm_frame fthumnail;
933 int fmnum;
934 struct msm_frame fmain;
935};
936
937struct msm_snapshot_pp_status {
938 void *status;
939};
940
941#define CFG_SET_MODE 0
942#define CFG_SET_EFFECT 1
943#define CFG_START 2
944#define CFG_PWR_UP 3
945#define CFG_PWR_DOWN 4
946#define CFG_WRITE_EXPOSURE_GAIN 5
947#define CFG_SET_DEFAULT_FOCUS 6
948#define CFG_MOVE_FOCUS 7
949#define CFG_REGISTER_TO_REAL_GAIN 8
950#define CFG_REAL_TO_REGISTER_GAIN 9
951#define CFG_SET_FPS 10
952#define CFG_SET_PICT_FPS 11
953#define CFG_SET_BRIGHTNESS 12
954#define CFG_SET_CONTRAST 13
955#define CFG_SET_ZOOM 14
956#define CFG_SET_EXPOSURE_MODE 15
957#define CFG_SET_WB 16
958#define CFG_SET_ANTIBANDING 17
959#define CFG_SET_EXP_GAIN 18
960#define CFG_SET_PICT_EXP_GAIN 19
961#define CFG_SET_LENS_SHADING 20
962#define CFG_GET_PICT_FPS 21
963#define CFG_GET_PREV_L_PF 22
964#define CFG_GET_PREV_P_PL 23
965#define CFG_GET_PICT_L_PF 24
966#define CFG_GET_PICT_P_PL 25
967#define CFG_GET_AF_MAX_STEPS 26
968#define CFG_GET_PICT_MAX_EXP_LC 27
969#define CFG_SEND_WB_INFO 28
970#define CFG_SENSOR_INIT 29
971#define CFG_GET_3D_CALI_DATA 30
972#define CFG_GET_CALIB_DATA 31
973#define CFG_GET_OUTPUT_INFO 32
974#define CFG_GET_EEPROM_INFO 33
975#define CFG_GET_EEPROM_DATA 34
976#define CFG_SET_ACTUATOR_INFO 35
977#define CFG_GET_ACTUATOR_INFO 36
978/* TBD: QRD */
979#define CFG_SET_SATURATION 37
980#define CFG_SET_SHARPNESS 38
981#define CFG_SET_TOUCHAEC 39
982#define CFG_SET_AUTO_FOCUS 40
983#define CFG_SET_AUTOFLASH 41
984#define CFG_SET_EXPOSURE_COMPENSATION 42
985#define CFG_SET_ISO 43
986#define CFG_START_STREAM 44
987#define CFG_STOP_STREAM 45
988#define CFG_GET_CSI_PARAMS 46
989#define CFG_POWER_UP 47
990#define CFG_POWER_DOWN 48
991#define CFG_WRITE_I2C_ARRAY 49
992#define CFG_READ_I2C_ARRAY 50
993#define CFG_PCLK_CHANGE 51
994#define CFG_CONFIG_VREG_ARRAY 52
995#define CFG_CONFIG_CLK_ARRAY 53
996#define CFG_GPIO_OP 54
997#define CFG_MAX 55
998
999
1000#define MOVE_NEAR 0
1001#define MOVE_FAR 1
1002
1003#define SENSOR_PREVIEW_MODE 0
1004#define SENSOR_SNAPSHOT_MODE 1
1005#define SENSOR_RAW_SNAPSHOT_MODE 2
1006#define SENSOR_HFR_60FPS_MODE 3
1007#define SENSOR_HFR_90FPS_MODE 4
1008#define SENSOR_HFR_120FPS_MODE 5
1009
1010#define SENSOR_QTR_SIZE 0
1011#define SENSOR_FULL_SIZE 1
1012#define SENSOR_QVGA_SIZE 2
1013#define SENSOR_INVALID_SIZE 3
1014
1015#define CAMERA_EFFECT_OFF 0
1016#define CAMERA_EFFECT_MONO 1
1017#define CAMERA_EFFECT_NEGATIVE 2
1018#define CAMERA_EFFECT_SOLARIZE 3
1019#define CAMERA_EFFECT_SEPIA 4
1020#define CAMERA_EFFECT_POSTERIZE 5
1021#define CAMERA_EFFECT_WHITEBOARD 6
1022#define CAMERA_EFFECT_BLACKBOARD 7
1023#define CAMERA_EFFECT_AQUA 8
1024#define CAMERA_EFFECT_EMBOSS 9
1025#define CAMERA_EFFECT_SKETCH 10
1026#define CAMERA_EFFECT_NEON 11
1027#define CAMERA_EFFECT_FADED 12
1028#define CAMERA_EFFECT_VINTAGECOOL 13
1029#define CAMERA_EFFECT_VINTAGEWARM 14
1030#define CAMERA_EFFECT_ACCENT_BLUE 15
1031#define CAMERA_EFFECT_ACCENT_GREEN 16
1032#define CAMERA_EFFECT_ACCENT_ORANGE 17
1033#define CAMERA_EFFECT_MAX 18
1034
1035/* QRD */
1036#define CAMERA_EFFECT_BW 10
1037#define CAMERA_EFFECT_BLUISH 12
1038#define CAMERA_EFFECT_REDDISH 13
1039#define CAMERA_EFFECT_GREENISH 14
1040
1041/* QRD */
1042#define CAMERA_ANTIBANDING_OFF 0
1043#define CAMERA_ANTIBANDING_50HZ 2
1044#define CAMERA_ANTIBANDING_60HZ 1
1045#define CAMERA_ANTIBANDING_AUTO 3
1046
1047#define CAMERA_CONTRAST_LV0 0
1048#define CAMERA_CONTRAST_LV1 1
1049#define CAMERA_CONTRAST_LV2 2
1050#define CAMERA_CONTRAST_LV3 3
1051#define CAMERA_CONTRAST_LV4 4
1052#define CAMERA_CONTRAST_LV5 5
1053#define CAMERA_CONTRAST_LV6 6
1054#define CAMERA_CONTRAST_LV7 7
1055#define CAMERA_CONTRAST_LV8 8
1056#define CAMERA_CONTRAST_LV9 9
1057
1058#define CAMERA_BRIGHTNESS_LV0 0
1059#define CAMERA_BRIGHTNESS_LV1 1
1060#define CAMERA_BRIGHTNESS_LV2 2
1061#define CAMERA_BRIGHTNESS_LV3 3
1062#define CAMERA_BRIGHTNESS_LV4 4
1063#define CAMERA_BRIGHTNESS_LV5 5
1064#define CAMERA_BRIGHTNESS_LV6 6
1065#define CAMERA_BRIGHTNESS_LV7 7
1066#define CAMERA_BRIGHTNESS_LV8 8
1067
1068
1069#define CAMERA_SATURATION_LV0 0
1070#define CAMERA_SATURATION_LV1 1
1071#define CAMERA_SATURATION_LV2 2
1072#define CAMERA_SATURATION_LV3 3
1073#define CAMERA_SATURATION_LV4 4
1074#define CAMERA_SATURATION_LV5 5
1075#define CAMERA_SATURATION_LV6 6
1076#define CAMERA_SATURATION_LV7 7
1077#define CAMERA_SATURATION_LV8 8
1078
1079#define CAMERA_SHARPNESS_LV0 0
1080#define CAMERA_SHARPNESS_LV1 3
1081#define CAMERA_SHARPNESS_LV2 6
1082#define CAMERA_SHARPNESS_LV3 9
1083#define CAMERA_SHARPNESS_LV4 12
1084#define CAMERA_SHARPNESS_LV5 15
1085#define CAMERA_SHARPNESS_LV6 18
1086#define CAMERA_SHARPNESS_LV7 21
1087#define CAMERA_SHARPNESS_LV8 24
1088#define CAMERA_SHARPNESS_LV9 27
1089#define CAMERA_SHARPNESS_LV10 30
1090
1091#define CAMERA_SETAE_AVERAGE 0
1092#define CAMERA_SETAE_CENWEIGHT 1
1093
1094#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */
1095#define CAMERA_WB_CUSTOM 2
1096#define CAMERA_WB_INCANDESCENT 3
1097#define CAMERA_WB_FLUORESCENT 4
1098#define CAMERA_WB_DAYLIGHT 5
1099#define CAMERA_WB_CLOUDY_DAYLIGHT 6
1100#define CAMERA_WB_TWILIGHT 7
1101#define CAMERA_WB_SHADE 8
1102
1103#define CAMERA_EXPOSURE_COMPENSATION_LV0 12
1104#define CAMERA_EXPOSURE_COMPENSATION_LV1 6
1105#define CAMERA_EXPOSURE_COMPENSATION_LV2 0
1106#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6
1107#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12
1108
1109enum msm_v4l2_saturation_level {
1110 MSM_V4L2_SATURATION_L0,
1111 MSM_V4L2_SATURATION_L1,
1112 MSM_V4L2_SATURATION_L2,
1113 MSM_V4L2_SATURATION_L3,
1114 MSM_V4L2_SATURATION_L4,
1115 MSM_V4L2_SATURATION_L5,
1116 MSM_V4L2_SATURATION_L6,
1117 MSM_V4L2_SATURATION_L7,
1118 MSM_V4L2_SATURATION_L8,
1119 MSM_V4L2_SATURATION_L9,
1120 MSM_V4L2_SATURATION_L10,
1121};
1122
1123enum msm_v4l2_contrast_level {
1124 MSM_V4L2_CONTRAST_L0,
1125 MSM_V4L2_CONTRAST_L1,
1126 MSM_V4L2_CONTRAST_L2,
1127 MSM_V4L2_CONTRAST_L3,
1128 MSM_V4L2_CONTRAST_L4,
1129 MSM_V4L2_CONTRAST_L5,
1130 MSM_V4L2_CONTRAST_L6,
1131 MSM_V4L2_CONTRAST_L7,
1132 MSM_V4L2_CONTRAST_L8,
1133 MSM_V4L2_CONTRAST_L9,
1134 MSM_V4L2_CONTRAST_L10,
1135};
1136
1137
1138enum msm_v4l2_exposure_level {
1139 MSM_V4L2_EXPOSURE_N2,
1140 MSM_V4L2_EXPOSURE_N1,
1141 MSM_V4L2_EXPOSURE_D,
1142 MSM_V4L2_EXPOSURE_P1,
1143 MSM_V4L2_EXPOSURE_P2,
1144};
1145
1146enum msm_v4l2_sharpness_level {
1147 MSM_V4L2_SHARPNESS_L0,
1148 MSM_V4L2_SHARPNESS_L1,
1149 MSM_V4L2_SHARPNESS_L2,
1150 MSM_V4L2_SHARPNESS_L3,
1151 MSM_V4L2_SHARPNESS_L4,
1152 MSM_V4L2_SHARPNESS_L5,
1153 MSM_V4L2_SHARPNESS_L6,
1154};
1155
1156enum msm_v4l2_expo_metering_mode {
1157 MSM_V4L2_EXP_FRAME_AVERAGE,
1158 MSM_V4L2_EXP_CENTER_WEIGHTED,
1159 MSM_V4L2_EXP_SPOT_METERING,
1160};
1161
1162enum msm_v4l2_iso_mode {
1163 MSM_V4L2_ISO_AUTO = 0,
1164 MSM_V4L2_ISO_DEBLUR,
1165 MSM_V4L2_ISO_100,
1166 MSM_V4L2_ISO_200,
1167 MSM_V4L2_ISO_400,
1168 MSM_V4L2_ISO_800,
1169 MSM_V4L2_ISO_1600,
1170};
1171
1172enum msm_v4l2_wb_mode {
1173 MSM_V4L2_WB_OFF,
1174 MSM_V4L2_WB_AUTO,
1175 MSM_V4L2_WB_CUSTOM,
1176 MSM_V4L2_WB_INCANDESCENT,
1177 MSM_V4L2_WB_FLUORESCENT,
1178 MSM_V4L2_WB_DAYLIGHT,
1179 MSM_V4L2_WB_CLOUDY_DAYLIGHT,
1180};
1181
1182enum msm_v4l2_special_effect {
1183 MSM_V4L2_EFFECT_OFF,
1184 MSM_V4L2_EFFECT_MONO,
1185 MSM_V4L2_EFFECT_NEGATIVE,
1186 MSM_V4L2_EFFECT_SOLARIZE,
1187 MSM_V4L2_EFFECT_SEPIA,
1188 MSM_V4L2_EFFECT_POSTERAIZE,
1189 MSM_V4L2_EFFECT_WHITEBOARD,
1190 MSM_V4L2_EFFECT_BLACKBOARD,
1191 MSM_V4L2_EFFECT_AQUA,
1192 MSM_V4L2_EFFECT_EMBOSS,
1193 MSM_V4L2_EFFECT_SKETCH,
1194 MSM_V4L2_EFFECT_NEON,
1195 MSM_V4L2_EFFECT_MAX,
1196};
1197
1198enum msm_v4l2_power_line_frequency {
1199 MSM_V4L2_POWER_LINE_OFF,
1200 MSM_V4L2_POWER_LINE_60HZ,
1201 MSM_V4L2_POWER_LINE_50HZ,
1202 MSM_V4L2_POWER_LINE_AUTO,
1203};
1204
1205#define CAMERA_ISO_TYPE_AUTO 0
1206#define CAMEAR_ISO_TYPE_HJR 1
1207#define CAMEAR_ISO_TYPE_100 2
1208#define CAMERA_ISO_TYPE_200 3
1209#define CAMERA_ISO_TYPE_400 4
1210#define CAMEAR_ISO_TYPE_800 5
1211#define CAMERA_ISO_TYPE_1600 6
1212
1213struct sensor_pict_fps {
1214 uint16_t prevfps;
1215 uint16_t pictfps;
1216};
1217
1218struct exp_gain_cfg {
1219 uint16_t gain;
1220 uint32_t line;
1221};
1222
1223struct focus_cfg {
1224 int32_t steps;
1225 int dir;
1226};
1227
1228struct fps_cfg {
1229 uint16_t f_mult;
1230 uint16_t fps_div;
1231 uint32_t pict_fps_div;
1232};
1233struct wb_info_cfg {
1234 uint16_t red_gain;
1235 uint16_t green_gain;
1236 uint16_t blue_gain;
1237};
1238struct sensor_3d_exp_cfg {
1239 uint16_t gain;
1240 uint32_t line;
1241 uint16_t r_gain;
1242 uint16_t b_gain;
1243 uint16_t gr_gain;
1244 uint16_t gb_gain;
1245 uint16_t gain_adjust;
1246};
1247struct sensor_3d_cali_data_t {
1248 unsigned char left_p_matrix[3][4][8];
1249 unsigned char right_p_matrix[3][4][8];
1250 unsigned char square_len[8];
1251 unsigned char focal_len[8];
1252 unsigned char pixel_pitch[8];
1253 uint16_t left_r;
1254 uint16_t left_b;
1255 uint16_t left_gb;
1256 uint16_t left_af_far;
1257 uint16_t left_af_mid;
1258 uint16_t left_af_short;
1259 uint16_t left_af_5um;
1260 uint16_t left_af_50up;
1261 uint16_t left_af_50down;
1262 uint16_t right_r;
1263 uint16_t right_b;
1264 uint16_t right_gb;
1265 uint16_t right_af_far;
1266 uint16_t right_af_mid;
1267 uint16_t right_af_short;
1268 uint16_t right_af_5um;
1269 uint16_t right_af_50up;
1270 uint16_t right_af_50down;
1271};
1272struct sensor_init_cfg {
1273 uint8_t prev_res;
1274 uint8_t pict_res;
1275};
1276
1277struct sensor_calib_data {
1278 /* Color Related Measurements */
1279 uint16_t r_over_g;
1280 uint16_t b_over_g;
1281 uint16_t gr_over_gb;
1282
1283 /* Lens Related Measurements */
1284 uint16_t macro_2_inf;
1285 uint16_t inf_2_macro;
1286 uint16_t stroke_amt;
1287 uint16_t af_pos_1m;
1288 uint16_t af_pos_inf;
1289};
1290
1291enum msm_sensor_resolution_t {
1292 MSM_SENSOR_RES_FULL,
1293 MSM_SENSOR_RES_QTR,
1294 MSM_SENSOR_RES_2,
1295 MSM_SENSOR_RES_3,
1296 MSM_SENSOR_RES_4,
1297 MSM_SENSOR_RES_5,
1298 MSM_SENSOR_RES_6,
1299 MSM_SENSOR_RES_7,
1300 MSM_SENSOR_INVALID_RES,
1301};
1302
1303struct msm_sensor_output_info_t {
1304 uint16_t x_output;
1305 uint16_t y_output;
1306 uint16_t line_length_pclk;
1307 uint16_t frame_length_lines;
1308 uint32_t vt_pixel_clk;
1309 uint32_t op_pixel_clk;
1310 uint16_t binning_factor;
1311};
1312
1313struct sensor_output_info_t {
1314 struct msm_sensor_output_info_t *output_info;
1315 uint16_t num_info;
1316};
1317
1318struct msm_sensor_exp_gain_info_t {
1319 uint16_t coarse_int_time_addr;
1320 uint16_t global_gain_addr;
1321 uint16_t vert_offset;
1322};
1323
1324struct msm_sensor_output_reg_addr_t {
1325 uint16_t x_output;
1326 uint16_t y_output;
1327 uint16_t line_length_pclk;
1328 uint16_t frame_length_lines;
1329};
1330
1331struct sensor_driver_params_type {
1332 struct msm_camera_i2c_reg_setting *init_settings;
1333 uint16_t init_settings_size;
1334 struct msm_camera_i2c_reg_setting *mode_settings;
1335 uint16_t mode_settings_size;
1336 struct msm_sensor_output_reg_addr_t *sensor_output_reg_addr;
1337 struct msm_camera_i2c_reg_setting *start_settings;
1338 struct msm_camera_i2c_reg_setting *stop_settings;
1339 struct msm_camera_i2c_reg_setting *groupon_settings;
1340 struct msm_camera_i2c_reg_setting *groupoff_settings;
1341 struct msm_sensor_exp_gain_info_t *sensor_exp_gain_info;
1342 struct msm_sensor_output_info_t *output_info;
1343};
1344
1345struct mirror_flip {
1346 int32_t x_mirror;
1347 int32_t y_flip;
1348};
1349
1350struct cord {
1351 uint32_t x;
1352 uint32_t y;
1353};
1354
1355struct msm_eeprom_data_t {
1356 void *eeprom_data;
1357 uint16_t index;
1358};
1359
1360struct msm_camera_csid_vc_cfg {
1361 uint8_t cid;
1362 uint8_t dt;
1363 uint8_t decode_format;
1364};
1365
1366struct csi_lane_params_t {
1367 uint16_t csi_lane_assign;
1368 uint8_t csi_lane_mask;
1369 uint8_t csi_if;
1370 uint8_t csid_core[2];
1371 uint8_t csi_phy_sel;
1372};
1373
1374struct msm_camera_csid_lut_params {
1375 uint8_t num_cid;
1376 struct msm_camera_csid_vc_cfg *vc_cfg;
1377};
1378
1379struct msm_camera_csid_params {
1380 uint8_t lane_cnt;
1381 uint16_t lane_assign;
1382 uint8_t phy_sel;
1383 struct msm_camera_csid_lut_params lut_params;
1384};
1385
1386struct msm_camera_csiphy_params {
1387 uint8_t lane_cnt;
1388 uint8_t settle_cnt;
1389 uint16_t lane_mask;
1390 uint8_t combo_mode;
1391 uint8_t csid_core;
1392};
1393
1394struct msm_camera_csi2_params {
1395 struct msm_camera_csid_params csid_params;
1396 struct msm_camera_csiphy_params csiphy_params;
1397};
1398
1399enum msm_camera_csi_data_format {
1400 CSI_8BIT,
1401 CSI_10BIT,
1402 CSI_12BIT,
1403};
1404
1405struct msm_camera_csi_params {
1406 enum msm_camera_csi_data_format data_format;
1407 uint8_t lane_cnt;
1408 uint8_t lane_assign;
1409 uint8_t settle_cnt;
1410 uint8_t dpcm_scheme;
1411};
1412
1413enum csic_cfg_type_t {
1414 CSIC_INIT,
1415 CSIC_CFG,
1416};
1417
1418struct csic_cfg_data {
1419 enum csic_cfg_type_t cfgtype;
1420 struct msm_camera_csi_params *csic_params;
1421};
1422
1423enum csid_cfg_type_t {
1424 CSID_INIT,
1425 CSID_CFG,
1426};
1427
1428struct csid_cfg_data {
1429 enum csid_cfg_type_t cfgtype;
1430 union {
1431 uint32_t csid_version;
1432 struct msm_camera_csid_params *csid_params;
1433 } cfg;
1434};
1435
1436enum csiphy_cfg_type_t {
1437 CSIPHY_INIT,
1438 CSIPHY_CFG,
1439};
1440
1441struct csiphy_cfg_data {
1442 enum csiphy_cfg_type_t cfgtype;
1443 struct msm_camera_csiphy_params *csiphy_params;
1444};
1445
1446#define CSI_EMBED_DATA 0x12
1447#define CSI_RESERVED_DATA_0 0x13
1448#define CSI_YUV422_8 0x1E
1449#define CSI_RAW8 0x2A
1450#define CSI_RAW10 0x2B
1451#define CSI_RAW12 0x2C
1452
1453#define CSI_DECODE_6BIT 0
1454#define CSI_DECODE_8BIT 1
1455#define CSI_DECODE_10BIT 2
1456#define CSI_DECODE_DPCM_10_8_10 5
1457
1458#define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+\
1459 (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT))
1460#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0)
1461#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1)
1462#define ISPIF_OFF_IMMEDIATELY (0x01 << 2)
1463#define ISPIF_S_STREAM_SHIFT 4
1464#define ISPIF_VFE_INTF_SHIFT 12
1465
1466#define PIX_0 (0x01 << 0)
1467#define RDI_0 (0x01 << 1)
1468#define PIX_1 (0x01 << 2)
1469#define RDI_1 (0x01 << 3)
1470#define RDI_2 (0x01 << 4)
1471
1472enum msm_ispif_vfe_intf {
1473 VFE0,
1474 VFE1,
1475 VFE_MAX,
1476};
1477
1478enum msm_ispif_intftype {
1479 PIX0,
1480 RDI0,
1481 PIX1,
1482 RDI1,
1483 RDI2,
1484 INTF_MAX,
1485};
1486
1487enum msm_ispif_vc {
1488 VC0,
1489 VC1,
1490 VC2,
1491 VC3,
1492};
1493
1494enum msm_ispif_cid {
1495 CID0,
1496 CID1,
1497 CID2,
1498 CID3,
1499 CID4,
1500 CID5,
1501 CID6,
1502 CID7,
1503 CID8,
1504 CID9,
1505 CID10,
1506 CID11,
1507 CID12,
1508 CID13,
1509 CID14,
1510 CID15,
1511};
1512
1513struct msm_ispif_params {
1514 uint8_t intftype;
1515 uint16_t cid_mask;
1516 uint8_t csid;
1517 uint8_t vfe_intf;
1518};
1519
1520struct msm_ispif_params_list {
1521 uint32_t len;
1522 struct msm_ispif_params params[4];
1523};
1524
1525enum ispif_cfg_type_t {
1526 ISPIF_INIT,
1527 ISPIF_SET_CFG,
1528 ISPIF_SET_ON_FRAME_BOUNDARY,
1529 ISPIF_SET_OFF_FRAME_BOUNDARY,
1530 ISPIF_SET_OFF_IMMEDIATELY,
1531 ISPIF_RELEASE,
1532};
1533
1534struct ispif_cfg_data {
1535 enum ispif_cfg_type_t cfgtype;
1536 union {
1537 uint32_t csid_version;
1538 int cmd;
1539 struct msm_ispif_params_list ispif_params;
1540 } cfg;
1541};
1542
1543enum msm_camera_i2c_reg_addr_type {
1544 MSM_CAMERA_I2C_BYTE_ADDR = 1,
1545 MSM_CAMERA_I2C_WORD_ADDR,
1546 MSM_CAMERA_I2C_3B_ADDR,
1547 MSM_CAMERA_I2C_DWORD_ADDR,
1548};
1549#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR
1550
1551struct msm_camera_i2c_reg_array {
1552 uint16_t reg_addr;
1553 uint16_t reg_data;
1554};
1555
1556enum msm_camera_i2c_data_type {
1557 MSM_CAMERA_I2C_BYTE_DATA = 1,
1558 MSM_CAMERA_I2C_WORD_DATA,
1559 MSM_CAMERA_I2C_SET_BYTE_MASK,
1560 MSM_CAMERA_I2C_UNSET_BYTE_MASK,
1561 MSM_CAMERA_I2C_SET_WORD_MASK,
1562 MSM_CAMERA_I2C_UNSET_WORD_MASK,
1563 MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,
1564};
1565
1566struct msm_camera_i2c_reg_setting {
1567 struct msm_camera_i2c_reg_array *reg_setting;
1568 uint16_t size;
1569 enum msm_camera_i2c_reg_addr_type addr_type;
1570 enum msm_camera_i2c_data_type data_type;
1571 uint16_t delay;
1572};
1573
1574enum oem_setting_type {
1575 I2C_READ = 1,
1576 I2C_WRITE,
1577 GPIO_OP,
1578 EEPROM_READ,
1579 VREG_SET,
1580 CLK_SET,
1581};
1582
1583struct sensor_oem_setting {
1584 enum oem_setting_type type;
1585 void *data;
1586};
1587
1588enum camera_vreg_type {
1589 REG_LDO,
1590 REG_VS,
1591 REG_GPIO,
1592};
1593
1594enum msm_camera_vreg_name_t {
1595 CAM_VDIG,
1596 CAM_VIO,
1597 CAM_VANA,
1598 CAM_VAF,
1599 CAM_VREG_MAX,
1600};
1601
1602struct msm_camera_csi_lane_params {
1603 uint16_t csi_lane_assign;
1604 uint16_t csi_lane_mask;
1605};
1606
1607struct camera_vreg_t {
1608 const char *reg_name;
1609 int min_voltage;
1610 int max_voltage;
1611 int op_mode;
1612 uint32_t delay;
1613};
1614
1615struct msm_camera_vreg_setting {
1616 struct camera_vreg_t *cam_vreg;
1617 uint16_t num_vreg;
1618 uint8_t enable;
1619};
1620
1621struct msm_cam_clk_info {
1622 const char *clk_name;
1623 long clk_rate;
1624 uint32_t delay;
1625};
1626
1627struct msm_cam_clk_setting {
1628 struct msm_cam_clk_info *clk_info;
1629 uint16_t num_clk_info;
1630 uint8_t enable;
1631};
1632
1633struct sensor_cfg_data {
1634 int cfgtype;
1635 int mode;
1636 int rs;
1637 uint8_t max_steps;
1638
1639 union {
1640 int8_t effect;
1641 uint8_t lens_shading;
1642 uint16_t prevl_pf;
1643 uint16_t prevp_pl;
1644 uint16_t pictl_pf;
1645 uint16_t pictp_pl;
1646 uint32_t pict_max_exp_lc;
1647 uint16_t p_fps;
1648 uint8_t iso_type;
1649 struct sensor_init_cfg init_info;
1650 struct sensor_pict_fps gfps;
1651 struct exp_gain_cfg exp_gain;
1652 struct focus_cfg focus;
1653 struct fps_cfg fps;
1654 struct wb_info_cfg wb_info;
1655 struct sensor_3d_exp_cfg sensor_3d_exp;
1656 struct sensor_calib_data calib_info;
1657 struct sensor_output_info_t output_info;
1658 struct msm_eeprom_data_t eeprom_data;
1659 struct csi_lane_params_t csi_lane_params;
1660 /* QRD */
1661 uint16_t antibanding;
1662 uint8_t contrast;
1663 uint8_t saturation;
1664 uint8_t sharpness;
1665 int8_t brightness;
1666 int ae_mode;
1667 uint8_t wb_val;
1668 int8_t exp_compensation;
1669 uint32_t pclk;
1670 struct cord aec_cord;
1671 int is_autoflash;
1672 struct mirror_flip mirror_flip;
1673 void *setting;
1674 } cfg;
1675};
1676
1677enum gpio_operation_type {
1678 GPIO_REQUEST,
1679 GPIO_FREE,
1680 GPIO_SET_DIRECTION_OUTPUT,
1681 GPIO_SET_DIRECTION_INPUT,
1682 GPIO_GET_VALUE,
1683 GPIO_SET_VALUE,
1684};
1685
1686struct msm_cam_gpio_operation {
1687 enum gpio_operation_type op_type;
1688 unsigned int address;
1689 int value;
1690 const char *tag;
1691};
1692
1693struct damping_params_t {
1694 uint32_t damping_step;
1695 uint32_t damping_delay;
1696 uint32_t hw_params;
1697};
1698
1699enum actuator_type {
1700 ACTUATOR_VCM,
1701 ACTUATOR_PIEZO,
1702 ACTUATOR_HVCM,
1703 ACTUATOR_BIVCM,
1704};
1705
1706enum msm_actuator_data_type {
1707 MSM_ACTUATOR_BYTE_DATA = 1,
1708 MSM_ACTUATOR_WORD_DATA,
1709};
1710
1711enum msm_actuator_addr_type {
1712 MSM_ACTUATOR_BYTE_ADDR = 1,
1713 MSM_ACTUATOR_WORD_ADDR,
1714};
1715
1716enum msm_actuator_write_type {
1717 MSM_ACTUATOR_WRITE_HW_DAMP,
1718 MSM_ACTUATOR_WRITE_DAC,
1719 MSM_ACTUATOR_WRITE,
1720 MSM_ACTUATOR_WRITE_DIR_REG,
1721 MSM_ACTUATOR_POLL,
1722 MSM_ACTUATOR_READ_WRITE,
1723};
1724
1725struct msm_actuator_reg_params_t {
1726 enum msm_actuator_write_type reg_write_type;
1727 uint32_t hw_mask;
1728 uint16_t reg_addr;
1729 uint16_t hw_shift;
1730 uint16_t data_type;
1731 uint16_t addr_type;
1732 uint16_t reg_data;
1733 uint16_t delay;
1734};
1735
1736struct reg_settings_t {
1737 uint16_t reg_addr;
1738 uint16_t reg_data;
1739};
1740
1741struct region_params_t {
1742 /* [0] = ForwardDirection Macro boundary
1743 * [1] = ReverseDirection Inf boundary
1744 */
1745 uint16_t step_bound[2];
1746 uint16_t code_per_step;
1747};
1748
1749struct msm_actuator_move_params_t {
1750 int8_t dir;
1751 int8_t sign_dir;
1752 int16_t dest_step_pos;
1753 int32_t num_steps;
1754 struct damping_params_t __user *ringing_params;
1755};
1756
1757struct msm_actuator_tuning_params_t {
1758 int16_t initial_code;
1759 uint16_t pwd_step;
1760 uint16_t region_size;
1761 uint32_t total_steps;
1762 struct region_params_t __user *region_params;
1763};
1764
1765struct msm_actuator_params_t {
1766 enum actuator_type act_type;
1767 uint8_t reg_tbl_size;
1768 uint16_t data_size;
1769 uint16_t init_setting_size;
1770 uint32_t i2c_addr;
1771 enum msm_actuator_addr_type i2c_addr_type;
1772 enum msm_actuator_data_type i2c_data_type;
1773 struct msm_actuator_reg_params_t __user *reg_tbl_params;
1774 struct reg_settings_t __user *init_settings;
1775};
1776
1777struct msm_actuator_set_info_t {
1778 struct msm_actuator_params_t actuator_params;
1779 struct msm_actuator_tuning_params_t af_tuning_params;
1780};
1781
1782struct msm_actuator_get_info_t {
1783 uint32_t focal_length_num;
1784 uint32_t focal_length_den;
1785 uint32_t f_number_num;
1786 uint32_t f_number_den;
1787 uint32_t f_pix_num;
1788 uint32_t f_pix_den;
1789 uint32_t total_f_dist_num;
1790 uint32_t total_f_dist_den;
1791 uint32_t hor_view_angle_num;
1792 uint32_t hor_view_angle_den;
1793 uint32_t ver_view_angle_num;
1794 uint32_t ver_view_angle_den;
1795};
1796
1797enum af_camera_name {
1798 ACTUATOR_MAIN_CAM_0,
1799 ACTUATOR_MAIN_CAM_1,
1800 ACTUATOR_MAIN_CAM_2,
1801 ACTUATOR_MAIN_CAM_3,
1802 ACTUATOR_MAIN_CAM_4,
1803 ACTUATOR_MAIN_CAM_5,
1804 ACTUATOR_WEB_CAM_0,
1805 ACTUATOR_WEB_CAM_1,
1806 ACTUATOR_WEB_CAM_2,
1807};
1808
1809struct msm_actuator_cfg_data {
1810 int cfgtype;
1811 uint8_t is_af_supported;
1812 union {
1813 struct msm_actuator_move_params_t move;
1814 struct msm_actuator_set_info_t set_info;
1815 struct msm_actuator_get_info_t get_info;
1816 enum af_camera_name cam_name;
1817 } cfg;
1818};
1819
1820struct msm_eeprom_support {
1821 uint16_t is_supported;
1822 uint16_t size;
1823 uint16_t index;
1824 uint16_t qvalue;
1825};
1826
1827struct msm_calib_wb {
1828 uint16_t r_over_g;
1829 uint16_t b_over_g;
1830 uint16_t gr_over_gb;
1831};
1832
1833struct msm_calib_af {
1834 uint16_t macro_dac;
1835 uint16_t inf_dac;
1836 uint16_t start_dac;
1837};
1838
1839struct msm_calib_lsc {
1840 uint16_t r_gain[221];
1841 uint16_t b_gain[221];
1842 uint16_t gr_gain[221];
1843 uint16_t gb_gain[221];
1844};
1845
1846struct pixel_t {
1847 int x;
1848 int y;
1849};
1850
1851struct msm_calib_dpc {
1852 uint16_t validcount;
1853 struct pixel_t snapshot_coord[128];
1854 struct pixel_t preview_coord[128];
1855 struct pixel_t video_coord[128];
1856};
1857
1858struct msm_calib_raw {
1859 uint8_t *data;
1860 uint32_t size;
1861};
1862
1863struct msm_camera_eeprom_info_t {
1864 struct msm_eeprom_support af;
1865 struct msm_eeprom_support wb;
1866 struct msm_eeprom_support lsc;
1867 struct msm_eeprom_support dpc;
1868 struct msm_eeprom_support raw;
1869};
1870
1871struct msm_eeprom_cfg_data {
1872 int cfgtype;
1873 uint8_t is_eeprom_supported;
1874 union {
1875 struct msm_eeprom_data_t get_data;
1876 struct msm_camera_eeprom_info_t get_info;
1877 } cfg;
1878};
1879
1880struct sensor_large_data {
1881 int cfgtype;
1882 union {
1883 struct sensor_3d_cali_data_t sensor_3d_cali_data;
1884 } data;
1885};
1886
1887enum sensor_type_t {
1888 BAYER,
1889 YUV,
1890 JPEG_SOC,
1891};
1892
1893enum flash_type {
1894 LED_FLASH,
1895 STROBE_FLASH,
1896};
1897
1898enum strobe_flash_ctrl_type {
1899 STROBE_FLASH_CTRL_INIT,
1900 STROBE_FLASH_CTRL_CHARGE,
1901 STROBE_FLASH_CTRL_RELEASE
1902};
1903
1904struct strobe_flash_ctrl_data {
1905 enum strobe_flash_ctrl_type type;
1906 int charge_en;
1907};
1908
1909struct msm_camera_info {
1910 int num_cameras;
1911 uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS];
1912 uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS];
1913 uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS];
1914 const char *video_dev_name[MSM_MAX_CAMERA_SENSORS];
1915 enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS];
1916};
1917
1918struct msm_cam_config_dev_info {
1919 int num_config_nodes;
1920 const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS];
1921 int config_dev_id[MSM_MAX_CAMERA_CONFIGS];
1922};
1923
1924struct msm_mctl_node_info {
1925 int num_mctl_nodes;
1926 const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS];
1927};
1928
1929struct flash_ctrl_data {
1930 int flashtype;
1931 union {
1932 int led_state;
1933 struct strobe_flash_ctrl_data strobe_ctrl;
1934 } ctrl_data;
1935};
1936
1937#define GET_NAME 0
1938#define GET_PREVIEW_LINE_PER_FRAME 1
1939#define GET_PREVIEW_PIXELS_PER_LINE 2
1940#define GET_SNAPSHOT_LINE_PER_FRAME 3
1941#define GET_SNAPSHOT_PIXELS_PER_LINE 4
1942#define GET_SNAPSHOT_FPS 5
1943#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6
1944
1945struct msm_camsensor_info {
1946 char name[MAX_SENSOR_NAME];
1947 uint8_t flash_enabled;
1948 uint8_t strobe_flash_enabled;
1949 uint8_t actuator_enabled;
1950 uint8_t ispif_supported;
1951 int8_t total_steps;
1952 uint8_t support_3d;
1953 enum flash_type flashtype;
1954 enum sensor_type_t sensor_type;
1955 uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */
1956 uint32_t camera_type; /* msm_camera_type */
1957 int mount_angle;
1958 uint32_t max_width;
1959 uint32_t max_height;
1960};
1961
1962#define V4L2_SINGLE_PLANE 0
1963#define V4L2_MULTI_PLANE_Y 0
1964#define V4L2_MULTI_PLANE_CBCR 1
1965#define V4L2_MULTI_PLANE_CB 1
1966#define V4L2_MULTI_PLANE_CR 2
1967
1968struct plane_data {
1969 int plane_id;
1970 uint32_t offset;
1971 unsigned long size;
1972};
1973
1974struct img_plane_info {
1975 uint32_t width;
1976 uint32_t height;
1977 uint32_t pixelformat;
1978 uint8_t buffer_type; /*Single/Multi planar*/
1979 uint8_t output_port;
1980 uint32_t ext_mode;
1981 uint8_t num_planes;
1982 struct plane_data plane[MAX_PLANES];
1983 uint32_t sp_y_offset;
1984 uint32_t inst_handle;
1985};
1986
1987#define QCAMERA_NAME "qcamera"
1988#define QCAMERA_SERVER_NAME "qcamera_server"
1989#define QCAMERA_DEVICE_GROUP_ID 1
1990#define QCAMERA_VNODE_GROUP_ID 2
1991
1992enum msm_cam_subdev_type {
1993 CSIPHY_DEV,
1994 CSID_DEV,
1995 CSIC_DEV,
1996 ISPIF_DEV,
1997 VFE_DEV,
1998 AXI_DEV,
1999 VPE_DEV,
2000 SENSOR_DEV,
2001 ACTUATOR_DEV,
2002 EEPROM_DEV,
2003 GESTURE_DEV,
2004 IRQ_ROUTER_DEV,
2005 CPP_DEV,
2006 CCI_DEV,
2007 FLASH_DEV,
2008};
2009
2010struct msm_mctl_set_sdev_data {
2011 uint32_t revision;
2012 enum msm_cam_subdev_type sdev_type;
2013};
2014
2015#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \
2016 _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
2017
2018#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \
2019 _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
2020
2021#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \
2022 _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
2023
2024#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \
2025 _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
2026
2027#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \
2028 _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
2029
2030#define MSM_CAM_IOCTL_SEND_EVENT \
2031 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event)
2032
2033#define MSM_CAM_V4L2_IOCTL_CFG_VPE \
2034 _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd)
2035
2036#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \
2037 _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
2038
2039#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL \
2040 _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t)
2041
2042#define MSM_CAM_V4L2_IOCTL_PRIVATE_GENERAL \
2043 _IOW('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t)
2044
2045#define VIDIOC_MSM_VPE_INIT \
2046 _IO('V', BASE_VIDIOC_PRIVATE + 15)
2047
2048#define VIDIOC_MSM_VPE_RELEASE \
2049 _IO('V', BASE_VIDIOC_PRIVATE + 16)
2050
2051#define VIDIOC_MSM_VPE_CFG \
2052 _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *)
2053
2054#define VIDIOC_MSM_AXI_INIT \
2055 _IOWR('V', BASE_VIDIOC_PRIVATE + 18, uint8_t *)
2056
2057#define VIDIOC_MSM_AXI_RELEASE \
2058 _IO('V', BASE_VIDIOC_PRIVATE + 19)
2059
2060#define VIDIOC_MSM_AXI_CFG \
2061 _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *)
2062
2063#define VIDIOC_MSM_AXI_IRQ \
2064 _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *)
2065
2066#define VIDIOC_MSM_AXI_BUF_CFG \
2067 _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *)
2068
2069#define VIDIOC_MSM_AXI_RDI_COUNT_UPDATE \
2070 _IOWR('V', BASE_VIDIOC_PRIVATE + 23, void *)
2071
2072#define VIDIOC_MSM_VFE_INIT \
2073 _IO('V', BASE_VIDIOC_PRIVATE + 24)
2074
2075#define VIDIOC_MSM_VFE_RELEASE \
2076 _IO('V', BASE_VIDIOC_PRIVATE + 25)
2077
2078struct msm_camera_v4l2_ioctl_t {
2079 uint32_t id;
2080 uint32_t len;
2081 uint32_t trans_code;
2082 void __user *ioctl_ptr;
2083};
2084
2085struct msm_camera_vfe_params_t {
2086 uint32_t operation_mode;
2087 uint32_t capture_count;
2088 uint8_t skip_reset;
2089 uint8_t stop_immediately;
2090 uint16_t port_info;
2091 uint32_t inst_handle;
2092 uint16_t cmd_type;
2093};
2094
2095enum msm_camss_irq_idx {
2096 CAMERA_SS_IRQ_0,
2097 CAMERA_SS_IRQ_1,
2098 CAMERA_SS_IRQ_2,
2099 CAMERA_SS_IRQ_3,
2100 CAMERA_SS_IRQ_4,
2101 CAMERA_SS_IRQ_5,
2102 CAMERA_SS_IRQ_6,
2103 CAMERA_SS_IRQ_7,
2104 CAMERA_SS_IRQ_8,
2105 CAMERA_SS_IRQ_9,
2106 CAMERA_SS_IRQ_10,
2107 CAMERA_SS_IRQ_11,
2108 CAMERA_SS_IRQ_12,
2109 CAMERA_SS_IRQ_MAX
2110};
2111
2112enum msm_cam_hw_idx {
2113 MSM_CAM_HW_MICRO,
2114 MSM_CAM_HW_CCI,
2115 MSM_CAM_HW_CSI0,
2116 MSM_CAM_HW_CSI1,
2117 MSM_CAM_HW_CSI2,
2118 MSM_CAM_HW_CSI3,
2119 MSM_CAM_HW_ISPIF,
2120 MSM_CAM_HW_CPP,
2121 MSM_CAM_HW_VFE0,
2122 MSM_CAM_HW_VFE1,
2123 MSM_CAM_HW_JPEG0,
2124 MSM_CAM_HW_JPEG1,
2125 MSM_CAM_HW_JPEG2,
2126 MSM_CAM_HW_MAX
2127};
2128
2129struct msm_camera_irq_cfg {
2130 /* Bit mask of all the camera hardwares that needs to
2131 * be composited into a single IRQ to the MSM.
2132 * Current usage: (may be updated based on hw changes)
2133 * Bits 31:13 - Reserved.
2134 * Bits 12:0
2135 * 12 - MSM_CAM_HW_JPEG2
2136 * 11 - MSM_CAM_HW_JPEG1
2137 * 10 - MSM_CAM_HW_JPEG0
2138 * 9 - MSM_CAM_HW_VFE1
2139 * 8 - MSM_CAM_HW_VFE0
2140 * 7 - MSM_CAM_HW_CPP
2141 * 6 - MSM_CAM_HW_ISPIF
2142 * 5 - MSM_CAM_HW_CSI3
2143 * 4 - MSM_CAM_HW_CSI2
2144 * 3 - MSM_CAM_HW_CSI1
2145 * 2 - MSM_CAM_HW_CSI0
2146 * 1 - MSM_CAM_HW_CCI
2147 * 0 - MSM_CAM_HW_MICRO
2148 */
2149 uint32_t cam_hw_mask;
2150 uint8_t irq_idx;
2151 uint8_t num_hwcore;
2152};
2153
2154#define MSM_IRQROUTER_CFG_COMPIRQ \
2155 _IOWR('V', BASE_VIDIOC_PRIVATE, void __user *)
2156
2157#define MAX_NUM_CPP_STRIPS 8
2158
2159enum msm_cpp_frame_type {
2160 MSM_CPP_OFFLINE_FRAME,
2161 MSM_CPP_REALTIME_FRAME,
2162};
2163
2164struct msm_cpp_frame_info_t {
2165 int32_t frame_id;
2166 uint32_t inst_id;
2167 uint32_t client_id;
2168 enum msm_cpp_frame_type frame_type;
2169 uint32_t num_strips;
2170};
2171
2172struct msm_ver_num_info {
2173 uint32_t main;
2174 uint32_t minor;
2175 uint32_t rev;
2176};
2177
2178#define VIDIOC_MSM_CPP_CFG \
2179 _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t)
2180
2181#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \
2182 _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
2183
2184#define VIDIOC_MSM_CPP_GET_INST_INFO \
2185 _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
2186
2187#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0)
2188
2189/* Instance Handle - inst_handle
2190 * Data bundle containing the information about where
2191 * to get a buffer for a particular camera instance.
2192 * This is a bitmask containing the following data:
2193 * Buffer Handle Bitmask:
2194 * ------------------------------------
2195 * Bits : Purpose
2196 * ------------------------------------
2197 * 31 : is Dev ID valid?
2198 * 30 - 24 : Dev ID.
2199 * 23 : is Image mode valid?
2200 * 22 - 16 : Image mode.
2201 * 15 : is MCTL PP inst idx valid?
2202 * 14 - 8 : MCTL PP inst idx.
2203 * 7 : is Video inst idx valid?
2204 * 6 - 0 : Video inst idx.
2205 */
2206#define CLR_DEVID_MODE(handle) (handle &= 0x00FFFFFF)
2207#define SET_DEVID_MODE(handle, data) \
2208 (handle |= ((0x1 << 31) | ((data & 0x7F) << 24)))
2209#define GET_DEVID_MODE(handle) \
2210 ((handle & 0x80000000) ? ((handle & 0x7F000000) >> 24) : 0xFF)
2211
2212#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF)
2213#define SET_IMG_MODE(handle, data) \
2214 (handle |= ((0x1 << 23) | ((data & 0x7F) << 16)))
2215#define GET_IMG_MODE(handle) \
2216 ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF)
2217
2218#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF)
2219#define SET_MCTLPP_INST_IDX(handle, data) \
2220 (handle |= ((0x1 << 15) | ((data & 0x7F) << 8)))
2221#define GET_MCTLPP_INST_IDX(handle) \
2222 ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF)
2223
2224#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00)
2225#define GET_VIDEO_INST_IDX(handle) \
2226 ((handle & 0x80) ? (handle & 0x7F) : 0xFF)
2227#define SET_VIDEO_INST_IDX(handle, data) \
2228 (handle |= (0x1 << 7) | (data & 0x7F))
2229#endif