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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
Jeff Garzik669a5db2006-08-29 18:12:40 -04004 *
5 * Based in part on linux/drivers/ide/pci/sl82c105.c
6 * SL82C105/Winbond 553 IDE driver
7 *
8 * and in part on the documentation and errata sheet
Alan16728da2007-02-20 17:51:51 +00009 *
10 *
11 * Note: The controller like many controllers has shared timings for
12 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
13 * in the dma_stop function. Thus we actually don't need a set_dmamode
14 * method as the PIO method is always called and will set the right PIO
15 * timing parameters.
Jeff Garzik669a5db2006-08-29 18:12:40 -040016 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040017
Jeff Garzik669a5db2006-08-29 18:12:40 -040018#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_sl82c105"
Alan Cox92ba5d02008-01-28 16:08:23 +000028#define DRV_VERSION "0.3.3"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30enum {
31 /*
32 * SL82C105 PCI config register 0x40 bits.
33 */
34 CTRL_IDE_IRQB = (1 << 30),
35 CTRL_IDE_IRQA = (1 << 28),
36 CTRL_LEGIRQ = (1 << 11),
37 CTRL_P1F16 = (1 << 5),
38 CTRL_P1EN = (1 << 4),
39 CTRL_P0F16 = (1 << 1),
40 CTRL_P0EN = (1 << 0)
41};
42
43/**
44 * sl82c105_pre_reset - probe begin
Tejun Heocc0680a2007-08-06 18:36:23 +090045 * @link: ATA link
Tejun Heod4b2bab2007-02-02 16:50:52 +090046 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -040047 *
48 * Set up cable type and use generic probe init
49 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040050
Tejun Heocc0680a2007-08-06 18:36:23 +090051static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -040052{
53 static const struct pci_bits sl82c105_enable_bits[] = {
54 { 0x40, 1, 0x01, 0x01 },
55 { 0x40, 1, 0x10, 0x10 }
56 };
Tejun Heocc0680a2007-08-06 18:36:23 +090057 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -040058 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
59
Alan Coxc9619222006-09-26 17:53:38 +010060 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
61 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +090062 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040063}
64
65
Jeff Garzik669a5db2006-08-29 18:12:40 -040066/**
67 * sl82c105_configure_piomode - set chip PIO timing
68 * @ap: ATA interface
69 * @adev: ATA device
70 * @pio: PIO mode
71 *
72 * Called to do the PIO mode setup. Our timing registers are shared
73 * so a configure_dmamode call will undo any work we do here and vice
74 * versa
75 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040076
Jeff Garzik669a5db2006-08-29 18:12:40 -040077static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
78{
79 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
80 static u16 pio_timing[5] = {
81 0x50D, 0x407, 0x304, 0x242, 0x240
82 };
83 u16 dummy;
84 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
Jeff Garzik85cd7252006-08-31 00:03:49 -040085
Jeff Garzik669a5db2006-08-29 18:12:40 -040086 pci_write_config_word(pdev, timing, pio_timing[pio]);
87 /* Can we lose this oddity of the old driver */
88 pci_read_config_word(pdev, timing, &dummy);
89}
90
91/**
92 * sl82c105_set_piomode - set initial PIO mode data
93 * @ap: ATA interface
94 * @adev: ATA device
95 *
96 * Called to do the PIO mode setup. Our timing registers are shared
97 * but we want to set the PIO timing by default.
98 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040099
Jeff Garzik669a5db2006-08-29 18:12:40 -0400100static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
101{
102 sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
103}
104
105/**
106 * sl82c105_configure_dmamode - set DMA mode in chip
107 * @ap: ATA interface
108 * @adev: ATA device
109 *
110 * Load DMA cycle times into the chip ready for a DMA transfer
111 * to occur.
112 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400113
Jeff Garzik669a5db2006-08-29 18:12:40 -0400114static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
115{
116 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
117 static u16 dma_timing[3] = {
118 0x707, 0x201, 0x200
119 };
120 u16 dummy;
121 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
122 int dma = adev->dma_mode - XFER_MW_DMA_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400123
Jeff Garzik669a5db2006-08-29 18:12:40 -0400124 pci_write_config_word(pdev, timing, dma_timing[dma]);
125 /* Can we lose this oddity of the old driver */
126 pci_read_config_word(pdev, timing, &dummy);
127}
128
129/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400130 * sl82c105_reset_engine - Reset the DMA engine
131 * @ap: ATA interface
132 *
133 * The sl82c105 has some serious problems with the DMA engine
Jeff Garzik85cd7252006-08-31 00:03:49 -0400134 * when transfers don't run as expected or ATAPI is used. The
Jeff Garzik669a5db2006-08-29 18:12:40 -0400135 * recommended fix is to reset the engine each use using a chip
136 * test register.
137 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400138
Jeff Garzik669a5db2006-08-29 18:12:40 -0400139static void sl82c105_reset_engine(struct ata_port *ap)
140{
141 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
142 u16 val;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400143
Jeff Garzik669a5db2006-08-29 18:12:40 -0400144 pci_read_config_word(pdev, 0x7E, &val);
145 pci_write_config_word(pdev, 0x7E, val | 4);
146 pci_write_config_word(pdev, 0x7E, val & ~4);
147}
148
149/**
150 * sl82c105_bmdma_start - DMA engine begin
151 * @qc: ATA command
152 *
153 * Reset the DMA engine each use as recommended by the errata
Jeff Garzik85cd7252006-08-31 00:03:49 -0400154 * document.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 *
156 * FIXME: if we switch clock at BMDMA start/end we might get better
157 * PIO performance on DMA capable devices.
158 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400159
Jeff Garzik669a5db2006-08-29 18:12:40 -0400160static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
161{
162 struct ata_port *ap = qc->ap;
163
Olaf Hering8361cd72007-02-10 21:36:14 +0100164 udelay(100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 sl82c105_reset_engine(ap);
Olaf Hering8361cd72007-02-10 21:36:14 +0100166 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400167
Jeff Garzik669a5db2006-08-29 18:12:40 -0400168 /* Set the clocks for DMA */
169 sl82c105_configure_dmamode(ap, qc->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400170 /* Activate DMA */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400171 ata_bmdma_start(qc);
172}
173
174/**
175 * sl82c105_bmdma_end - DMA engine stop
176 * @qc: ATA command
177 *
178 * Reset the DMA engine each use as recommended by the errata
179 * document.
180 *
181 * This function is also called to turn off DMA when a timeout occurs
182 * during DMA operation. In both cases we need to reset the engine,
183 * so no actual eng_timeout handler is required.
184 *
185 * We assume bmdma_stop is always called if bmdma_start as called. If
186 * not then we may need to wrap qc_issue.
187 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400188
Jeff Garzik669a5db2006-08-29 18:12:40 -0400189static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
190{
191 struct ata_port *ap = qc->ap;
192
193 ata_bmdma_stop(qc);
194 sl82c105_reset_engine(ap);
Olaf Hering8361cd72007-02-10 21:36:14 +0100195 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400196
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197 /* This will redo the initial setup of the DMA device to matching
198 PIO timings */
Alan16728da2007-02-20 17:51:51 +0000199 sl82c105_set_piomode(ap, qc->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400200}
201
Alan Cox92ba5d02008-01-28 16:08:23 +0000202/**
203 * sl82c105_qc_defer - implement serialization
204 * @qc: command
205 *
206 * We must issue one command per host not per channel because
207 * of the reset bug.
208 *
209 * Q: is the scsi host lock sufficient ?
210 */
211
212static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
213{
214 struct ata_host *host = qc->ap->host;
215 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
216 int rc;
217
Jeff Garzikc85665f2008-05-19 17:56:10 -0400218 /* First apply the usual rules */
Alan Cox92ba5d02008-01-28 16:08:23 +0000219 rc = ata_std_qc_defer(qc);
220 if (rc != 0)
221 return rc;
222
223 /* Now apply serialization rules. Only allow a command if the
224 other channel state machine is idle */
225 if (alt && alt->qc_active)
226 return ATA_DEFER_PORT;
227 return 0;
228}
229
Sergei Shtylyovf7a437d2010-10-08 19:02:13 +0400230static bool sl82c105_sff_irq_check(struct ata_port *ap)
231{
232 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
233 u32 val, mask = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
234
235 pci_read_config_dword(pdev, 0x40, &val);
236
237 return val & mask;
238}
239
Jeff Garzik669a5db2006-08-29 18:12:40 -0400240static struct scsi_host_template sl82c105_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900241 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400242};
243
244static struct ata_port_operations sl82c105_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900245 .inherits = &ata_bmdma_port_ops,
246 .qc_defer = sl82c105_qc_defer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400247 .bmdma_start = sl82c105_bmdma_start,
248 .bmdma_stop = sl82c105_bmdma_stop,
Tejun Heo029cfd62008-03-25 12:22:49 +0900249 .cable_detect = ata_cable_40wire,
250 .set_piomode = sl82c105_set_piomode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900251 .prereset = sl82c105_pre_reset,
Sergei Shtylyovf7a437d2010-10-08 19:02:13 +0400252 .sff_irq_check = sl82c105_sff_irq_check,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400253};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400254
255/**
256 * sl82c105_bridge_revision - find bridge version
257 * @pdev: PCI device for the ATA function
258 *
259 * Locates the PCI bridge associated with the ATA function and
260 * providing it is a Winbond 553 reports the revision. If it cannot
261 * find a revision or the right device it returns -1
262 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400263
Jeff Garzik669a5db2006-08-29 18:12:40 -0400264static int sl82c105_bridge_revision(struct pci_dev *pdev)
265{
266 struct pci_dev *bridge;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400267
268 /*
269 * The bridge should be part of the same device, but function 0.
270 */
271 bridge = pci_get_slot(pdev->bus,
272 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
273 if (!bridge)
274 return -1;
275
276 /*
277 * Make sure it is a Winbond 553 and is an ISA bridge.
278 */
279 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
280 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
281 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
282 pci_dev_put(bridge);
283 return -1;
284 }
285 /*
286 * We need to find function 0's revision, not function 1
287 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400288 pci_dev_put(bridge);
Auke Kok44c10132007-06-08 15:46:36 -0700289 return bridge->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400290}
291
Jeff Garzik85cd7252006-08-31 00:03:49 -0400292
Jeff Garzik669a5db2006-08-29 18:12:40 -0400293static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
294{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200295 static const struct ata_port_info info_dma = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400296 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100297 .pio_mask = ATA_PIO4,
298 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299 .port_ops = &sl82c105_port_ops
300 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200301 static const struct ata_port_info info_early = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400302 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100303 .pio_mask = ATA_PIO4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400304 .port_ops = &sl82c105_port_ops
305 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200306 /* for now use only the first port */
307 const struct ata_port_info *ppi[] = { &info_early,
Alan Cox92ba5d02008-01-28 16:08:23 +0000308 NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309 u32 val;
310 int rev;
Tejun Heof08048e2008-03-25 12:22:47 +0900311 int rc;
312
313 rc = pcim_enable_device(dev);
314 if (rc)
315 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400316
317 rev = sl82c105_bridge_revision(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400318
Jeff Garzik669a5db2006-08-29 18:12:40 -0400319 if (rev == -1)
Joe Perchesa44fec12011-04-15 15:51:58 -0700320 dev_warn(&dev->dev,
321 "pata_sl82c105: Unable to find bridge, disabling DMA\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -0400322 else if (rev <= 5)
Joe Perchesa44fec12011-04-15 15:51:58 -0700323 dev_warn(&dev->dev,
324 "pata_sl82c105: Early bridge revision, no DMA available\n");
Tejun Heo1626aeb2007-05-04 12:43:58 +0200325 else
326 ppi[0] = &info_dma;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400327
Jeff Garzik669a5db2006-08-29 18:12:40 -0400328 pci_read_config_dword(dev, 0x40, &val);
329 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
330 pci_write_config_dword(dev, 0x40, val);
331
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200332 return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400333}
334
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400335static const struct pci_device_id sl82c105[] = {
336 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
337
338 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400339};
340
341static struct pci_driver sl82c105_pci_driver = {
342 .name = DRV_NAME,
343 .id_table = sl82c105,
344 .probe = sl82c105_init_one,
345 .remove = ata_pci_remove_one
346};
347
348static int __init sl82c105_init(void)
349{
350 return pci_register_driver(&sl82c105_pci_driver);
351}
352
Jeff Garzik669a5db2006-08-29 18:12:40 -0400353static void __exit sl82c105_exit(void)
354{
355 pci_unregister_driver(&sl82c105_pci_driver);
356}
357
Jeff Garzik669a5db2006-08-29 18:12:40 -0400358MODULE_AUTHOR("Alan Cox");
359MODULE_DESCRIPTION("low-level driver for Sl82c105");
360MODULE_LICENSE("GPL");
361MODULE_DEVICE_TABLE(pci, sl82c105);
362MODULE_VERSION(DRV_VERSION);
363
364module_init(sl82c105_init);
365module_exit(sl82c105_exit);