Sujeev Dias | dd66ce0 | 2016-09-07 11:35:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __MSM_GPI_H_ |
| 14 | #define __MSM_GPI_H_ |
| 15 | |
| 16 | struct __packed msm_gpi_tre { |
| 17 | u32 dword[4]; |
| 18 | }; |
| 19 | |
| 20 | enum msm_gpi_tre_type { |
| 21 | MSM_GPI_TRE_INVALID = 0x00, |
| 22 | MSM_GPI_TRE_NOP = 0x01, |
| 23 | MSM_GPI_TRE_DMA_W_BUF = 0x10, |
| 24 | MSM_GPI_TRE_DMA_IMMEDIATE = 0x11, |
| 25 | MSM_GPI_TRE_DMA_W_SG_LIST = 0x12, |
| 26 | MSM_GPI_TRE_GO = 0x20, |
| 27 | MSM_GPI_TRE_CONFIG0 = 0x22, |
| 28 | MSM_GPI_TRE_CONFIG1 = 0x23, |
| 29 | MSM_GPI_TRE_CONFIG2 = 0x24, |
| 30 | MSM_GPI_TRE_CONFIG3 = 0x25, |
| 31 | MSM_GPI_TRE_LOCK = 0x30, |
| 32 | MSM_GPI_TRE_UNLOCK = 0x31, |
| 33 | }; |
| 34 | |
| 35 | #define MSM_GPI_TRE_TYPE(tre) ((tre->dword[3] >> 16) & 0xFF) |
| 36 | |
| 37 | /* DMA w. Buffer TRE */ |
| 38 | #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) ((u32)ptr) |
| 39 | #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) ((u32)(ptr >> 32)) |
| 40 | #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length) (length & 0xFFFFFF) |
| 41 | #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(bei, ieot, ieob, ch) ((0x1 << 20) | \ |
| 42 | (0x0 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 43 | #define MSM_GPI_DMA_W_BUFFER_TRE_GET_LEN(tre) (tre->dword[2] & 0xFFFFFF) |
| 44 | #define MSM_GPI_DMA_W_BUFFER_TRE_SET_LEN(tre, length) (tre->dword[2] = \ |
| 45 | MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length)) |
| 46 | |
| 47 | /* DMA Immediate TRE */ |
| 48 | #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD0(d3, d2, d1, d0) ((d3 << 24) | \ |
| 49 | (d2 << 16) | (d1 << 8) | (d0)) |
| 50 | #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD1(d4, d5, d6, d7) ((d7 << 24) | \ |
| 51 | (d6 << 16) | (d5 << 8) | (d4)) |
| 52 | #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD2(length) (length & 0xF) |
| 53 | #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(bei, ieot, ieob, ch) ((0x1 << 20) | \ |
| 54 | (0x1 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 55 | #define MSM_GPI_DMA_IMMEDIATE_TRE_GET_LEN(tre) (tre->dword[2] & 0xF) |
| 56 | |
| 57 | /* DMA w. Scatter/Gather List TRE */ |
| 58 | #define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) ((u32)ptr) |
| 59 | #define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) ((u32)(ptr >> 32)) |
| 60 | #define MSM_GPI_SG_LIST_TRE_DWORD2(length) (length & 0xFFFF) |
| 61 | #define MSM_GPI_SG_LIST_TRE_DWORD3(bei, ieot, ieob, ch) ((0x1 << 20) | \ |
| 62 | (0x2 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 63 | |
| 64 | /* SG Element */ |
| 65 | #define MSM_GPI_SG_ELEMENT_DWORD0(ptr) ((u32)ptr) |
| 66 | #define MSM_GPI_SG_ELEMENT_DWORD1(ptr) ((u32)(ptr >> 32)) |
| 67 | #define MSM_GSI_SG_ELEMENT_DWORD2(length) (length & 0xFFFFF) |
| 68 | #define MSM_GSI_SG_ELEMENT_DWORD3 (0) |
| 69 | |
| 70 | /* Config2 TRE */ |
| 71 | #define GPI_CONFIG2_TRE_DWORD0(gr, txp) ((gr << 20) | (txp)) |
| 72 | #define GPI_CONFIG2_TRE_DWORD1(txp) (txp) |
| 73 | #define GPI_CONFIG2_TRE_DWORD2 (0) |
| 74 | #define GPI_CONFIG2_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 75 | (0x4 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 76 | |
| 77 | /* Config3 TRE */ |
| 78 | #define GPI_CONFIG3_TRE_DWORD0(rxp) (rxp) |
| 79 | #define GPI_CONFIG3_TRE_DWORD1(rxp) (rxp) |
| 80 | #define GPI_CONFIG3_TRE_DWORD2 (0) |
| 81 | #define GPI_CONFIG3_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 82 | (0x5 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 83 | |
| 84 | /* SPI Go TRE */ |
| 85 | #define MSM_GPI_SPI_GO_TRE_DWORD0(flags, cs, command) ((flags << 24) | \ |
| 86 | (cs << 8) | command) |
| 87 | #define MSM_GPI_SPI_GO_TRE_DWORD1 (0) |
| 88 | #define MSM_GPI_SPI_GO_TRE_DWORD2(rx_len) (rx_len) |
| 89 | #define MSM_GPI_SPI_GO_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 90 | (0x0 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 91 | |
| 92 | /* SPI Config0 TRE */ |
| 93 | #define MSM_GPI_SPI_CONFIG0_TRE_DWORD0(pack, flags, word_size) ((pack << 24) | \ |
| 94 | (flags << 8) | word_size) |
| 95 | #define MSM_GPI_SPI_CONFIG0_TRE_DWORD1(it_del, cs_clk_del, iw_del) \ |
| 96 | ((it_del << 16) | (cs_clk_del << 8) | iw_del) |
| 97 | #define MSM_GPI_SPI_CONFIG0_TRE_DWORD2(clk_src, clk_div) ((clk_src << 16) | \ |
| 98 | clk_div) |
| 99 | #define MSM_GPI_SPI_CONFIG0_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 100 | (0x2 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 101 | |
| 102 | /* UART Go TRE */ |
| 103 | #define MSM_GPI_UART_GO_TRE_DWORD0(en_hunt, command) ((en_hunt << 8) | command) |
| 104 | #define MSM_GPI_UART_GO_TRE_DWORD1 (0) |
| 105 | #define MSM_GPI_UART_GO_TRE_DWORD2 (0) |
| 106 | #define MSM_GPI_UART_GO_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 107 | (0x0 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 108 | |
| 109 | /* UART Config0 TRE */ |
| 110 | #define MSM_GPI_UART_CONFIG0_TRE_DWORD0(pack, hunt, flags, parity, sbl, size) \ |
| 111 | ((pack << 24) | (hunt << 16) | (flags << 8) | (parity << 5) | \ |
| 112 | (sbl << 3) | size) |
| 113 | #define MSM_GPI_UART_CONFIG0_TRE_DWORD1(rfr_level, rx_stale) \ |
| 114 | ((rfr_level << 24) | rx_stale) |
| 115 | #define MSM_GPI_UART_CONFIG0_TRE_DWORD2(clk_source, clk_div) \ |
| 116 | ((clk_source << 16) | clk_div) |
| 117 | #define MSM_GPI_UART_CONFIG0_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 118 | (0x2 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 119 | |
| 120 | /* I2C GO TRE */ |
| 121 | #define MSM_GPI_I2C_GO_TRE_DWORD0(flags, slave, opcode) \ |
| 122 | ((flags << 24) | (slave << 8) | opcode) |
| 123 | #define MSM_GPI_I2C_GO_TRE_DWORD1 (0) |
| 124 | #define MSM_GPI_I2C_GO_TRE_DWORD2(rx_len) (rx_len) |
| 125 | #define MSM_GPI_I2C_GO_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 126 | (0x0 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 127 | |
| 128 | /* I2C Config0 TRE */ |
| 129 | #define MSM_GPI_I2C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \ |
| 130 | ((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low) |
| 131 | #define MSM_GPI_I2C_CONFIG0_TRE_DWORD1(inter_delay, noise_rej) \ |
| 132 | ((inter_delay << 16) | noise_rej) |
| 133 | #define MSM_GPI_I2C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \ |
| 134 | ((clk_src << 16) | clk_div) |
| 135 | #define MSM_GPI_I2C_CONFIG0_TRE_DWORD3(bei, ieot, ieob, ch) ((0x2 << 20) | \ |
| 136 | (0x2 << 16) | (bei << 10) | (ieot << 9) | (ieob << 8) | ch) |
| 137 | |
| 138 | /* cmds to perform by using dmaengine_slave_config() */ |
| 139 | enum msm_gpi_ctrl_cmd { |
| 140 | MSM_GPI_INIT, |
| 141 | MSM_GPI_CMD_UART_SW_STALE, |
| 142 | MSM_GPI_CMD_UART_RFR_READY, |
| 143 | MSM_GPI_CMD_UART_RFR_NOT_READY, |
| 144 | }; |
| 145 | |
| 146 | enum msm_gpi_cb_event { |
| 147 | /* These events are hardware generated events */ |
| 148 | MSM_GPI_QUP_NOTIFY, |
| 149 | MSM_GPI_QUP_ERROR, /* global error */ |
| 150 | MSM_GPI_QUP_CH_ERROR, /* channel specific error */ |
| 151 | MSM_GPI_QUP_FW_ERROR, /* unhandled error */ |
| 152 | /* These events indicate a software bug */ |
| 153 | MSM_GPI_QUP_PENDING_EVENT, |
| 154 | MSM_GPI_QUP_EOT_DESC_MISMATCH, |
| 155 | MSM_GPI_QUP_SW_ERROR, |
| 156 | MSM_GPI_QUP_MAX_EVENT, |
| 157 | }; |
| 158 | |
| 159 | struct msm_gpi_error_log { |
| 160 | u32 routine; |
| 161 | u32 type; |
| 162 | u32 error_code; |
| 163 | }; |
| 164 | |
| 165 | struct msm_gpi_cb { |
| 166 | enum msm_gpi_cb_event cb_event; |
| 167 | u64 status; |
| 168 | u64 timestamp; |
| 169 | u64 count; |
| 170 | struct msm_gpi_error_log error_log; |
| 171 | }; |
| 172 | |
| 173 | struct gpi_client_info { |
| 174 | /* |
| 175 | * memory for msm_gpi_cb is released after callback, clients shall |
| 176 | * save any required data for post processing after returning |
| 177 | * from callback |
| 178 | */ |
| 179 | void (*callback)(struct dma_chan *chan, |
| 180 | struct msm_gpi_cb const *msm_gpi_cb, |
| 181 | void *cb_param); |
| 182 | void *cb_param; |
| 183 | }; |
| 184 | |
| 185 | /* |
| 186 | * control structure to config gpi dma engine via dmaengine_slave_config() |
| 187 | * dma_chan.private should point to msm_gpi_ctrl structure |
| 188 | */ |
| 189 | struct msm_gpi_ctrl { |
| 190 | enum msm_gpi_ctrl_cmd cmd; |
| 191 | union { |
| 192 | struct gpi_client_info init; |
| 193 | }; |
| 194 | }; |
| 195 | |
| 196 | enum msm_gpi_tce_code { |
| 197 | MSM_GPI_TCE_SUCCESS = 1, |
| 198 | MSM_GPI_TCE_EOT = 2, |
| 199 | MSM_GPI_TCE_EOB = 4, |
| 200 | MSM_GPI_TCE_UNEXP_ERR = 16, |
| 201 | }; |
| 202 | |
| 203 | /* |
| 204 | * gpi specific callback parameters to pass between gpi client and gpi engine. |
| 205 | * client shall set async_desc.callback_parm to msm_gpi_dma_async_tx_cb_param |
| 206 | */ |
| 207 | struct msm_gpi_dma_async_tx_cb_param { |
| 208 | u32 length; |
| 209 | enum msm_gpi_tce_code completion_code; /* TCE event code */ |
| 210 | u32 status; |
| 211 | void *userdata; |
| 212 | }; |
| 213 | |
| 214 | #endif |