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gerrit-public.fairphone.software / kernel / msm-4.9 / 6eebee625544ac4ef1d805da942f463275bd6caa / . / arch / blackfin / include / asm / mem_init.h
blob: 4179e329b9c931d94521b2f2a1c457a4c59090e3 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]2 * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]3 *
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]4 * Copyright 2004-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]5 *
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]6 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]7 */
8
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]9#if defined(EBIU_SDGCTL)
10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
13 defined(CONFIG_MEM_GENERIC_BOARD) || \
14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \
15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
Sonic Zhang49345402009-01-07 23:14:38 +0800[diff] [blame]16 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
17 defined(CONFIG_MEM_MT48LC32M8A2_75)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]18#if (CONFIG_SCLK_HZ > 119402985)
19#define SDRAM_tRP TRP_2
20#define SDRAM_tRP_num 2
21#define SDRAM_tRAS TRAS_7
22#define SDRAM_tRAS_num 7
23#define SDRAM_tRCD TRCD_2
24#define SDRAM_tWR TWR_2
25#endif
26#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
27#define SDRAM_tRP TRP_2
28#define SDRAM_tRP_num 2
29#define SDRAM_tRAS TRAS_6
30#define SDRAM_tRAS_num 6
31#define SDRAM_tRCD TRCD_2
32#define SDRAM_tWR TWR_2
33#endif
34#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
35#define SDRAM_tRP TRP_2
36#define SDRAM_tRP_num 2
37#define SDRAM_tRAS TRAS_5
38#define SDRAM_tRAS_num 5
39#define SDRAM_tRCD TRCD_2
40#define SDRAM_tWR TWR_2
41#endif
42#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
43#define SDRAM_tRP TRP_2
44#define SDRAM_tRP_num 2
45#define SDRAM_tRAS TRAS_4
46#define SDRAM_tRAS_num 4
47#define SDRAM_tRCD TRCD_2
48#define SDRAM_tWR TWR_2
49#endif
50#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
51#define SDRAM_tRP TRP_2
52#define SDRAM_tRP_num 2
53#define SDRAM_tRAS TRAS_3
54#define SDRAM_tRAS_num 3
55#define SDRAM_tRCD TRCD_2
56#define SDRAM_tWR TWR_2
57#endif
58#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
59#define SDRAM_tRP TRP_1
60#define SDRAM_tRP_num 1
61#define SDRAM_tRAS TRAS_4
Graf Yang8f580f72009-06-18 04:21:39 +0000[diff] [blame]62#define SDRAM_tRAS_num 4
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]63#define SDRAM_tRCD TRCD_1
64#define SDRAM_tWR TWR_2
65#endif
66#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
67#define SDRAM_tRP TRP_1
68#define SDRAM_tRP_num 1
69#define SDRAM_tRAS TRAS_3
70#define SDRAM_tRAS_num 3
71#define SDRAM_tRCD TRCD_1
72#define SDRAM_tWR TWR_2
73#endif
74#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
75#define SDRAM_tRP TRP_1
76#define SDRAM_tRP_num 1
77#define SDRAM_tRAS TRAS_2
78#define SDRAM_tRAS_num 2
79#define SDRAM_tRCD TRCD_1
80#define SDRAM_tWR TWR_2
81#endif
82#if (CONFIG_SCLK_HZ <= 29850746)
83#define SDRAM_tRP TRP_1
84#define SDRAM_tRP_num 1
85#define SDRAM_tRAS TRAS_1
86#define SDRAM_tRAS_num 1
87#define SDRAM_tRCD TRCD_1
88#define SDRAM_tWR TWR_2
89#endif
90#endif
91
Graf Yangee48efb2009-06-18 04:32:04 +0000[diff] [blame]92/*
93 * The BF526-EZ-Board changed SDRAM chips between revisions,
94 * so we use below timings to accommodate both.
95 */
96#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
97#if (CONFIG_SCLK_HZ > 119402985)
98#define SDRAM_tRP TRP_2
99#define SDRAM_tRP_num 2
100#define SDRAM_tRAS TRAS_8
101#define SDRAM_tRAS_num 8
102#define SDRAM_tRCD TRCD_2
103#define SDRAM_tWR TWR_2
104#endif
105#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
106#define SDRAM_tRP TRP_2
107#define SDRAM_tRP_num 2
108#define SDRAM_tRAS TRAS_7
109#define SDRAM_tRAS_num 7
110#define SDRAM_tRCD TRCD_2
111#define SDRAM_tWR TWR_2
112#endif
113#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
114#define SDRAM_tRP TRP_2
115#define SDRAM_tRP_num 2
116#define SDRAM_tRAS TRAS_6
117#define SDRAM_tRAS_num 6
118#define SDRAM_tRCD TRCD_2
119#define SDRAM_tWR TWR_2
120#endif
121#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
122#define SDRAM_tRP TRP_2
123#define SDRAM_tRP_num 2
124#define SDRAM_tRAS TRAS_5
125#define SDRAM_tRAS_num 5
126#define SDRAM_tRCD TRCD_2
127#define SDRAM_tWR TWR_2
128#endif
129#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
130#define SDRAM_tRP TRP_2
131#define SDRAM_tRP_num 2
132#define SDRAM_tRAS TRAS_4
133#define SDRAM_tRAS_num 4
134#define SDRAM_tRCD TRCD_2
135#define SDRAM_tWR TWR_2
136#endif
137#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
138#define SDRAM_tRP TRP_2
139#define SDRAM_tRP_num 2
140#define SDRAM_tRAS TRAS_4
141#define SDRAM_tRAS_num 4
142#define SDRAM_tRCD TRCD_1
143#define SDRAM_tWR TWR_2
144#endif
145#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
146#define SDRAM_tRP TRP_2
147#define SDRAM_tRP_num 2
148#define SDRAM_tRAS TRAS_3
149#define SDRAM_tRAS_num 3
150#define SDRAM_tRCD TRCD_1
151#define SDRAM_tWR TWR_2
152#endif
153#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
154#define SDRAM_tRP TRP_1
155#define SDRAM_tRP_num 1
156#define SDRAM_tRAS TRAS_3
157#define SDRAM_tRAS_num 3
158#define SDRAM_tRCD TRCD_1
159#define SDRAM_tWR TWR_2
160#endif
161#if (CONFIG_SCLK_HZ <= 29850746)
162#define SDRAM_tRP TRP_1
163#define SDRAM_tRP_num 1
164#define SDRAM_tRAS TRAS_2
165#define SDRAM_tRAS_num 2
166#define SDRAM_tRCD TRCD_1
167#define SDRAM_tWR TWR_2
168#endif
169#endif
170
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]171#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
172 defined(CONFIG_MEM_MT48LC8M32B2B5_7)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]173 /*SDRAM INFORMATION: */
174#define SDRAM_Tref 64 /* Refresh period in milliseconds */
175#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
176#define SDRAM_CL CL_3
177#endif
178
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]179#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
180 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
181 defined(CONFIG_MEM_GENERIC_BOARD) || \
182 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
Sonic Zhang49345402009-01-07 23:14:38 +0800[diff] [blame]183 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
184 defined(CONFIG_MEM_MT48LC32M8A2_75)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]185 /*SDRAM INFORMATION: */
186#define SDRAM_Tref 64 /* Refresh period in milliseconds */
187#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
188#define SDRAM_CL CL_3
189#endif
190
Graf Yangee48efb2009-06-18 04:32:04 +0000[diff] [blame]191#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
192 /*SDRAM INFORMATION: */
193#define SDRAM_Tref 64 /* Refresh period in milliseconds */
194#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
195#define SDRAM_CL CL_2
196#endif
197
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]198
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]199#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]200/* Equation from section 17 (p17-46) of BF533 HRM */
201#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
202
203/* Enable SCLK Out */
Michael Hennerich33169312009-02-04 16:49:45 +0800[diff] [blame]204#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]205#else
206#define mem_SDRRC CONFIG_MEM_SDRRC
207#define mem_SDGCTL CONFIG_MEM_SDGCTL
208#endif
209#endif
210
211
212#if defined(EBIU_DDRCTL0)
213#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
214#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
215#define DDR_CLK_HZ(x) (1000*1000*1000/x)
216
217#if defined(CONFIG_MEM_MT46V32M16_6T)
218#define DDR_SIZE DEVSZ_512
219#define DDR_WIDTH DEVWD_16
220#define DDR_MAX_tCK 13
221
222#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
223#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
224#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
225#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
226#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
227
228#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
229#define DDR_tWTR DDR_TWTR(1)
230#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
231#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
232#endif
233
234#if defined(CONFIG_MEM_MT46V32M16_5B)
235#define DDR_SIZE DEVSZ_512
236#define DDR_WIDTH DEVWD_16
237#define DDR_MAX_tCK 13
238
239#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
240#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
241#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
242#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
243#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
244
245#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
246#define DDR_tWTR DDR_TWTR(2)
247#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
248#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
249#endif
250
251#if defined(CONFIG_MEM_GENERIC_BOARD)
252#define DDR_SIZE DEVSZ_512
253#define DDR_WIDTH DEVWD_16
254#define DDR_MAX_tCK 13
255
256#define DDR_tRCD DDR_TRCD(3)
257#define DDR_tWTR DDR_TWTR(2)
258#define DDR_tWR DDR_TWR(2)
259#define DDR_tMRD DDR_TMRD(2)
260#define DDR_tRP DDR_TRP(3)
261#define DDR_tRAS DDR_TRAS(7)
262#define DDR_tRC DDR_TRC(10)
263#define DDR_tRFC DDR_TRFC(12)
264#define DDR_tREFI DDR_TREFI(1288)
265#endif
266
267#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
268# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
269#elif(CONFIG_SCLK_HZ <= 133333333)
270# define DDR_CL CL_2
271#else
272# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
273#endif
274
275#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
276#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
277#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
278 | DDR_tMRD | DDR_tWR | DDR_tRCD)
279#define mem_DDRCTL2 DDR_CL
280#else
281#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
282#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
283#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
284#endif
285#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]286
287#if defined CONFIG_CLKIN_HALF
288#define CLKIN_HALF 1
289#else
290#define CLKIN_HALF 0
291#endif
292
293#if defined CONFIG_PLL_BYPASS
294#define PLL_BYPASS 1
295#else
296#define PLL_BYPASS 0
297#endif
298
299/***************************************Currently Not Being Used *********************************/
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]300
301#if defined(CONFIG_FLASH_SPEED_BWAT) && \
302defined(CONFIG_FLASH_SPEED_BRAT) && \
303defined(CONFIG_FLASH_SPEED_BHT) && \
304defined(CONFIG_FLASH_SPEED_BST) && \
305defined(CONFIG_FLASH_SPEED_BTT)
306
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]307#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
308#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
309#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
310#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
311#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
312
313#if (flash_EBIU_AMBCTL_TT > 3)
314#define flash_EBIU_AMBCTL0_TT B0TT_4
315#endif
316#if (flash_EBIU_AMBCTL_TT == 3)
317#define flash_EBIU_AMBCTL0_TT B0TT_3
318#endif
319#if (flash_EBIU_AMBCTL_TT == 2)
320#define flash_EBIU_AMBCTL0_TT B0TT_2
321#endif
322#if (flash_EBIU_AMBCTL_TT < 2)
323#define flash_EBIU_AMBCTL0_TT B0TT_1
324#endif
325
326#if (flash_EBIU_AMBCTL_ST > 3)
327#define flash_EBIU_AMBCTL0_ST B0ST_4
328#endif
329#if (flash_EBIU_AMBCTL_ST == 3)
330#define flash_EBIU_AMBCTL0_ST B0ST_3
331#endif
332#if (flash_EBIU_AMBCTL_ST == 2)
333#define flash_EBIU_AMBCTL0_ST B0ST_2
334#endif
335#if (flash_EBIU_AMBCTL_ST < 2)
336#define flash_EBIU_AMBCTL0_ST B0ST_1
337#endif
338
339#if (flash_EBIU_AMBCTL_HT > 2)
340#define flash_EBIU_AMBCTL0_HT B0HT_3
341#endif
342#if (flash_EBIU_AMBCTL_HT == 2)
343#define flash_EBIU_AMBCTL0_HT B0HT_2
344#endif
345#if (flash_EBIU_AMBCTL_HT == 1)
346#define flash_EBIU_AMBCTL0_HT B0HT_1
347#endif
348#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
349#define flash_EBIU_AMBCTL0_HT B0HT_0
350#endif
351#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
352#define flash_EBIU_AMBCTL0_HT B0HT_1
353#endif
354
355#if (flash_EBIU_AMBCTL_WAT > 14)
356#define flash_EBIU_AMBCTL0_WAT B0WAT_15
357#endif
358#if (flash_EBIU_AMBCTL_WAT == 14)
359#define flash_EBIU_AMBCTL0_WAT B0WAT_14
360#endif
361#if (flash_EBIU_AMBCTL_WAT == 13)
362#define flash_EBIU_AMBCTL0_WAT B0WAT_13
363#endif
364#if (flash_EBIU_AMBCTL_WAT == 12)
365#define flash_EBIU_AMBCTL0_WAT B0WAT_12
366#endif
367#if (flash_EBIU_AMBCTL_WAT == 11)
368#define flash_EBIU_AMBCTL0_WAT B0WAT_11
369#endif
370#if (flash_EBIU_AMBCTL_WAT == 10)
371#define flash_EBIU_AMBCTL0_WAT B0WAT_10
372#endif
373#if (flash_EBIU_AMBCTL_WAT == 9)
374#define flash_EBIU_AMBCTL0_WAT B0WAT_9
375#endif
376#if (flash_EBIU_AMBCTL_WAT == 8)
377#define flash_EBIU_AMBCTL0_WAT B0WAT_8
378#endif
379#if (flash_EBIU_AMBCTL_WAT == 7)
380#define flash_EBIU_AMBCTL0_WAT B0WAT_7
381#endif
382#if (flash_EBIU_AMBCTL_WAT == 6)
383#define flash_EBIU_AMBCTL0_WAT B0WAT_6
384#endif
385#if (flash_EBIU_AMBCTL_WAT == 5)
386#define flash_EBIU_AMBCTL0_WAT B0WAT_5
387#endif
388#if (flash_EBIU_AMBCTL_WAT == 4)
389#define flash_EBIU_AMBCTL0_WAT B0WAT_4
390#endif
391#if (flash_EBIU_AMBCTL_WAT == 3)
392#define flash_EBIU_AMBCTL0_WAT B0WAT_3
393#endif
394#if (flash_EBIU_AMBCTL_WAT == 2)
395#define flash_EBIU_AMBCTL0_WAT B0WAT_2
396#endif
397#if (flash_EBIU_AMBCTL_WAT == 1)
398#define flash_EBIU_AMBCTL0_WAT B0WAT_1
399#endif
400
401#if (flash_EBIU_AMBCTL_RAT > 14)
402#define flash_EBIU_AMBCTL0_RAT B0RAT_15
403#endif
404#if (flash_EBIU_AMBCTL_RAT == 14)
405#define flash_EBIU_AMBCTL0_RAT B0RAT_14
406#endif
407#if (flash_EBIU_AMBCTL_RAT == 13)
408#define flash_EBIU_AMBCTL0_RAT B0RAT_13
409#endif
410#if (flash_EBIU_AMBCTL_RAT == 12)
411#define flash_EBIU_AMBCTL0_RAT B0RAT_12
412#endif
413#if (flash_EBIU_AMBCTL_RAT == 11)
414#define flash_EBIU_AMBCTL0_RAT B0RAT_11
415#endif
416#if (flash_EBIU_AMBCTL_RAT == 10)
417#define flash_EBIU_AMBCTL0_RAT B0RAT_10
418#endif
419#if (flash_EBIU_AMBCTL_RAT == 9)
420#define flash_EBIU_AMBCTL0_RAT B0RAT_9
421#endif
422#if (flash_EBIU_AMBCTL_RAT == 8)
423#define flash_EBIU_AMBCTL0_RAT B0RAT_8
424#endif
425#if (flash_EBIU_AMBCTL_RAT == 7)
426#define flash_EBIU_AMBCTL0_RAT B0RAT_7
427#endif
428#if (flash_EBIU_AMBCTL_RAT == 6)
429#define flash_EBIU_AMBCTL0_RAT B0RAT_6
430#endif
431#if (flash_EBIU_AMBCTL_RAT == 5)
432#define flash_EBIU_AMBCTL0_RAT B0RAT_5
433#endif
434#if (flash_EBIU_AMBCTL_RAT == 4)
435#define flash_EBIU_AMBCTL0_RAT B0RAT_4
436#endif
437#if (flash_EBIU_AMBCTL_RAT == 3)
438#define flash_EBIU_AMBCTL0_RAT B0RAT_3
439#endif
440#if (flash_EBIU_AMBCTL_RAT == 2)
441#define flash_EBIU_AMBCTL0_RAT B0RAT_2
442#endif
443#if (flash_EBIU_AMBCTL_RAT == 1)
444#define flash_EBIU_AMBCTL0_RAT B0RAT_1
445#endif
446
447#define flash_EBIU_AMBCTL0 \
448 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
449 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800[diff] [blame]450#endif