Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 1 | /* |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 2 | * Copyright (C) 1994 Linus Torvalds |
| 3 | * |
| 4 | * Cyrix stuff, June 1998 by: |
| 5 | * - Rafael R. Reilova (moved everything from head.S), |
| 6 | * <rreilova@ececs.uc.edu> |
| 7 | * - Channing Corn (tests & fixes), |
| 8 | * - Andrew D. Balsa (code cleanup). |
| 9 | */ |
| 10 | #include <linux/init.h> |
| 11 | #include <linux/utsname.h> |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 12 | #include <linux/cpu.h> |
Andi Kleen | a1745ad | 2018-01-25 15:50:28 -0800 | [diff] [blame] | 13 | #include <linux/module.h> |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 14 | #include <linux/nospec.h> |
| 15 | #include <linux/prctl.h> |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 16 | |
Thomas Gleixner | 7a2d235 | 2018-04-29 15:01:37 +0200 | [diff] [blame] | 17 | #include <asm/spec-ctrl.h> |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 18 | #include <asm/cmdline.h> |
Josh Triplett | 91eb1b7 | 2007-07-31 00:39:20 -0700 | [diff] [blame] | 19 | #include <asm/bugs.h> |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 20 | #include <asm/processor.h> |
Dave Jones | 7ebad70 | 2008-01-30 13:30:39 +0100 | [diff] [blame] | 21 | #include <asm/processor-flags.h> |
Ingo Molnar | 952f07e | 2015-04-26 16:56:05 +0200 | [diff] [blame] | 22 | #include <asm/fpu/internal.h> |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 23 | #include <asm/msr.h> |
| 24 | #include <asm/paravirt.h> |
| 25 | #include <asm/alternative.h> |
Borislav Petkov | 56eff36 | 2016-10-24 19:38:43 +0200 | [diff] [blame] | 26 | #include <asm/pgtable.h> |
| 27 | #include <asm/cacheflush.h> |
David Woodhouse | abf67b1 | 2018-01-12 17:49:25 +0000 | [diff] [blame] | 28 | #include <asm/intel-family.h> |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 29 | |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 30 | static void __init spectre_v2_select_mitigation(void); |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 31 | static void __init ssb_select_mitigation(void); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 32 | |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 33 | /* |
| 34 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any |
| 35 | * writes to SPEC_CTRL contain whatever reserved bits have been set. |
| 36 | */ |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 37 | u64 __ro_after_init x86_spec_ctrl_base; |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 38 | |
Konrad Rzeszutek Wilk | 99b1311 | 2018-04-25 22:04:23 -0400 | [diff] [blame] | 39 | /* |
| 40 | * The vendor and possibly platform specific bits which can be modified in |
| 41 | * x86_spec_ctrl_base. |
| 42 | */ |
| 43 | static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS; |
| 44 | |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 45 | /* |
| 46 | * AMD specific MSR info for Speculative Store Bypass control. |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 47 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 48 | */ |
| 49 | u64 __ro_after_init x86_amd_ls_cfg_base; |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 50 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 51 | |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 52 | void __init check_bugs(void) |
| 53 | { |
| 54 | identify_boot_cpu(); |
Borislav Petkov | 55a36b6 | 2013-04-08 17:57:44 +0200 | [diff] [blame] | 55 | |
Borislav Petkov | 56eff36 | 2016-10-24 19:38:43 +0200 | [diff] [blame] | 56 | if (!IS_ENABLED(CONFIG_SMP)) { |
| 57 | pr_info("CPU: "); |
| 58 | print_cpu_info(&boot_cpu_data); |
| 59 | } |
| 60 | |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 61 | /* |
| 62 | * Read the SPEC_CTRL MSR to account for reserved bits which may |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 63 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
| 64 | * init code as it is not enumerated and depends on the family. |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 65 | */ |
| 66 | if (boot_cpu_has(X86_FEATURE_IBRS)) |
| 67 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
| 68 | |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 69 | /* Select the proper spectre mitigation before patching alternatives */ |
| 70 | spectre_v2_select_mitigation(); |
| 71 | |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 72 | /* |
| 73 | * Select proper mitigation for any exposure to the Speculative Store |
| 74 | * Bypass vulnerability. |
| 75 | */ |
| 76 | ssb_select_mitigation(); |
| 77 | |
Borislav Petkov | 56eff36 | 2016-10-24 19:38:43 +0200 | [diff] [blame] | 78 | #ifdef CONFIG_X86_32 |
Borislav Petkov | 55a36b6 | 2013-04-08 17:57:44 +0200 | [diff] [blame] | 79 | /* |
| 80 | * Check whether we are able to run this kernel safely on SMP. |
| 81 | * |
| 82 | * - i386 is no longer supported. |
| 83 | * - In order to run on anything without a TSC, we need to be |
| 84 | * compiled for a i486. |
| 85 | */ |
| 86 | if (boot_cpu_data.x86 < 4) |
| 87 | panic("Kernel requires i486+ for 'invlpg' and other features"); |
| 88 | |
Miklos Vajna | bfe4bb1 | 2008-05-17 22:48:13 +0200 | [diff] [blame] | 89 | init_utsname()->machine[1] = |
| 90 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 91 | alternative_instructions(); |
Suresh Siddha | 304bced | 2012-08-24 14:13:02 -0700 | [diff] [blame] | 92 | |
Ingo Molnar | 4d16409 | 2015-04-22 13:44:25 +0200 | [diff] [blame] | 93 | fpu__init_check_bugs(); |
Borislav Petkov | 56eff36 | 2016-10-24 19:38:43 +0200 | [diff] [blame] | 94 | #else /* CONFIG_X86_64 */ |
| 95 | alternative_instructions(); |
| 96 | |
| 97 | /* |
| 98 | * Make sure the first 2MB area is not mapped by huge pages |
| 99 | * There are typically fixed size MTRRs in there and overlapping |
| 100 | * MTRRs into large pages causes slow downs. |
| 101 | * |
| 102 | * Right now we don't do that with gbpages because there seems |
| 103 | * very little benefit for that case. |
| 104 | */ |
| 105 | if (!direct_gbpages) |
| 106 | set_memory_4k((unsigned long)__va(0), 1); |
| 107 | #endif |
Jeremy Fitzhardinge | 1353ebb | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 108 | } |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 109 | |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 110 | /* The kernel command line selection */ |
| 111 | enum spectre_v2_mitigation_cmd { |
| 112 | SPECTRE_V2_CMD_NONE, |
| 113 | SPECTRE_V2_CMD_AUTO, |
| 114 | SPECTRE_V2_CMD_FORCE, |
| 115 | SPECTRE_V2_CMD_RETPOLINE, |
| 116 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, |
| 117 | SPECTRE_V2_CMD_RETPOLINE_AMD, |
| 118 | }; |
| 119 | |
| 120 | static const char *spectre_v2_strings[] = { |
| 121 | [SPECTRE_V2_NONE] = "Vulnerable", |
| 122 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", |
| 123 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", |
| 124 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", |
| 125 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", |
| 126 | }; |
| 127 | |
| 128 | #undef pr_fmt |
Borislav Petkov | 557cbfa | 2018-01-26 13:11:39 +0100 | [diff] [blame] | 129 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 130 | |
Kees Cook | ea055f7 | 2018-05-03 15:03:30 -0700 | [diff] [blame] | 131 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
| 132 | SPECTRE_V2_NONE; |
Andi Kleen | a1745ad | 2018-01-25 15:50:28 -0800 | [diff] [blame] | 133 | |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 134 | void x86_spec_ctrl_set(u64 val) |
| 135 | { |
Konrad Rzeszutek Wilk | 99b1311 | 2018-04-25 22:04:23 -0400 | [diff] [blame] | 136 | if (val & x86_spec_ctrl_mask) |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 137 | WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); |
| 138 | else |
| 139 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); |
| 140 | } |
| 141 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); |
| 142 | |
| 143 | u64 x86_spec_ctrl_get_default(void) |
| 144 | { |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 145 | u64 msrval = x86_spec_ctrl_base; |
| 146 | |
| 147 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 148 | msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 149 | return msrval; |
Konrad Rzeszutek Wilk | 0f5dd65 | 2018-04-25 22:04:18 -0400 | [diff] [blame] | 150 | } |
| 151 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default); |
| 152 | |
Konrad Rzeszutek Wilk | cf21f58 | 2018-04-25 22:04:19 -0400 | [diff] [blame] | 153 | void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl) |
| 154 | { |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 155 | u64 host = x86_spec_ctrl_base; |
| 156 | |
Konrad Rzeszutek Wilk | cf21f58 | 2018-04-25 22:04:19 -0400 | [diff] [blame] | 157 | if (!boot_cpu_has(X86_FEATURE_IBRS)) |
| 158 | return; |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 159 | |
| 160 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 161 | host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 162 | |
| 163 | if (host != guest_spec_ctrl) |
Konrad Rzeszutek Wilk | cf21f58 | 2018-04-25 22:04:19 -0400 | [diff] [blame] | 164 | wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl); |
| 165 | } |
| 166 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest); |
| 167 | |
| 168 | void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl) |
| 169 | { |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 170 | u64 host = x86_spec_ctrl_base; |
| 171 | |
Konrad Rzeszutek Wilk | cf21f58 | 2018-04-25 22:04:19 -0400 | [diff] [blame] | 172 | if (!boot_cpu_has(X86_FEATURE_IBRS)) |
| 173 | return; |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 174 | |
| 175 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 176 | host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags); |
Thomas Gleixner | 89c6e9b | 2018-04-29 15:21:42 +0200 | [diff] [blame] | 177 | |
| 178 | if (host != guest_spec_ctrl) |
| 179 | wrmsrl(MSR_IA32_SPEC_CTRL, host); |
Konrad Rzeszutek Wilk | cf21f58 | 2018-04-25 22:04:19 -0400 | [diff] [blame] | 180 | } |
| 181 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host); |
| 182 | |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 183 | static void x86_amd_ssb_disable(void) |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 184 | { |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 185 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 186 | |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 187 | if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 188 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
| 189 | } |
| 190 | |
Andi Kleen | a1745ad | 2018-01-25 15:50:28 -0800 | [diff] [blame] | 191 | #ifdef RETPOLINE |
Thomas Gleixner | 9891122 | 2018-01-27 15:45:14 +0100 | [diff] [blame] | 192 | static bool spectre_v2_bad_module; |
| 193 | |
Andi Kleen | a1745ad | 2018-01-25 15:50:28 -0800 | [diff] [blame] | 194 | bool retpoline_module_ok(bool has_retpoline) |
| 195 | { |
| 196 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) |
| 197 | return true; |
| 198 | |
Colin Ian King | f67e05d | 2018-01-30 19:32:18 +0000 | [diff] [blame] | 199 | pr_err("System may be vulnerable to spectre v2\n"); |
Andi Kleen | a1745ad | 2018-01-25 15:50:28 -0800 | [diff] [blame] | 200 | spectre_v2_bad_module = true; |
| 201 | return false; |
| 202 | } |
Thomas Gleixner | 9891122 | 2018-01-27 15:45:14 +0100 | [diff] [blame] | 203 | |
| 204 | static inline const char *spectre_v2_module_string(void) |
| 205 | { |
| 206 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; |
| 207 | } |
| 208 | #else |
| 209 | static inline const char *spectre_v2_module_string(void) { return ""; } |
Andi Kleen | a1745ad | 2018-01-25 15:50:28 -0800 | [diff] [blame] | 210 | #endif |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 211 | |
| 212 | static void __init spec2_print_if_insecure(const char *reason) |
| 213 | { |
| 214 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 215 | pr_info("%s selected on command line.\n", reason); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | static void __init spec2_print_if_secure(const char *reason) |
| 219 | { |
| 220 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 221 | pr_info("%s selected on command line.\n", reason); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | static inline bool retp_compiler(void) |
| 225 | { |
| 226 | return __is_defined(RETPOLINE); |
| 227 | } |
| 228 | |
| 229 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
| 230 | { |
| 231 | int len = strlen(opt); |
| 232 | |
| 233 | return len == arglen && !strncmp(arg, opt, len); |
| 234 | } |
| 235 | |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 236 | static const struct { |
| 237 | const char *option; |
| 238 | enum spectre_v2_mitigation_cmd cmd; |
| 239 | bool secure; |
| 240 | } mitigation_options[] = { |
| 241 | { "off", SPECTRE_V2_CMD_NONE, false }, |
| 242 | { "on", SPECTRE_V2_CMD_FORCE, true }, |
| 243 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, |
| 244 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, |
| 245 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, |
| 246 | { "auto", SPECTRE_V2_CMD_AUTO, false }, |
| 247 | }; |
| 248 | |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 249 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
| 250 | { |
| 251 | char arg[20]; |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 252 | int ret, i; |
| 253 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 254 | |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 255 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) |
| 256 | return SPECTRE_V2_CMD_NONE; |
| 257 | else { |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 258 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 259 | if (ret < 0) |
| 260 | return SPECTRE_V2_CMD_AUTO; |
| 261 | |
| 262 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { |
| 263 | if (!match_option(arg, ret, mitigation_options[i].option)) |
| 264 | continue; |
| 265 | cmd = mitigation_options[i].cmd; |
| 266 | break; |
| 267 | } |
| 268 | |
| 269 | if (i >= ARRAY_SIZE(mitigation_options)) { |
Dan Carpenter | 14eb413 | 2018-02-14 10:14:17 +0300 | [diff] [blame] | 270 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 271 | return SPECTRE_V2_CMD_AUTO; |
| 272 | } |
| 273 | } |
| 274 | |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 275 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
| 276 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || |
| 277 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && |
| 278 | !IS_ENABLED(CONFIG_RETPOLINE)) { |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 279 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 280 | return SPECTRE_V2_CMD_AUTO; |
KarimAllah Ahmed | 961cb14 | 2018-02-01 11:27:21 +0000 | [diff] [blame] | 281 | } |
| 282 | |
| 283 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && |
| 284 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
| 285 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); |
| 286 | return SPECTRE_V2_CMD_AUTO; |
| 287 | } |
| 288 | |
| 289 | if (mitigation_options[i].secure) |
| 290 | spec2_print_if_secure(mitigation_options[i].option); |
| 291 | else |
| 292 | spec2_print_if_insecure(mitigation_options[i].option); |
| 293 | |
| 294 | return cmd; |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 295 | } |
| 296 | |
David Woodhouse | abf67b1 | 2018-01-12 17:49:25 +0000 | [diff] [blame] | 297 | /* Check for Skylake-like CPUs (for RSB handling) */ |
| 298 | static bool __init is_skylake_era(void) |
| 299 | { |
| 300 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && |
| 301 | boot_cpu_data.x86 == 6) { |
| 302 | switch (boot_cpu_data.x86_model) { |
| 303 | case INTEL_FAM6_SKYLAKE_MOBILE: |
| 304 | case INTEL_FAM6_SKYLAKE_DESKTOP: |
| 305 | case INTEL_FAM6_SKYLAKE_X: |
| 306 | case INTEL_FAM6_KABYLAKE_MOBILE: |
| 307 | case INTEL_FAM6_KABYLAKE_DESKTOP: |
| 308 | return true; |
| 309 | } |
| 310 | } |
| 311 | return false; |
| 312 | } |
| 313 | |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 314 | static void __init spectre_v2_select_mitigation(void) |
| 315 | { |
| 316 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); |
| 317 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; |
| 318 | |
| 319 | /* |
| 320 | * If the CPU is not affected and the command line mode is NONE or AUTO |
| 321 | * then nothing to do. |
| 322 | */ |
| 323 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && |
| 324 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) |
| 325 | return; |
| 326 | |
| 327 | switch (cmd) { |
| 328 | case SPECTRE_V2_CMD_NONE: |
| 329 | return; |
| 330 | |
| 331 | case SPECTRE_V2_CMD_FORCE: |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 332 | case SPECTRE_V2_CMD_AUTO: |
Dou Liyang | 9eedeb7 | 2018-01-30 14:13:50 +0800 | [diff] [blame] | 333 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
| 334 | goto retpoline_auto; |
| 335 | break; |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 336 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
| 337 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
| 338 | goto retpoline_amd; |
| 339 | break; |
| 340 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: |
| 341 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
| 342 | goto retpoline_generic; |
| 343 | break; |
| 344 | case SPECTRE_V2_CMD_RETPOLINE: |
| 345 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
| 346 | goto retpoline_auto; |
| 347 | break; |
| 348 | } |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 349 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 350 | return; |
| 351 | |
| 352 | retpoline_auto: |
| 353 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { |
| 354 | retpoline_amd: |
| 355 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 356 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 357 | goto retpoline_generic; |
| 358 | } |
| 359 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : |
| 360 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; |
| 361 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
| 362 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
| 363 | } else { |
| 364 | retpoline_generic: |
| 365 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : |
| 366 | SPECTRE_V2_RETPOLINE_MINIMAL; |
| 367 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
| 368 | } |
| 369 | |
| 370 | spectre_v2_enabled = mode; |
| 371 | pr_info("%s\n", spectre_v2_strings[mode]); |
David Woodhouse | abf67b1 | 2018-01-12 17:49:25 +0000 | [diff] [blame] | 372 | |
| 373 | /* |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 374 | * If neither SMEP nor PTI are available, there is a risk of |
David Woodhouse | abf67b1 | 2018-01-12 17:49:25 +0000 | [diff] [blame] | 375 | * hitting userspace addresses in the RSB after a context switch |
| 376 | * from a shallow call stack to a deeper one. To prevent this fill |
| 377 | * the entire RSB, even when using IBRS. |
| 378 | * |
| 379 | * Skylake era CPUs have a separate issue with *underflow* of the |
| 380 | * RSB, when they will predict 'ret' targets from the generic BTB. |
| 381 | * The proper mitigation for this is IBRS. If IBRS is not supported |
| 382 | * or deactivated in favour of retpolines the RSB fill on context |
| 383 | * switch is required. |
| 384 | */ |
| 385 | if ((!boot_cpu_has(X86_FEATURE_KAISER) && |
| 386 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { |
| 387 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 388 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
David Woodhouse | abf67b1 | 2018-01-12 17:49:25 +0000 | [diff] [blame] | 389 | } |
David Woodhouse | 31fd9ed | 2018-01-25 16:14:15 +0000 | [diff] [blame] | 390 | |
| 391 | /* Initialize Indirect Branch Prediction Barrier if supported */ |
David Woodhouse | 77b3b3e | 2018-01-27 16:24:32 +0000 | [diff] [blame] | 392 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
| 393 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 394 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
David Woodhouse | 31fd9ed | 2018-01-25 16:14:15 +0000 | [diff] [blame] | 395 | } |
David Woodhouse | a27ede1 | 2018-02-19 10:50:54 +0000 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * Retpoline means the kernel is safe because it has no indirect |
| 399 | * branches. But firmware isn't, so use IBRS to protect that. |
| 400 | */ |
| 401 | if (boot_cpu_has(X86_FEATURE_IBRS)) { |
| 402 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
| 403 | pr_info("Enabling Restricted Speculation for firmware calls\n"); |
| 404 | } |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | #undef pr_fmt |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 408 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt |
| 409 | |
Kees Cook | ea055f7 | 2018-05-03 15:03:30 -0700 | [diff] [blame] | 410 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 411 | |
| 412 | /* The kernel command line selection */ |
| 413 | enum ssb_mitigation_cmd { |
| 414 | SPEC_STORE_BYPASS_CMD_NONE, |
| 415 | SPEC_STORE_BYPASS_CMD_AUTO, |
| 416 | SPEC_STORE_BYPASS_CMD_ON, |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 417 | SPEC_STORE_BYPASS_CMD_PRCTL, |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 418 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 419 | }; |
| 420 | |
| 421 | static const char *ssb_strings[] = { |
| 422 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 423 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 424 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
| 425 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 426 | }; |
| 427 | |
| 428 | static const struct { |
| 429 | const char *option; |
| 430 | enum ssb_mitigation_cmd cmd; |
| 431 | } ssb_mitigation_options[] = { |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 432 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
| 433 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ |
| 434 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ |
| 435 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ |
| 436 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 437 | }; |
| 438 | |
| 439 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) |
| 440 | { |
| 441 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; |
| 442 | char arg[20]; |
| 443 | int ret, i; |
| 444 | |
| 445 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { |
| 446 | return SPEC_STORE_BYPASS_CMD_NONE; |
| 447 | } else { |
| 448 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", |
| 449 | arg, sizeof(arg)); |
| 450 | if (ret < 0) |
| 451 | return SPEC_STORE_BYPASS_CMD_AUTO; |
| 452 | |
| 453 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { |
| 454 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) |
| 455 | continue; |
| 456 | |
| 457 | cmd = ssb_mitigation_options[i].cmd; |
| 458 | break; |
| 459 | } |
| 460 | |
| 461 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { |
| 462 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
| 463 | return SPEC_STORE_BYPASS_CMD_AUTO; |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | return cmd; |
| 468 | } |
| 469 | |
Jiri Kosina | eb7b562 | 2018-05-10 22:47:18 +0200 | [diff] [blame] | 470 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 471 | { |
| 472 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; |
| 473 | enum ssb_mitigation_cmd cmd; |
| 474 | |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 475 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 476 | return mode; |
| 477 | |
| 478 | cmd = ssb_parse_cmdline(); |
| 479 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && |
| 480 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || |
| 481 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) |
| 482 | return mode; |
| 483 | |
| 484 | switch (cmd) { |
| 485 | case SPEC_STORE_BYPASS_CMD_AUTO: |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 486 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
| 487 | /* |
| 488 | * Choose prctl+seccomp as the default mode if seccomp is |
| 489 | * enabled. |
| 490 | */ |
| 491 | if (IS_ENABLED(CONFIG_SECCOMP)) |
| 492 | mode = SPEC_STORE_BYPASS_SECCOMP; |
| 493 | else |
| 494 | mode = SPEC_STORE_BYPASS_PRCTL; |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 495 | break; |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 496 | case SPEC_STORE_BYPASS_CMD_ON: |
| 497 | mode = SPEC_STORE_BYPASS_DISABLE; |
| 498 | break; |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 499 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
| 500 | mode = SPEC_STORE_BYPASS_PRCTL; |
| 501 | break; |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 502 | case SPEC_STORE_BYPASS_CMD_NONE: |
| 503 | break; |
| 504 | } |
| 505 | |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 506 | /* |
| 507 | * We have three CPU feature flags that are in play here: |
| 508 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 509 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 510 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
| 511 | */ |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 512 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 513 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 514 | /* |
| 515 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses |
| 516 | * a completely different MSR and bit dependent on family. |
| 517 | */ |
| 518 | switch (boot_cpu_data.x86_vendor) { |
| 519 | case X86_VENDOR_INTEL: |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 520 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
| 521 | x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD; |
| 522 | x86_spec_ctrl_set(SPEC_CTRL_SSBD); |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 523 | break; |
| 524 | case X86_VENDOR_AMD: |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 525 | x86_amd_ssb_disable(); |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 526 | break; |
| 527 | } |
| 528 | } |
| 529 | |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 530 | return mode; |
| 531 | } |
| 532 | |
Konrad Rzeszutek Wilk | 6fdd277 | 2018-05-11 16:50:35 -0400 | [diff] [blame^] | 533 | static void ssb_select_mitigation(void) |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 534 | { |
| 535 | ssb_mode = __ssb_select_mitigation(); |
| 536 | |
| 537 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) |
| 538 | pr_info("%s\n", ssb_strings[ssb_mode]); |
| 539 | } |
| 540 | |
| 541 | #undef pr_fmt |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 542 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
David Woodhouse | 8f96937ee | 2018-01-11 21:46:26 +0000 | [diff] [blame] | 543 | |
Kees Cook | 4272f52 | 2018-05-01 15:19:04 -0700 | [diff] [blame] | 544 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 545 | { |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 546 | bool update; |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 547 | |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 548 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
| 549 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 550 | return -ENXIO; |
| 551 | |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 552 | switch (ctrl) { |
| 553 | case PR_SPEC_ENABLE: |
| 554 | /* If speculation is force disabled, enable is not allowed */ |
| 555 | if (task_spec_ssb_force_disable(task)) |
| 556 | return -EPERM; |
| 557 | task_clear_spec_ssb_disable(task); |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 558 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 559 | break; |
| 560 | case PR_SPEC_DISABLE: |
| 561 | task_set_spec_ssb_disable(task); |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 562 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 563 | break; |
| 564 | case PR_SPEC_FORCE_DISABLE: |
| 565 | task_set_spec_ssb_disable(task); |
| 566 | task_set_spec_ssb_force_disable(task); |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 567 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 568 | break; |
| 569 | default: |
| 570 | return -ERANGE; |
| 571 | } |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 572 | |
Kees Cook | 4272f52 | 2018-05-01 15:19:04 -0700 | [diff] [blame] | 573 | /* |
| 574 | * If being set on non-current task, delay setting the CPU |
| 575 | * mitigation until it is next scheduled. |
| 576 | */ |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 577 | if (task == current && update) |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 578 | speculative_store_bypass_update(); |
| 579 | |
| 580 | return 0; |
| 581 | } |
| 582 | |
Thomas Gleixner | 094c276 | 2018-05-04 15:12:06 +0200 | [diff] [blame] | 583 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
| 584 | unsigned long ctrl) |
| 585 | { |
| 586 | switch (which) { |
| 587 | case PR_SPEC_STORE_BYPASS: |
| 588 | return ssb_prctl_set(task, ctrl); |
| 589 | default: |
| 590 | return -ENODEV; |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | #ifdef CONFIG_SECCOMP |
| 595 | void arch_seccomp_spec_mitigate(struct task_struct *task) |
| 596 | { |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 597 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
| 598 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); |
Thomas Gleixner | 094c276 | 2018-05-04 15:12:06 +0200 | [diff] [blame] | 599 | } |
| 600 | #endif |
| 601 | |
Kees Cook | 4272f52 | 2018-05-01 15:19:04 -0700 | [diff] [blame] | 602 | static int ssb_prctl_get(struct task_struct *task) |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 603 | { |
| 604 | switch (ssb_mode) { |
| 605 | case SPEC_STORE_BYPASS_DISABLE: |
| 606 | return PR_SPEC_DISABLE; |
Kees Cook | 05a85a3 | 2018-05-03 14:37:54 -0700 | [diff] [blame] | 607 | case SPEC_STORE_BYPASS_SECCOMP: |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 608 | case SPEC_STORE_BYPASS_PRCTL: |
Thomas Gleixner | 036608d | 2018-05-03 22:09:15 +0200 | [diff] [blame] | 609 | if (task_spec_ssb_force_disable(task)) |
| 610 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; |
| 611 | if (task_spec_ssb_disable(task)) |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 612 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
| 613 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; |
| 614 | default: |
| 615 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) |
| 616 | return PR_SPEC_ENABLE; |
| 617 | return PR_SPEC_NOT_AFFECTED; |
| 618 | } |
| 619 | } |
| 620 | |
Kees Cook | 4272f52 | 2018-05-01 15:19:04 -0700 | [diff] [blame] | 621 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 622 | { |
| 623 | switch (which) { |
| 624 | case PR_SPEC_STORE_BYPASS: |
Kees Cook | 4272f52 | 2018-05-01 15:19:04 -0700 | [diff] [blame] | 625 | return ssb_prctl_get(task); |
Thomas Gleixner | a078e3e | 2018-04-29 15:26:40 +0200 | [diff] [blame] | 626 | default: |
| 627 | return -ENODEV; |
| 628 | } |
| 629 | } |
| 630 | |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 631 | void x86_spec_ctrl_setup_ap(void) |
| 632 | { |
| 633 | if (boot_cpu_has(X86_FEATURE_IBRS)) |
Konrad Rzeszutek Wilk | 99b1311 | 2018-04-25 22:04:23 -0400 | [diff] [blame] | 634 | x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask); |
David Woodhouse | f854434 | 2018-05-20 20:52:05 +0100 | [diff] [blame] | 635 | |
| 636 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) |
Konrad Rzeszutek Wilk | bf3da84 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 637 | x86_amd_ssb_disable(); |
Konrad Rzeszutek Wilk | 19e3a2b | 2018-04-25 22:04:22 -0400 | [diff] [blame] | 638 | } |
| 639 | |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 640 | #ifdef CONFIG_SYSFS |
Konrad Rzeszutek Wilk | 3effee6 | 2018-04-25 22:04:17 -0400 | [diff] [blame] | 641 | |
Jiri Kosina | dbb264a | 2018-05-10 22:47:32 +0200 | [diff] [blame] | 642 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
Konrad Rzeszutek Wilk | 6fdd277 | 2018-05-11 16:50:35 -0400 | [diff] [blame^] | 643 | char *buf, unsigned int bug) |
Konrad Rzeszutek Wilk | 3effee6 | 2018-04-25 22:04:17 -0400 | [diff] [blame] | 644 | { |
| 645 | if (!boot_cpu_has_bug(bug)) |
| 646 | return sprintf(buf, "Not affected\n"); |
| 647 | |
| 648 | switch (bug) { |
| 649 | case X86_BUG_CPU_MELTDOWN: |
| 650 | if (boot_cpu_has(X86_FEATURE_KAISER)) |
| 651 | return sprintf(buf, "Mitigation: PTI\n"); |
| 652 | |
| 653 | break; |
| 654 | |
| 655 | case X86_BUG_SPECTRE_V1: |
| 656 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); |
| 657 | |
| 658 | case X86_BUG_SPECTRE_V2: |
| 659 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
| 660 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", |
| 661 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
| 662 | spectre_v2_module_string()); |
| 663 | |
Konrad Rzeszutek Wilk | 6f70a55 | 2018-04-25 22:04:21 -0400 | [diff] [blame] | 664 | case X86_BUG_SPEC_STORE_BYPASS: |
| 665 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); |
| 666 | |
Konrad Rzeszutek Wilk | 3effee6 | 2018-04-25 22:04:17 -0400 | [diff] [blame] | 667 | default: |
| 668 | break; |
| 669 | } |
| 670 | |
| 671 | return sprintf(buf, "Vulnerable\n"); |
| 672 | } |
| 673 | |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 674 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 675 | { |
Konrad Rzeszutek Wilk | 3effee6 | 2018-04-25 22:04:17 -0400 | [diff] [blame] | 676 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 677 | } |
| 678 | |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 679 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 680 | { |
Konrad Rzeszutek Wilk | 3effee6 | 2018-04-25 22:04:17 -0400 | [diff] [blame] | 681 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 682 | } |
| 683 | |
Ingo Molnar | 3aad6fe | 2018-02-13 09:03:08 +0100 | [diff] [blame] | 684 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 685 | { |
Konrad Rzeszutek Wilk | 3effee6 | 2018-04-25 22:04:17 -0400 | [diff] [blame] | 686 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 687 | } |
Konrad Rzeszutek Wilk | 24e4dd9 | 2018-04-25 22:04:20 -0400 | [diff] [blame] | 688 | |
| 689 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) |
| 690 | { |
| 691 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); |
| 692 | } |
Thomas Gleixner | 45a9882 | 2018-01-07 22:48:01 +0100 | [diff] [blame] | 693 | #endif |