blob: 4674f94957cd35398f8ea7fcb5e13ad6fde38fea [file] [log] [blame]
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +02001/*
2 * Marvell Armada 370/XP SoC timer handling.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Timer 0 is used as free-running clocksource, while timer 1 is
15 * used as clock_event_device.
16 */
17
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/kernel.h>
21#include <linux/timer.h>
22#include <linux/clockchips.h>
23#include <linux/interrupt.h>
24#include <linux/of.h>
25#include <linux/of_irq.h>
26#include <linux/of_address.h>
27#include <linux/irq.h>
28#include <linux/module.h>
29#include <asm/sched_clock.h>
30
31/*
32 * Timer block registers.
33 */
34#define TIMER_CTRL_OFF 0x0000
35#define TIMER0_EN 0x0001
36#define TIMER0_RELOAD_EN 0x0002
37#define TIMER0_25MHZ 0x0800
38#define TIMER0_DIV(div) ((div) << 19)
39#define TIMER1_EN 0x0004
40#define TIMER1_RELOAD_EN 0x0008
41#define TIMER1_25MHZ 0x1000
42#define TIMER1_DIV(div) ((div) << 22)
43#define TIMER_EVENTS_STATUS 0x0004
44#define TIMER0_CLR_MASK (~0x1)
45#define TIMER1_CLR_MASK (~0x100)
46#define TIMER0_RELOAD_OFF 0x0010
47#define TIMER0_VAL_OFF 0x0014
48#define TIMER1_RELOAD_OFF 0x0018
49#define TIMER1_VAL_OFF 0x001c
50
51/* Global timers are connected to the coherency fabric clock, and the
52 below divider reduces their incrementing frequency. */
53#define TIMER_DIVIDER_SHIFT 5
54#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
55
56/*
57 * SoC-specific data.
58 */
59static void __iomem *timer_base;
60static int timer_irq;
61
62/*
63 * Number of timer ticks per jiffy.
64 */
65static u32 ticks_per_jiffy;
66
67static u32 notrace armada_370_xp_read_sched_clock(void)
68{
69 return ~readl(timer_base + TIMER0_VAL_OFF);
70}
71
72/*
73 * Clockevent handling.
74 */
75static int
76armada_370_xp_clkevt_next_event(unsigned long delta,
77 struct clock_event_device *dev)
78{
79 u32 u;
80
81 /*
82 * Clear clockevent timer interrupt.
83 */
84 writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
85
86 /*
87 * Setup new clockevent timer value.
88 */
89 writel(delta, timer_base + TIMER1_VAL_OFF);
90
91 /*
92 * Enable the timer.
93 */
94 u = readl(timer_base + TIMER_CTRL_OFF);
95 u = ((u & ~TIMER1_RELOAD_EN) | TIMER1_EN |
96 TIMER1_DIV(TIMER_DIVIDER_SHIFT));
97 writel(u, timer_base + TIMER_CTRL_OFF);
98
99 return 0;
100}
101
102static void
103armada_370_xp_clkevt_mode(enum clock_event_mode mode,
104 struct clock_event_device *dev)
105{
106 u32 u;
107
108 if (mode == CLOCK_EVT_MODE_PERIODIC) {
109 /*
110 * Setup timer to fire at 1/HZ intervals.
111 */
112 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
113 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
114
115 /*
116 * Enable timer.
117 */
118 u = readl(timer_base + TIMER_CTRL_OFF);
119
120 writel((u | TIMER1_EN | TIMER1_RELOAD_EN |
121 TIMER1_DIV(TIMER_DIVIDER_SHIFT)),
122 timer_base + TIMER_CTRL_OFF);
123 } else {
124 /*
125 * Disable timer.
126 */
127 u = readl(timer_base + TIMER_CTRL_OFF);
128 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
129
130 /*
131 * ACK pending timer interrupt.
132 */
133 writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
134
135 }
136}
137
138static struct clock_event_device armada_370_xp_clkevt = {
139 .name = "armada_370_xp_tick",
140 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
141 .shift = 32,
142 .rating = 300,
143 .set_next_event = armada_370_xp_clkevt_next_event,
144 .set_mode = armada_370_xp_clkevt_mode,
145};
146
147static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
148{
149 /*
150 * ACK timer interrupt and call event handler.
151 */
152
153 writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
154 armada_370_xp_clkevt.event_handler(&armada_370_xp_clkevt);
155
156 return IRQ_HANDLED;
157}
158
159static struct irqaction armada_370_xp_timer_irq = {
160 .name = "armada_370_xp_tick",
161 .flags = IRQF_DISABLED | IRQF_TIMER,
162 .handler = armada_370_xp_timer_interrupt
163};
164
165void __init armada_370_xp_timer_init(void)
166{
167 u32 u;
168 struct device_node *np;
169 unsigned int timer_clk;
170 int ret;
171 np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
172 timer_base = of_iomap(np, 0);
173 WARN_ON(!timer_base);
174
175 if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
176 /* The fixed 25MHz timer is available so let's use it */
177 u = readl(timer_base + TIMER_CTRL_OFF);
178 writel(u | TIMER0_25MHZ | TIMER1_25MHZ,
179 timer_base + TIMER_CTRL_OFF);
180 timer_clk = 25000000;
181 } else {
182 u32 clk = 0;
183 ret = of_property_read_u32(np, "clock-frequency", &clk);
184 WARN_ON(!clk || ret < 0);
185 u = readl(timer_base + TIMER_CTRL_OFF);
186 writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
187 timer_base + TIMER_CTRL_OFF);
188 timer_clk = clk / TIMER_DIVIDER;
189 }
190
191 /* We use timer 0 as clocksource, and timer 1 for
192 clockevents */
193 timer_irq = irq_of_parse_and_map(np, 1);
194
195 ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
196
197 /*
198 * Set scale and timer for sched_clock.
199 */
200 setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
201
202 /*
203 * Setup free-running clocksource timer (interrupts
204 * disabled).
205 */
206 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
207 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
208
209 u = readl(timer_base + TIMER_CTRL_OFF);
210
211 writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
212 TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
213
214 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
215 "armada_370_xp_clocksource",
216 timer_clk, 300, 32, clocksource_mmio_readl_down);
217
218 /*
219 * Setup clockevent timer (interrupt-driven).
220 */
221 setup_irq(timer_irq, &armada_370_xp_timer_irq);
222 armada_370_xp_clkevt.cpumask = cpumask_of(0);
223 clockevents_config_and_register(&armada_370_xp_clkevt,
224 timer_clk, 1, 0xfffffffe);
225}
226