| Thomas Petazzoni | f3b42b7 | 2012-09-13 17:41:48 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Include file for Marvell Armada XP family SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * |
| 6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. |
| 11 | * |
| 12 | * Contains definitions specific to the Armada XP MV78230 SoC that are not |
| 13 | * common to all Armada XP SoCs. |
| 14 | */ |
| 15 | |
| 16 | /include/ "armada-xp.dtsi" |
| 17 | |
| 18 | / { |
| 19 | model = "Marvell Armada XP MV78230 SoC"; |
| 20 | compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; |
| 21 | |
| Thomas Petazzoni | 397d59f | 2012-09-19 22:53:01 +0200 | [diff] [blame] | 22 | aliases { |
| 23 | gpio0 = &gpio0; |
| 24 | gpio1 = &gpio1; |
| 25 | }; |
| 26 | |
| Gregory CLEMENT | 9d20278 | 2012-11-17 15:22:24 +0100 | [diff] [blame] | 27 | cpus { |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <0>; |
| 30 | |
| 31 | cpu@0 { |
| 32 | device_type = "cpu"; |
| 33 | compatible = "marvell,sheeva-v7"; |
| 34 | reg = <0>; |
| 35 | clocks = <&cpuclk 0>; |
| 36 | }; |
| Thomas Petazzoni | 44cfae9 | 2013-01-06 11:10:40 +0100 | [diff] [blame] | 37 | |
| 38 | cpu@1 { |
| 39 | device_type = "cpu"; |
| 40 | compatible = "marvell,sheeva-v7"; |
| 41 | reg = <1>; |
| 42 | clocks = <&cpuclk 1>; |
| 43 | }; |
| Andrew Lunn | 41be8dc | 2013-01-06 11:10:42 +0100 | [diff] [blame] | 44 | }; |
| Gregory CLEMENT | 9d20278 | 2012-11-17 15:22:24 +0100 | [diff] [blame] | 45 | |
| Thomas Petazzoni | f3b42b7 | 2012-09-13 17:41:48 +0200 | [diff] [blame] | 46 | soc { |
| 47 | pinctrl { |
| 48 | compatible = "marvell,mv78230-pinctrl"; |
| 49 | reg = <0xd0018000 0x38>; |
| Thomas Petazzoni | 6d36e8e | 2012-12-21 15:49:06 +0100 | [diff] [blame] | 50 | |
| 51 | sdio_pins: sdio-pins { |
| 52 | marvell,pins = "mpp30", "mpp31", "mpp32", |
| 53 | "mpp33", "mpp34", "mpp35"; |
| 54 | marvell,function = "sd0"; |
| 55 | }; |
| Thomas Petazzoni | f3b42b7 | 2012-09-13 17:41:48 +0200 | [diff] [blame] | 56 | }; |
| Thomas Petazzoni | 397d59f | 2012-09-19 22:53:01 +0200 | [diff] [blame] | 57 | |
| 58 | gpio0: gpio@d0018100 { |
| Thomas Petazzoni | 5f79c65 | 2013-01-07 17:26:58 +0100 | [diff] [blame] | 59 | compatible = "marvell,orion-gpio"; |
| 60 | reg = <0xd0018100 0x40>; |
| Thomas Petazzoni | 397d59f | 2012-09-19 22:53:01 +0200 | [diff] [blame] | 61 | ngpios = <32>; |
| 62 | gpio-controller; |
| 63 | #gpio-cells = <2>; |
| 64 | interrupt-controller; |
| 65 | #interrupts-cells = <2>; |
| Thomas Petazzoni | 5f79c65 | 2013-01-07 17:26:58 +0100 | [diff] [blame] | 66 | interrupts = <82>, <83>, <84>, <85>; |
| Thomas Petazzoni | 397d59f | 2012-09-19 22:53:01 +0200 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | gpio1: gpio@d0018140 { |
| Thomas Petazzoni | 5f79c65 | 2013-01-07 17:26:58 +0100 | [diff] [blame] | 70 | compatible = "marvell,orion-gpio"; |
| 71 | reg = <0xd0018140 0x40>; |
| Thomas Petazzoni | 397d59f | 2012-09-19 22:53:01 +0200 | [diff] [blame] | 72 | ngpios = <17>; |
| 73 | gpio-controller; |
| 74 | #gpio-cells = <2>; |
| 75 | interrupt-controller; |
| 76 | #interrupts-cells = <2>; |
| Thomas Petazzoni | 5f79c65 | 2013-01-07 17:26:58 +0100 | [diff] [blame] | 77 | interrupts = <87>, <88>, <89>; |
| Thomas Petazzoni | 397d59f | 2012-09-19 22:53:01 +0200 | [diff] [blame] | 78 | }; |
| Thomas Petazzoni | f3b42b7 | 2012-09-13 17:41:48 +0200 | [diff] [blame] | 79 | }; |
| 80 | }; |