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gerrit-public.fairphone.software / kernel / msm-4.9 / 7034228792cc561e79ff8600f02884bd4c80e287 / . / arch / mips / include / uapi / asm / ptrace.h
blob: 4d58d8468705940a77764f2615946a7c89485807 [file] [log] [blame]
David Howells61730c52012-10-09 09:47:14 +0100[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _UAPI_ASM_PTRACE_H
10#define _UAPI_ASM_PTRACE_H
11
12/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
13#define FPR_BASE 32
14#define PC 64
15#define CAUSE 65
16#define BADVADDR 66
17#define MMHI 67
18#define MMLO 68
19#define FPC_CSR 69
20#define FPC_EIR 70
21#define DSP_BASE 71 /* 3 more hi / lo register pairs */
22#define DSP_CONTROL 77
23#define ACX 78
24
25/*
26 * This struct defines the way the registers are stored on the stack during a
27 * system call/exception. As usual the registers k0/k1 aren't being saved.
28 */
29struct pt_regs {
30#ifdef CONFIG_32BIT
31 /* Pad bytes for argument save space on the stack. */
32 unsigned long pad0[6];
33#endif
34
35 /* Saved main processor registers. */
36 unsigned long regs[32];
37
38 /* Saved special registers. */
39 unsigned long cp0_status;
40 unsigned long hi;
41 unsigned long lo;
42#ifdef CONFIG_CPU_HAS_SMARTMIPS
43 unsigned long acx;
44#endif
45 unsigned long cp0_badvaddr;
46 unsigned long cp0_cause;
47 unsigned long cp0_epc;
48#ifdef CONFIG_MIPS_MT_SMTC
49 unsigned long cp0_tcstatus;
50#endif /* CONFIG_MIPS_MT_SMTC */
51#ifdef CONFIG_CPU_CAVIUM_OCTEON
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame^]52 unsigned long long mpl[3]; /* MTM{0,1,2} */
53 unsigned long long mtp[3]; /* MTP{0,1,2} */
David Howells61730c52012-10-09 09:47:14 +0100[diff] [blame]54#endif
55} __attribute__ ((aligned (8)));
56
57/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
58#define PTRACE_GETREGS 12
59#define PTRACE_SETREGS 13
60#define PTRACE_GETFPREGS 14
61#define PTRACE_SETFPREGS 15
62/* #define PTRACE_GETFPXREGS 18 */
63/* #define PTRACE_SETFPXREGS 19 */
64
65#define PTRACE_OLDSETOPTIONS 21
66
67#define PTRACE_GET_THREAD_AREA 25
68#define PTRACE_SET_THREAD_AREA 26
69
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame^]70/* Calls to trace a 64bit program from a 32bit program. */
David Howells61730c52012-10-09 09:47:14 +0100[diff] [blame]71#define PTRACE_PEEKTEXT_3264 0xc0
72#define PTRACE_PEEKDATA_3264 0xc1
73#define PTRACE_POKETEXT_3264 0xc2
74#define PTRACE_POKEDATA_3264 0xc3
75#define PTRACE_GET_THREAD_AREA_3264 0xc4
76
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame^]77/* Read and write watchpoint registers. */
David Howells61730c52012-10-09 09:47:14 +0100[diff] [blame]78enum pt_watch_style {
79 pt_watch_style_mips32,
80 pt_watch_style_mips64
81};
82struct mips32_watch_regs {
83 unsigned int watchlo[8];
84 /* Lower 16 bits of watchhi. */
85 unsigned short watchhi[8];
86 /* Valid mask and I R W bits.
87 * bit 0 -- 1 if W bit is usable.
88 * bit 1 -- 1 if R bit is usable.
89 * bit 2 -- 1 if I bit is usable.
90 * bits 3 - 11 -- Valid watchhi mask bits.
91 */
92 unsigned short watch_masks[8];
93 /* The number of valid watch register pairs. */
94 unsigned int num_valid;
95} __attribute__((aligned(8)));
96
97struct mips64_watch_regs {
98 unsigned long long watchlo[8];
99 unsigned short watchhi[8];
100 unsigned short watch_masks[8];
101 unsigned int num_valid;
102} __attribute__((aligned(8)));
103
104struct pt_watch_regs {
105 enum pt_watch_style style;
106 union {
107 struct mips32_watch_regs mips32;
108 struct mips64_watch_regs mips64;
109 };
110};
111
112#define PTRACE_GET_WATCH_REGS 0xd0
113#define PTRACE_SET_WATCH_REGS 0xd1
114
115
116#endif /* _UAPI_ASM_PTRACE_H */