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Linus Torvalds1da177e2005-04-16 15:20:36 -07001comment "Processor Type"
2
3config CPU_32
4 bool
5 default y
6
7# Select CPU types depending on the architecture selected. This selects
8# which CPUs we support in the kernel image, and the compiler instruction
9# optimiser behaviour.
10
11# ARM610
12config CPU_ARM610
13 bool "Support ARM610 processor"
14 depends on ARCH_RPC
15 select CPU_32v3
16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT
18 select CPU_COPY_V3
19 select CPU_TLB_V3
20 help
21 The ARM610 is the successor to the ARM3 processor
22 and was produced by VLSI Technology Inc.
23
24 Say Y if you want support for the ARM610 processor.
25 Otherwise, say N.
26
27# ARM710
28config CPU_ARM710
29 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
30 default y if ARCH_CLPS7500
31 select CPU_32v3
32 select CPU_CACHE_V3
33 select CPU_CACHE_VIVT
34 select CPU_COPY_V3
35 select CPU_TLB_V3
36 help
37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 designed by Advanced RISC Machines Ltd. The ARM710 is the
39 successor to the ARM610 processor. It was released in
40 July 1994 by VLSI Technology Inc.
41
42 Say Y if you want support for the ARM710 processor.
43 Otherwise, say N.
44
45# ARM720T
46config CPU_ARM720T
47 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
48 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
49 select CPU_32v4
50 select CPU_ABRT_LV4T
51 select CPU_CACHE_V4
52 select CPU_CACHE_VIVT
53 select CPU_COPY_V4WT
54 select CPU_TLB_V4WT
55 help
56 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
57 MMU built around an ARM7TDMI core.
58
59 Say Y if you want support for the ARM720T processor.
60 Otherwise, say N.
61
62# ARM920T
63config CPU_ARM920T
64 bool "Support ARM920T processor" if !ARCH_S3C2410
65 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX
66 default y if ARCH_S3C2410
67 select CPU_32v4
68 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT
70 select CPU_CACHE_VIVT
71 select CPU_COPY_V4WB
72 select CPU_TLB_V4WBI
73 help
74 The ARM920T is licensed to be produced by numerous vendors,
75 and is used in the Maverick EP9312 and the Samsung S3C2410.
76
77 More information on the Maverick EP9312 at
78 <http://linuxdevices.com/products/PD2382866068.html>.
79
80 Say Y if you want support for the ARM920T processor.
81 Otherwise, say N.
82
83# ARM922T
84config CPU_ARM922T
85 bool "Support ARM922T processor" if ARCH_INTEGRATOR
86 depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR
87 default y if ARCH_CAMELOT || ARCH_LH7A40X
88 select CPU_32v4
89 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT
91 select CPU_CACHE_VIVT
92 select CPU_COPY_V4WB
93 select CPU_TLB_V4WBI
94 help
95 The ARM922T is a version of the ARM920T, but with smaller
96 instruction and data caches. It is used in Altera's
97 Excalibur XA device family.
98
99 Say Y if you want support for the ARM922T processor.
100 Otherwise, say N.
101
102# ARM925T
103config CPU_ARM925T
104 bool "Support ARM925T processor" if ARCH_OMAP
105 depends on ARCH_OMAP1510
106 default y if ARCH_OMAP1510
107 select CPU_32v4
108 select CPU_ABRT_EV4T
109 select CPU_CACHE_V4WT
110 select CPU_CACHE_VIVT
111 select CPU_COPY_V4WB
112 select CPU_TLB_V4WBI
113 help
114 The ARM925T is a mix between the ARM920T and ARM926T, but with
115 different instruction and data caches. It is used in TI's OMAP
116 device family.
117
118 Say Y if you want support for the ARM925T processor.
119 Otherwise, say N.
120
121# ARM926T
122config CPU_ARM926T
123 bool "Support ARM926T processor" if ARCH_INTEGRATOR
124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
126 select CPU_32v5
127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT
129 select CPU_COPY_V4WB
130 select CPU_TLB_V4WBI
131 help
132 This is a variant of the ARM920. It has slightly different
133 instruction sequences for cache and TLB operations. Curiously,
134 there is no documentation on it at the ARM corporate website.
135
136 Say Y if you want support for the ARM926T processor.
137 Otherwise, say N.
138
139# ARM1020 - needs validating
140config CPU_ARM1020
141 bool "Support ARM1020T (rev 0) processor"
142 depends on ARCH_INTEGRATOR
143 select CPU_32v5
144 select CPU_ABRT_EV4T
145 select CPU_CACHE_V4WT
146 select CPU_CACHE_VIVT
147 select CPU_COPY_V4WB
148 select CPU_TLB_V4WBI
149 help
150 The ARM1020 is the 32K cached version of the ARM10 processor,
151 with an addition of a floating-point unit.
152
153 Say Y if you want support for the ARM1020 processor.
154 Otherwise, say N.
155
156# ARM1020E - needs validating
157config CPU_ARM1020E
158 bool "Support ARM1020E processor"
159 depends on ARCH_INTEGRATOR
160 select CPU_32v5
161 select CPU_ABRT_EV4T
162 select CPU_CACHE_V4WT
163 select CPU_CACHE_VIVT
164 select CPU_COPY_V4WB
165 select CPU_TLB_V4WBI
166 depends on n
167
168# ARM1022E
169config CPU_ARM1022
170 bool "Support ARM1022E processor"
171 depends on ARCH_INTEGRATOR
172 select CPU_32v5
173 select CPU_ABRT_EV4T
174 select CPU_CACHE_VIVT
175 select CPU_COPY_V4WB # can probably do better
176 select CPU_TLB_V4WBI
177 help
178 The ARM1022E is an implementation of the ARMv5TE architecture
179 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
180 embedded trace macrocell, and a floating-point unit.
181
182 Say Y if you want support for the ARM1022E processor.
183 Otherwise, say N.
184
185# ARM1026EJ-S
186config CPU_ARM1026
187 bool "Support ARM1026EJ-S processor"
188 depends on ARCH_INTEGRATOR
189 select CPU_32v5
190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
191 select CPU_CACHE_VIVT
192 select CPU_COPY_V4WB # can probably do better
193 select CPU_TLB_V4WBI
194 help
195 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
196 based upon the ARM10 integer core.
197
198 Say Y if you want support for the ARM1026EJ-S processor.
199 Otherwise, say N.
200
201# SA110
202config CPU_SA110
203 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
204 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
205 select CPU_32v3 if ARCH_RPC
206 select CPU_32v4 if !ARCH_RPC
207 select CPU_ABRT_EV4
208 select CPU_CACHE_V4WB
209 select CPU_CACHE_VIVT
210 select CPU_COPY_V4WB
211 select CPU_TLB_V4WB
212 help
213 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
214 is available at five speeds ranging from 100 MHz to 233 MHz.
215 More information is available at
216 <http://developer.intel.com/design/strong/sa110.htm>.
217
218 Say Y if you want support for the SA-110 processor.
219 Otherwise, say N.
220
221# SA1100
222config CPU_SA1100
223 bool
224 depends on ARCH_SA1100
225 default y
226 select CPU_32v4
227 select CPU_ABRT_EV4
228 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT
230 select CPU_TLB_V4WB
231 select CPU_MINICACHE
232
233# XScale
234config CPU_XSCALE
235 bool
236 depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
237 default y
238 select CPU_32v5
239 select CPU_ABRT_EV5T
240 select CPU_CACHE_VIVT
241 select CPU_TLB_V4WBI
242 select CPU_MINICACHE
243
244# ARMv6
245config CPU_V6
246 bool "Support ARM V6 processor"
247 depends on ARCH_INTEGRATOR
248 select CPU_32v6
249 select CPU_ABRT_EV6
250 select CPU_CACHE_V6
251 select CPU_CACHE_VIPT
252 select CPU_COPY_V6
253 select CPU_TLB_V6
254
255# Figure out what processor architecture version we should be using.
256# This defines the compiler instruction set which depends on the machine type.
257config CPU_32v3
258 bool
259
260config CPU_32v4
261 bool
262
263config CPU_32v5
264 bool
265
266config CPU_32v6
267 bool
268
269# The abort model
270config CPU_ABRT_EV4
271 bool
272
273config CPU_ABRT_EV4T
274 bool
275
276config CPU_ABRT_LV4T
277 bool
278
279config CPU_ABRT_EV5T
280 bool
281
282config CPU_ABRT_EV5TJ
283 bool
284
285config CPU_ABRT_EV6
286 bool
287
288# The cache model
289config CPU_CACHE_V3
290 bool
291
292config CPU_CACHE_V4
293 bool
294
295config CPU_CACHE_V4WT
296 bool
297
298config CPU_CACHE_V4WB
299 bool
300
301config CPU_CACHE_V6
302 bool
303
304config CPU_CACHE_VIVT
305 bool
306
307config CPU_CACHE_VIPT
308 bool
309
310# The copy-page model
311config CPU_COPY_V3
312 bool
313
314config CPU_COPY_V4WT
315 bool
316
317config CPU_COPY_V4WB
318 bool
319
320config CPU_COPY_V6
321 bool
322
323# This selects the TLB model
324config CPU_TLB_V3
325 bool
326 help
327 ARM Architecture Version 3 TLB.
328
329config CPU_TLB_V4WT
330 bool
331 help
332 ARM Architecture Version 4 TLB with writethrough cache.
333
334config CPU_TLB_V4WB
335 bool
336 help
337 ARM Architecture Version 4 TLB with writeback cache.
338
339config CPU_TLB_V4WBI
340 bool
341 help
342 ARM Architecture Version 4 TLB with writeback cache and invalidate
343 instruction cache entry.
344
345config CPU_TLB_V6
346 bool
347
348config CPU_MINICACHE
349 bool
350 help
351 Processor has a minicache.
352
353comment "Processor Features"
354
355config ARM_THUMB
356 bool "Support Thumb user binaries"
357 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6
358 default y
359 help
360 Say Y if you want to include kernel support for running user space
361 Thumb binaries.
362
363 The Thumb instruction set is a compressed form of the standard ARM
364 instruction set resulting in smaller binaries at the expense of
365 slightly less efficient code.
366
367 If you don't know what this all is, saying Y is a safe choice.
368
369config CPU_BIG_ENDIAN
370 bool "Build big-endian kernel"
371 depends on ARCH_SUPPORTS_BIG_ENDIAN
372 help
373 Say Y if you plan on running a kernel in big-endian mode.
374 Note that your board must be properly built and your board
375 port must properly enable any big-endian related features
376 of your chipset/board/processor.
377
378config CPU_ICACHE_DISABLE
379 bool "Disable I-Cache"
380 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
381 help
382 Say Y here to disable the processor instruction cache. Unless
383 you have a reason not to or are unsure, say N.
384
385config CPU_DCACHE_DISABLE
386 bool "Disable D-Cache"
387 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
388 help
389 Say Y here to disable the processor data cache. Unless
390 you have a reason not to or are unsure, say N.
391
392config CPU_DCACHE_WRITETHROUGH
393 bool "Force write through D-cache"
394 depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
395 default y if CPU_ARM925T
396 help
397 Say Y here to use the data cache in writethrough mode. Unless you
398 specifically require this or are unsure, say N.
399
400config CPU_CACHE_ROUND_ROBIN
401 bool "Round robin I and D cache replacement algorithm"
402 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
403 help
404 Say Y here to use the predictable round-robin cache replacement
405 policy. Unless you specifically require this or are unsure, say N.
406
407config CPU_BPREDICT_DISABLE
408 bool "Disable branch prediction"
409 depends on CPU_ARM1020
410 help
411 Say Y here to disable branch prediction. If unsure, say N.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100412
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100413config TLS_REG_EMUL
414 bool
Nicolas Pitre70489c82005-05-12 19:27:12 +0100415 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100416 help
Nicolas Pitre70489c82005-05-12 19:27:12 +0100417 An SMP system using a pre-ARMv6 processor (there are apparently
418 a few prototypes like that in existence) and therefore access to
419 that required register must be emulated.
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100420
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100421config HAS_TLS_REG
422 bool
Nicolas Pitre70489c82005-05-12 19:27:12 +0100423 depends on !TLS_REG_EMUL
424 default y if SMP || CPU_32v7
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100425 help
426 This selects support for the CP15 thread register.
Nicolas Pitre70489c82005-05-12 19:27:12 +0100427 It is defined to be available on some ARMv6 processors (including
428 all SMP capable ARMv6's) or later processors. User space may
429 assume directly accessing that register and always obtain the
430 expected value only on ARMv7 and above.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100431