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gerrit-public.fairphone.software / kernel / msm-4.9 / 705b6c7b34f2621f95f606d0e683daa10cdb8eb9 / . / drivers / char / synclink_gt.c
blob: 2b9cde94e2f746ad88d1f8a75fb2305270479f95 [file] [log] [blame]
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame^]1/*
2 * $Id: synclink_gt.c,v 4.20 2005/11/08 19:51:55 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26/*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45//#define DBGTBUF(info) dump_tbufs(info)
46//#define DBGRBUF(info) dump_rbufs(info)
47
48
49#include <linux/config.h>
50#include <linux/module.h>
51#include <linux/version.h>
52#include <linux/errno.h>
53#include <linux/signal.h>
54#include <linux/sched.h>
55#include <linux/timer.h>
56#include <linux/interrupt.h>
57#include <linux/pci.h>
58#include <linux/tty.h>
59#include <linux/tty_flip.h>
60#include <linux/serial.h>
61#include <linux/major.h>
62#include <linux/string.h>
63#include <linux/fcntl.h>
64#include <linux/ptrace.h>
65#include <linux/ioport.h>
66#include <linux/mm.h>
67#include <linux/slab.h>
68#include <linux/netdevice.h>
69#include <linux/vmalloc.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/ioctl.h>
73#include <linux/termios.h>
74#include <linux/bitops.h>
75#include <linux/workqueue.h>
76#include <linux/hdlc.h>
77
78#include <asm/serial.h>
79#include <asm/system.h>
80#include <asm/io.h>
81#include <asm/irq.h>
82#include <asm/dma.h>
83#include <asm/types.h>
84#include <asm/uaccess.h>
85
86#include "linux/synclink.h"
87
88#ifdef CONFIG_HDLC_MODULE
89#define CONFIG_HDLC 1
90#endif
91
92/*
93 * module identification
94 */
95static char *driver_name = "SyncLink GT";
96static char *driver_version = "$Revision: 4.20 $";
97static char *tty_driver_name = "synclink_gt";
98static char *tty_dev_prefix = "ttySLG";
99MODULE_LICENSE("GPL");
100#define MGSL_MAGIC 0x5401
101#define MAX_DEVICES 12
102
103static struct pci_device_id pci_table[] = {
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {0,}, /* terminate list */
108};
109MODULE_DEVICE_TABLE(pci, pci_table);
110
111static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
112static void remove_one(struct pci_dev *dev);
113static struct pci_driver pci_driver = {
114 .name = "synclink_gt",
115 .id_table = pci_table,
116 .probe = init_one,
117 .remove = __devexit_p(remove_one),
118};
119
120static int pci_registered;
121
122/*
123 * module configuration and status
124 */
125static struct slgt_info *slgt_device_list;
126static int slgt_device_count;
127
128static int ttymajor;
129static int debug_level;
130static int maxframe[MAX_DEVICES];
131static int dosyncppp[MAX_DEVICES];
132
133module_param(ttymajor, int, 0);
134module_param(debug_level, int, 0);
135module_param_array(maxframe, int, NULL, 0);
136module_param_array(dosyncppp, int, NULL, 0);
137
138MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
139MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
140MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
141MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
142
143/*
144 * tty support and callbacks
145 */
146#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
147
148static struct tty_driver *serial_driver;
149
150static int open(struct tty_struct *tty, struct file * filp);
151static void close(struct tty_struct *tty, struct file * filp);
152static void hangup(struct tty_struct *tty);
153static void set_termios(struct tty_struct *tty, struct termios *old_termios);
154
155static int write(struct tty_struct *tty, const unsigned char *buf, int count);
156static void put_char(struct tty_struct *tty, unsigned char ch);
157static void send_xchar(struct tty_struct *tty, char ch);
158static void wait_until_sent(struct tty_struct *tty, int timeout);
159static int write_room(struct tty_struct *tty);
160static void flush_chars(struct tty_struct *tty);
161static void flush_buffer(struct tty_struct *tty);
162static void tx_hold(struct tty_struct *tty);
163static void tx_release(struct tty_struct *tty);
164
165static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
166static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
167static int chars_in_buffer(struct tty_struct *tty);
168static void throttle(struct tty_struct * tty);
169static void unthrottle(struct tty_struct * tty);
170static void set_break(struct tty_struct *tty, int break_state);
171
172/*
173 * generic HDLC support and callbacks
174 */
175#ifdef CONFIG_HDLC
176#define dev_to_port(D) (dev_to_hdlc(D)->priv)
177static void hdlcdev_tx_done(struct slgt_info *info);
178static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
179static int hdlcdev_init(struct slgt_info *info);
180static void hdlcdev_exit(struct slgt_info *info);
181#endif
182
183
184/*
185 * device specific structures, macros and functions
186 */
187
188#define SLGT_MAX_PORTS 4
189#define SLGT_REG_SIZE 256
190
191/*
192 * DMA buffer descriptor and access macros
193 */
194struct slgt_desc
195{
196 unsigned short count;
197 unsigned short status;
198 unsigned int pbuf; /* physical address of data buffer */
199 unsigned int next; /* physical address of next descriptor */
200
201 /* driver book keeping */
202 char *buf; /* virtual address of data buffer */
203 unsigned int pdesc; /* physical address of this descriptor */
204 dma_addr_t buf_dma_addr;
205};
206
207#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
208#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
209#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
210#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
211#define desc_count(a) (le16_to_cpu((a).count))
212#define desc_status(a) (le16_to_cpu((a).status))
213#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
214#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
215#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
216#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
217#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
218
219struct _input_signal_events {
220 int ri_up;
221 int ri_down;
222 int dsr_up;
223 int dsr_down;
224 int dcd_up;
225 int dcd_down;
226 int cts_up;
227 int cts_down;
228};
229
230/*
231 * device instance data structure
232 */
233struct slgt_info {
234 void *if_ptr; /* General purpose pointer (used by SPPP) */
235
236 struct slgt_info *next_device; /* device list link */
237
238 int magic;
239 int flags;
240
241 char device_name[25];
242 struct pci_dev *pdev;
243
244 int port_count; /* count of ports on adapter */
245 int adapter_num; /* adapter instance number */
246 int port_num; /* port instance number */
247
248 /* array of pointers to port contexts on this adapter */
249 struct slgt_info *port_array[SLGT_MAX_PORTS];
250
251 int count; /* count of opens */
252 int line; /* tty line instance number */
253 unsigned short close_delay;
254 unsigned short closing_wait; /* time to wait before closing */
255
256 struct mgsl_icount icount;
257
258 struct tty_struct *tty;
259 int timeout;
260 int x_char; /* xon/xoff character */
261 int blocked_open; /* # of blocked opens */
262 unsigned int read_status_mask;
263 unsigned int ignore_status_mask;
264
265 wait_queue_head_t open_wait;
266 wait_queue_head_t close_wait;
267
268 wait_queue_head_t status_event_wait_q;
269 wait_queue_head_t event_wait_q;
270 struct timer_list tx_timer;
271 struct timer_list rx_timer;
272
273 spinlock_t lock; /* spinlock for synchronizing with ISR */
274
275 struct work_struct task;
276 u32 pending_bh;
277 int bh_requested;
278 int bh_running;
279
280 int isr_overflow;
281 int irq_requested; /* nonzero if IRQ requested */
282 int irq_occurred; /* for diagnostics use */
283
284 /* device configuration */
285
286 unsigned int bus_type;
287 unsigned int irq_level;
288 unsigned long irq_flags;
289
290 unsigned char __iomem * reg_addr; /* memory mapped registers address */
291 u32 phys_reg_addr;
292 u32 reg_offset;
293 int reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int raw_rx_size;
300 unsigned int if_mode;
301
302 /* device status */
303
304 int rx_enabled;
305 int rx_restart;
306
307 int tx_enabled;
308 int tx_active;
309
310 unsigned char signals; /* serial signal states */
311 unsigned int init_error; /* initialization error */
312
313 unsigned char *tx_buf;
314 int tx_count;
315
316 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
317 char char_buf[MAX_ASYNC_BUFFER_SIZE];
318 BOOLEAN drop_rts_on_tx_done;
319 struct _input_signal_events input_signal_events;
320
321 int dcd_chkcount; /* check counts to prevent */
322 int cts_chkcount; /* too many IRQs if a signal */
323 int dsr_chkcount; /* is floating */
324 int ri_chkcount;
325
326 char *bufs; /* virtual address of DMA buffer lists */
327 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
328
329 unsigned int rbuf_count;
330 struct slgt_desc *rbufs;
331 unsigned int rbuf_current;
332 unsigned int rbuf_index;
333
334 unsigned int tbuf_count;
335 struct slgt_desc *tbufs;
336 unsigned int tbuf_current;
337 unsigned int tbuf_start;
338
339 unsigned char *tmp_rbuf;
340 unsigned int tmp_rbuf_count;
341
342 /* SPPP/Cisco HDLC device parts */
343
344 int netcount;
345 int dosyncppp;
346 spinlock_t netlock;
347#ifdef CONFIG_HDLC
348 struct net_device *netdev;
349#endif
350
351};
352
353static MGSL_PARAMS default_params = {
354 .mode = MGSL_MODE_HDLC,
355 .loopback = 0,
356 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
357 .encoding = HDLC_ENCODING_NRZI_SPACE,
358 .clock_speed = 0,
359 .addr_filter = 0xff,
360 .crc_type = HDLC_CRC_16_CCITT,
361 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
362 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
363 .data_rate = 9600,
364 .data_bits = 8,
365 .stop_bits = 1,
366 .parity = ASYNC_PARITY_NONE
367};
368
369
370#define BH_RECEIVE 1
371#define BH_TRANSMIT 2
372#define BH_STATUS 4
373#define IO_PIN_SHUTDOWN_LIMIT 100
374
375#define DMABUFSIZE 256
376#define DESC_LIST_SIZE 4096
377
378#define MASK_PARITY BIT1
379#define MASK_FRAMING BIT2
380#define MASK_BREAK BIT3
381#define MASK_OVERRUN BIT4
382
383#define GSR 0x00 /* global status */
384#define TDR 0x80 /* tx data */
385#define RDR 0x80 /* rx data */
386#define TCR 0x82 /* tx control */
387#define TIR 0x84 /* tx idle */
388#define TPR 0x85 /* tx preamble */
389#define RCR 0x86 /* rx control */
390#define VCR 0x88 /* V.24 control */
391#define CCR 0x89 /* clock control */
392#define BDR 0x8a /* baud divisor */
393#define SCR 0x8c /* serial control */
394#define SSR 0x8e /* serial status */
395#define RDCSR 0x90 /* rx DMA control/status */
396#define TDCSR 0x94 /* tx DMA control/status */
397#define RDDAR 0x98 /* rx DMA descriptor address */
398#define TDDAR 0x9c /* tx DMA descriptor address */
399
400#define RXIDLE BIT14
401#define RXBREAK BIT14
402#define IRQ_TXDATA BIT13
403#define IRQ_TXIDLE BIT12
404#define IRQ_TXUNDER BIT11 /* HDLC */
405#define IRQ_RXDATA BIT10
406#define IRQ_RXIDLE BIT9 /* HDLC */
407#define IRQ_RXBREAK BIT9 /* async */
408#define IRQ_RXOVER BIT8
409#define IRQ_DSR BIT7
410#define IRQ_CTS BIT6
411#define IRQ_DCD BIT5
412#define IRQ_RI BIT4
413#define IRQ_ALL 0x3ff0
414#define IRQ_MASTER BIT0
415
416#define slgt_irq_on(info, mask) \
417 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
418#define slgt_irq_off(info, mask) \
419 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
420
421static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
422static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
423static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
424static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
425static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
426static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
427
428static void msc_set_vcr(struct slgt_info *info);
429
430static int startup(struct slgt_info *info);
431static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
432static void shutdown(struct slgt_info *info);
433static void program_hw(struct slgt_info *info);
434static void change_params(struct slgt_info *info);
435
436static int register_test(struct slgt_info *info);
437static int irq_test(struct slgt_info *info);
438static int loopback_test(struct slgt_info *info);
439static int adapter_test(struct slgt_info *info);
440
441static void reset_adapter(struct slgt_info *info);
442static void reset_port(struct slgt_info *info);
443static void async_mode(struct slgt_info *info);
444static void hdlc_mode(struct slgt_info *info);
445
446static void rx_stop(struct slgt_info *info);
447static void rx_start(struct slgt_info *info);
448static void reset_rbufs(struct slgt_info *info);
449static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
450static void rdma_reset(struct slgt_info *info);
451static int rx_get_frame(struct slgt_info *info);
452static int rx_get_buf(struct slgt_info *info);
453
454static void tx_start(struct slgt_info *info);
455static void tx_stop(struct slgt_info *info);
456static void tx_set_idle(struct slgt_info *info);
457static unsigned int free_tbuf_count(struct slgt_info *info);
458static void reset_tbufs(struct slgt_info *info);
459static void tdma_reset(struct slgt_info *info);
460static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
461
462static void get_signals(struct slgt_info *info);
463static void set_signals(struct slgt_info *info);
464static void enable_loopback(struct slgt_info *info);
465static void set_rate(struct slgt_info *info, u32 data_rate);
466
467static int bh_action(struct slgt_info *info);
468static void bh_handler(void* context);
469static void bh_transmit(struct slgt_info *info);
470static void isr_serial(struct slgt_info *info);
471static void isr_rdma(struct slgt_info *info);
472static void isr_txeom(struct slgt_info *info, unsigned short status);
473static void isr_tdma(struct slgt_info *info);
474static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs);
475
476static int alloc_dma_bufs(struct slgt_info *info);
477static void free_dma_bufs(struct slgt_info *info);
478static int alloc_desc(struct slgt_info *info);
479static void free_desc(struct slgt_info *info);
480static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
481static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
482
483static int alloc_tmp_rbuf(struct slgt_info *info);
484static void free_tmp_rbuf(struct slgt_info *info);
485
486static void tx_timeout(unsigned long context);
487static void rx_timeout(unsigned long context);
488
489/*
490 * ioctl handlers
491 */
492static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
493static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
494static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
495static int get_txidle(struct slgt_info *info, int __user *idle_mode);
496static int set_txidle(struct slgt_info *info, int idle_mode);
497static int tx_enable(struct slgt_info *info, int enable);
498static int tx_abort(struct slgt_info *info);
499static int rx_enable(struct slgt_info *info, int enable);
500static int modem_input_wait(struct slgt_info *info,int arg);
501static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
502static int tiocmget(struct tty_struct *tty, struct file *file);
503static int tiocmset(struct tty_struct *tty, struct file *file,
504 unsigned int set, unsigned int clear);
505static void set_break(struct tty_struct *tty, int break_state);
506static int get_interface(struct slgt_info *info, int __user *if_mode);
507static int set_interface(struct slgt_info *info, int if_mode);
508
509/*
510 * driver functions
511 */
512static void add_device(struct slgt_info *info);
513static void device_init(int adapter_num, struct pci_dev *pdev);
514static int claim_resources(struct slgt_info *info);
515static void release_resources(struct slgt_info *info);
516
517/*
518 * DEBUG OUTPUT CODE
519 */
520#ifndef DBGINFO
521#define DBGINFO(fmt)
522#endif
523#ifndef DBGERR
524#define DBGERR(fmt)
525#endif
526#ifndef DBGBH
527#define DBGBH(fmt)
528#endif
529#ifndef DBGISR
530#define DBGISR(fmt)
531#endif
532
533#ifdef DBGDATA
534static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
535{
536 int i;
537 int linecount;
538 printk("%s %s data:\n",info->device_name, label);
539 while(count) {
540 linecount = (count > 16) ? 16 : count;
541 for(i=0; i < linecount; i++)
542 printk("%02X ",(unsigned char)data[i]);
543 for(;i<17;i++)
544 printk(" ");
545 for(i=0;i<linecount;i++) {
546 if (data[i]>=040 && data[i]<=0176)
547 printk("%c",data[i]);
548 else
549 printk(".");
550 }
551 printk("\n");
552 data += linecount;
553 count -= linecount;
554 }
555}
556#else
557#define DBGDATA(info, buf, size, label)
558#endif
559
560#ifdef DBGTBUF
561static void dump_tbufs(struct slgt_info *info)
562{
563 int i;
564 printk("tbuf_current=%d\n", info->tbuf_current);
565 for (i=0 ; i < info->tbuf_count ; i++) {
566 printk("%d: count=%04X status=%04X\n",
567 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
568 }
569}
570#else
571#define DBGTBUF(info)
572#endif
573
574#ifdef DBGRBUF
575static void dump_rbufs(struct slgt_info *info)
576{
577 int i;
578 printk("rbuf_current=%d\n", info->rbuf_current);
579 for (i=0 ; i < info->rbuf_count ; i++) {
580 printk("%d: count=%04X status=%04X\n",
581 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
582 }
583}
584#else
585#define DBGRBUF(info)
586#endif
587
588static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
589{
590#ifdef SANITY_CHECK
591 if (!info) {
592 printk("null struct slgt_info for (%s) in %s\n", devname, name);
593 return 1;
594 }
595 if (info->magic != MGSL_MAGIC) {
596 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
597 return 1;
598 }
599#else
600 if (!info)
601 return 1;
602#endif
603 return 0;
604}
605
606/**
607 * line discipline callback wrappers
608 *
609 * The wrappers maintain line discipline references
610 * while calling into the line discipline.
611 *
612 * ldisc_receive_buf - pass receive data to line discipline
613 */
614static void ldisc_receive_buf(struct tty_struct *tty,
615 const __u8 *data, char *flags, int count)
616{
617 struct tty_ldisc *ld;
618 if (!tty)
619 return;
620 ld = tty_ldisc_ref(tty);
621 if (ld) {
622 if (ld->receive_buf)
623 ld->receive_buf(tty, data, flags, count);
624 tty_ldisc_deref(ld);
625 }
626}
627
628/* tty callbacks */
629
630static int open(struct tty_struct *tty, struct file *filp)
631{
632 struct slgt_info *info;
633 int retval, line;
634 unsigned long flags;
635
636 line = tty->index;
637 if ((line < 0) || (line >= slgt_device_count)) {
638 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
639 return -ENODEV;
640 }
641
642 info = slgt_device_list;
643 while(info && info->line != line)
644 info = info->next_device;
645 if (sanity_check(info, tty->name, "open"))
646 return -ENODEV;
647 if (info->init_error) {
648 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
649 return -ENODEV;
650 }
651
652 tty->driver_data = info;
653 info->tty = tty;
654
655 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
656
657 /* If port is closing, signal caller to try again */
658 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
659 if (info->flags & ASYNC_CLOSING)
660 interruptible_sleep_on(&info->close_wait);
661 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
662 -EAGAIN : -ERESTARTSYS);
663 goto cleanup;
664 }
665
666 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
667
668 spin_lock_irqsave(&info->netlock, flags);
669 if (info->netcount) {
670 retval = -EBUSY;
671 spin_unlock_irqrestore(&info->netlock, flags);
672 goto cleanup;
673 }
674 info->count++;
675 spin_unlock_irqrestore(&info->netlock, flags);
676
677 if (info->count == 1) {
678 /* 1st open on this device, init hardware */
679 retval = startup(info);
680 if (retval < 0)
681 goto cleanup;
682 }
683
684 retval = block_til_ready(tty, filp, info);
685 if (retval) {
686 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
687 goto cleanup;
688 }
689
690 retval = 0;
691
692cleanup:
693 if (retval) {
694 if (tty->count == 1)
695 info->tty = NULL; /* tty layer will release tty struct */
696 if(info->count)
697 info->count--;
698 }
699
700 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
701 return retval;
702}
703
704static void close(struct tty_struct *tty, struct file *filp)
705{
706 struct slgt_info *info = tty->driver_data;
707
708 if (sanity_check(info, tty->name, "close"))
709 return;
710 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
711
712 if (!info->count)
713 return;
714
715 if (tty_hung_up_p(filp))
716 goto cleanup;
717
718 if ((tty->count == 1) && (info->count != 1)) {
719 /*
720 * tty->count is 1 and the tty structure will be freed.
721 * info->count should be one in this case.
722 * if it's not, correct it so that the port is shutdown.
723 */
724 DBGERR(("%s close: bad refcount; tty->count=1, "
725 "info->count=%d\n", info->device_name, info->count));
726 info->count = 1;
727 }
728
729 info->count--;
730
731 /* if at least one open remaining, leave hardware active */
732 if (info->count)
733 goto cleanup;
734
735 info->flags |= ASYNC_CLOSING;
736
737 /* set tty->closing to notify line discipline to
738 * only process XON/XOFF characters. Only the N_TTY
739 * discipline appears to use this (ppp does not).
740 */
741 tty->closing = 1;
742
743 /* wait for transmit data to clear all layers */
744
745 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
746 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
747 tty_wait_until_sent(tty, info->closing_wait);
748 }
749
750 if (info->flags & ASYNC_INITIALIZED)
751 wait_until_sent(tty, info->timeout);
752 if (tty->driver->flush_buffer)
753 tty->driver->flush_buffer(tty);
754 tty_ldisc_flush(tty);
755
756 shutdown(info);
757
758 tty->closing = 0;
759 info->tty = NULL;
760
761 if (info->blocked_open) {
762 if (info->close_delay) {
763 msleep_interruptible(jiffies_to_msecs(info->close_delay));
764 }
765 wake_up_interruptible(&info->open_wait);
766 }
767
768 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
769
770 wake_up_interruptible(&info->close_wait);
771
772cleanup:
773 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
774}
775
776static void hangup(struct tty_struct *tty)
777{
778 struct slgt_info *info = tty->driver_data;
779
780 if (sanity_check(info, tty->name, "hangup"))
781 return;
782 DBGINFO(("%s hangup\n", info->device_name));
783
784 flush_buffer(tty);
785 shutdown(info);
786
787 info->count = 0;
788 info->flags &= ~ASYNC_NORMAL_ACTIVE;
789 info->tty = NULL;
790
791 wake_up_interruptible(&info->open_wait);
792}
793
794static void set_termios(struct tty_struct *tty, struct termios *old_termios)
795{
796 struct slgt_info *info = tty->driver_data;
797 unsigned long flags;
798
799 DBGINFO(("%s set_termios\n", tty->driver->name));
800
801 /* just return if nothing has changed */
802 if ((tty->termios->c_cflag == old_termios->c_cflag)
803 && (RELEVANT_IFLAG(tty->termios->c_iflag)
804 == RELEVANT_IFLAG(old_termios->c_iflag)))
805 return;
806
807 change_params(info);
808
809 /* Handle transition to B0 status */
810 if (old_termios->c_cflag & CBAUD &&
811 !(tty->termios->c_cflag & CBAUD)) {
812 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
813 spin_lock_irqsave(&info->lock,flags);
814 set_signals(info);
815 spin_unlock_irqrestore(&info->lock,flags);
816 }
817
818 /* Handle transition away from B0 status */
819 if (!(old_termios->c_cflag & CBAUD) &&
820 tty->termios->c_cflag & CBAUD) {
821 info->signals |= SerialSignal_DTR;
822 if (!(tty->termios->c_cflag & CRTSCTS) ||
823 !test_bit(TTY_THROTTLED, &tty->flags)) {
824 info->signals |= SerialSignal_RTS;
825 }
826 spin_lock_irqsave(&info->lock,flags);
827 set_signals(info);
828 spin_unlock_irqrestore(&info->lock,flags);
829 }
830
831 /* Handle turning off CRTSCTS */
832 if (old_termios->c_cflag & CRTSCTS &&
833 !(tty->termios->c_cflag & CRTSCTS)) {
834 tty->hw_stopped = 0;
835 tx_release(tty);
836 }
837}
838
839static int write(struct tty_struct *tty,
840 const unsigned char *buf, int count)
841{
842 int ret = 0;
843 struct slgt_info *info = tty->driver_data;
844 unsigned long flags;
845
846 if (sanity_check(info, tty->name, "write"))
847 goto cleanup;
848 DBGINFO(("%s write count=%d\n", info->device_name, count));
849
850 if (!tty || !info->tx_buf)
851 goto cleanup;
852
853 if (count > info->max_frame_size) {
854 ret = -EIO;
855 goto cleanup;
856 }
857
858 if (!count)
859 goto cleanup;
860
861 if (info->params.mode == MGSL_MODE_RAW) {
862 unsigned int bufs_needed = (count/DMABUFSIZE);
863 unsigned int bufs_free = free_tbuf_count(info);
864 if (count % DMABUFSIZE)
865 ++bufs_needed;
866 if (bufs_needed > bufs_free)
867 goto cleanup;
868 } else {
869 if (info->tx_active)
870 goto cleanup;
871 if (info->tx_count) {
872 /* send accumulated data from send_char() calls */
873 /* as frame and wait before accepting more data. */
874 tx_load(info, info->tx_buf, info->tx_count);
875 goto start;
876 }
877 }
878
879 ret = info->tx_count = count;
880 tx_load(info, buf, count);
881 goto start;
882
883start:
884 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
885 spin_lock_irqsave(&info->lock,flags);
886 if (!info->tx_active)
887 tx_start(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891cleanup:
892 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
893 return ret;
894}
895
896static void put_char(struct tty_struct *tty, unsigned char ch)
897{
898 struct slgt_info *info = tty->driver_data;
899 unsigned long flags;
900
901 if (sanity_check(info, tty->name, "put_char"))
902 return;
903 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
904 if (!tty || !info->tx_buf)
905 return;
906 spin_lock_irqsave(&info->lock,flags);
907 if (!info->tx_active && (info->tx_count < info->max_frame_size))
908 info->tx_buf[info->tx_count++] = ch;
909 spin_unlock_irqrestore(&info->lock,flags);
910}
911
912static void send_xchar(struct tty_struct *tty, char ch)
913{
914 struct slgt_info *info = tty->driver_data;
915 unsigned long flags;
916
917 if (sanity_check(info, tty->name, "send_xchar"))
918 return;
919 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
920 info->x_char = ch;
921 if (ch) {
922 spin_lock_irqsave(&info->lock,flags);
923 if (!info->tx_enabled)
924 tx_start(info);
925 spin_unlock_irqrestore(&info->lock,flags);
926 }
927}
928
929static void wait_until_sent(struct tty_struct *tty, int timeout)
930{
931 struct slgt_info *info = tty->driver_data;
932 unsigned long orig_jiffies, char_time;
933
934 if (!info )
935 return;
936 if (sanity_check(info, tty->name, "wait_until_sent"))
937 return;
938 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
939 if (!(info->flags & ASYNC_INITIALIZED))
940 goto exit;
941
942 orig_jiffies = jiffies;
943
944 /* Set check interval to 1/5 of estimated time to
945 * send a character, and make it at least 1. The check
946 * interval should also be less than the timeout.
947 * Note: use tight timings here to satisfy the NIST-PCTS.
948 */
949
950 if (info->params.data_rate) {
951 char_time = info->timeout/(32 * 5);
952 if (!char_time)
953 char_time++;
954 } else
955 char_time = 1;
956
957 if (timeout)
958 char_time = min_t(unsigned long, char_time, timeout);
959
960 while (info->tx_active) {
961 msleep_interruptible(jiffies_to_msecs(char_time));
962 if (signal_pending(current))
963 break;
964 if (timeout && time_after(jiffies, orig_jiffies + timeout))
965 break;
966 }
967
968exit:
969 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
970}
971
972static int write_room(struct tty_struct *tty)
973{
974 struct slgt_info *info = tty->driver_data;
975 int ret;
976
977 if (sanity_check(info, tty->name, "write_room"))
978 return 0;
979 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
980 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
981 return ret;
982}
983
984static void flush_chars(struct tty_struct *tty)
985{
986 struct slgt_info *info = tty->driver_data;
987 unsigned long flags;
988
989 if (sanity_check(info, tty->name, "flush_chars"))
990 return;
991 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
992
993 if (info->tx_count <= 0 || tty->stopped ||
994 tty->hw_stopped || !info->tx_buf)
995 return;
996
997 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
998
999 spin_lock_irqsave(&info->lock,flags);
1000 if (!info->tx_active && info->tx_count) {
1001 tx_load(info, info->tx_buf,info->tx_count);
1002 tx_start(info);
1003 }
1004 spin_unlock_irqrestore(&info->lock,flags);
1005}
1006
1007static void flush_buffer(struct tty_struct *tty)
1008{
1009 struct slgt_info *info = tty->driver_data;
1010 unsigned long flags;
1011
1012 if (sanity_check(info, tty->name, "flush_buffer"))
1013 return;
1014 DBGINFO(("%s flush_buffer\n", info->device_name));
1015
1016 spin_lock_irqsave(&info->lock,flags);
1017 if (!info->tx_active)
1018 info->tx_count = 0;
1019 spin_unlock_irqrestore(&info->lock,flags);
1020
1021 wake_up_interruptible(&tty->write_wait);
1022 tty_wakeup(tty);
1023}
1024
1025/*
1026 * throttle (stop) transmitter
1027 */
1028static void tx_hold(struct tty_struct *tty)
1029{
1030 struct slgt_info *info = tty->driver_data;
1031 unsigned long flags;
1032
1033 if (sanity_check(info, tty->name, "tx_hold"))
1034 return;
1035 DBGINFO(("%s tx_hold\n", info->device_name));
1036 spin_lock_irqsave(&info->lock,flags);
1037 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1038 tx_stop(info);
1039 spin_unlock_irqrestore(&info->lock,flags);
1040}
1041
1042/*
1043 * release (start) transmitter
1044 */
1045static void tx_release(struct tty_struct *tty)
1046{
1047 struct slgt_info *info = tty->driver_data;
1048 unsigned long flags;
1049
1050 if (sanity_check(info, tty->name, "tx_release"))
1051 return;
1052 DBGINFO(("%s tx_release\n", info->device_name));
1053 spin_lock_irqsave(&info->lock,flags);
1054 if (!info->tx_active && info->tx_count) {
1055 tx_load(info, info->tx_buf, info->tx_count);
1056 tx_start(info);
1057 }
1058 spin_unlock_irqrestore(&info->lock,flags);
1059}
1060
1061/*
1062 * Service an IOCTL request
1063 *
1064 * Arguments
1065 *
1066 * tty pointer to tty instance data
1067 * file pointer to associated file object for device
1068 * cmd IOCTL command code
1069 * arg command argument/context
1070 *
1071 * Return 0 if success, otherwise error code
1072 */
1073static int ioctl(struct tty_struct *tty, struct file *file,
1074 unsigned int cmd, unsigned long arg)
1075{
1076 struct slgt_info *info = tty->driver_data;
1077 struct mgsl_icount cnow; /* kernel counter temps */
1078 struct serial_icounter_struct __user *p_cuser; /* user space */
1079 unsigned long flags;
1080 void __user *argp = (void __user *)arg;
1081
1082 if (sanity_check(info, tty->name, "ioctl"))
1083 return -ENODEV;
1084 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1085
1086 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1087 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1088 if (tty->flags & (1 << TTY_IO_ERROR))
1089 return -EIO;
1090 }
1091
1092 switch (cmd) {
1093 case MGSL_IOCGPARAMS:
1094 return get_params(info, argp);
1095 case MGSL_IOCSPARAMS:
1096 return set_params(info, argp);
1097 case MGSL_IOCGTXIDLE:
1098 return get_txidle(info, argp);
1099 case MGSL_IOCSTXIDLE:
1100 return set_txidle(info, (int)arg);
1101 case MGSL_IOCTXENABLE:
1102 return tx_enable(info, (int)arg);
1103 case MGSL_IOCRXENABLE:
1104 return rx_enable(info, (int)arg);
1105 case MGSL_IOCTXABORT:
1106 return tx_abort(info);
1107 case MGSL_IOCGSTATS:
1108 return get_stats(info, argp);
1109 case MGSL_IOCWAITEVENT:
1110 return wait_mgsl_event(info, argp);
1111 case TIOCMIWAIT:
1112 return modem_input_wait(info,(int)arg);
1113 case MGSL_IOCGIF:
1114 return get_interface(info, argp);
1115 case MGSL_IOCSIF:
1116 return set_interface(info,(int)arg);
1117 case TIOCGICOUNT:
1118 spin_lock_irqsave(&info->lock,flags);
1119 cnow = info->icount;
1120 spin_unlock_irqrestore(&info->lock,flags);
1121 p_cuser = argp;
1122 if (put_user(cnow.cts, &p_cuser->cts) ||
1123 put_user(cnow.dsr, &p_cuser->dsr) ||
1124 put_user(cnow.rng, &p_cuser->rng) ||
1125 put_user(cnow.dcd, &p_cuser->dcd) ||
1126 put_user(cnow.rx, &p_cuser->rx) ||
1127 put_user(cnow.tx, &p_cuser->tx) ||
1128 put_user(cnow.frame, &p_cuser->frame) ||
1129 put_user(cnow.overrun, &p_cuser->overrun) ||
1130 put_user(cnow.parity, &p_cuser->parity) ||
1131 put_user(cnow.brk, &p_cuser->brk) ||
1132 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1133 return -EFAULT;
1134 return 0;
1135 default:
1136 return -ENOIOCTLCMD;
1137 }
1138 return 0;
1139}
1140
1141/*
1142 * proc fs support
1143 */
1144static inline int line_info(char *buf, struct slgt_info *info)
1145{
1146 char stat_buf[30];
1147 int ret;
1148 unsigned long flags;
1149
1150 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1151 info->device_name, info->phys_reg_addr,
1152 info->irq_level, info->max_frame_size);
1153
1154 /* output current serial signal states */
1155 spin_lock_irqsave(&info->lock,flags);
1156 get_signals(info);
1157 spin_unlock_irqrestore(&info->lock,flags);
1158
1159 stat_buf[0] = 0;
1160 stat_buf[1] = 0;
1161 if (info->signals & SerialSignal_RTS)
1162 strcat(stat_buf, "|RTS");
1163 if (info->signals & SerialSignal_CTS)
1164 strcat(stat_buf, "|CTS");
1165 if (info->signals & SerialSignal_DTR)
1166 strcat(stat_buf, "|DTR");
1167 if (info->signals & SerialSignal_DSR)
1168 strcat(stat_buf, "|DSR");
1169 if (info->signals & SerialSignal_DCD)
1170 strcat(stat_buf, "|CD");
1171 if (info->signals & SerialSignal_RI)
1172 strcat(stat_buf, "|RI");
1173
1174 if (info->params.mode != MGSL_MODE_ASYNC) {
1175 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1176 info->icount.txok, info->icount.rxok);
1177 if (info->icount.txunder)
1178 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1179 if (info->icount.txabort)
1180 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1181 if (info->icount.rxshort)
1182 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1183 if (info->icount.rxlong)
1184 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1185 if (info->icount.rxover)
1186 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1187 if (info->icount.rxcrc)
1188 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1189 } else {
1190 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1191 info->icount.tx, info->icount.rx);
1192 if (info->icount.frame)
1193 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1194 if (info->icount.parity)
1195 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1196 if (info->icount.brk)
1197 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1198 if (info->icount.overrun)
1199 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1200 }
1201
1202 /* Append serial signal status to end */
1203 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1204
1205 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1206 info->tx_active,info->bh_requested,info->bh_running,
1207 info->pending_bh);
1208
1209 return ret;
1210}
1211
1212/* Called to print information about devices
1213 */
1214static int read_proc(char *page, char **start, off_t off, int count,
1215 int *eof, void *data)
1216{
1217 int len = 0, l;
1218 off_t begin = 0;
1219 struct slgt_info *info;
1220
1221 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1222
1223 info = slgt_device_list;
1224 while( info ) {
1225 l = line_info(page + len, info);
1226 len += l;
1227 if (len+begin > off+count)
1228 goto done;
1229 if (len+begin < off) {
1230 begin += len;
1231 len = 0;
1232 }
1233 info = info->next_device;
1234 }
1235
1236 *eof = 1;
1237done:
1238 if (off >= len+begin)
1239 return 0;
1240 *start = page + (off-begin);
1241 return ((count < begin+len-off) ? count : begin+len-off);
1242}
1243
1244/*
1245 * return count of bytes in transmit buffer
1246 */
1247static int chars_in_buffer(struct tty_struct *tty)
1248{
1249 struct slgt_info *info = tty->driver_data;
1250 if (sanity_check(info, tty->name, "chars_in_buffer"))
1251 return 0;
1252 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1253 return info->tx_count;
1254}
1255
1256/*
1257 * signal remote device to throttle send data (our receive data)
1258 */
1259static void throttle(struct tty_struct * tty)
1260{
1261 struct slgt_info *info = tty->driver_data;
1262 unsigned long flags;
1263
1264 if (sanity_check(info, tty->name, "throttle"))
1265 return;
1266 DBGINFO(("%s throttle\n", info->device_name));
1267 if (I_IXOFF(tty))
1268 send_xchar(tty, STOP_CHAR(tty));
1269 if (tty->termios->c_cflag & CRTSCTS) {
1270 spin_lock_irqsave(&info->lock,flags);
1271 info->signals &= ~SerialSignal_RTS;
1272 set_signals(info);
1273 spin_unlock_irqrestore(&info->lock,flags);
1274 }
1275}
1276
1277/*
1278 * signal remote device to stop throttling send data (our receive data)
1279 */
1280static void unthrottle(struct tty_struct * tty)
1281{
1282 struct slgt_info *info = tty->driver_data;
1283 unsigned long flags;
1284
1285 if (sanity_check(info, tty->name, "unthrottle"))
1286 return;
1287 DBGINFO(("%s unthrottle\n", info->device_name));
1288 if (I_IXOFF(tty)) {
1289 if (info->x_char)
1290 info->x_char = 0;
1291 else
1292 send_xchar(tty, START_CHAR(tty));
1293 }
1294 if (tty->termios->c_cflag & CRTSCTS) {
1295 spin_lock_irqsave(&info->lock,flags);
1296 info->signals |= SerialSignal_RTS;
1297 set_signals(info);
1298 spin_unlock_irqrestore(&info->lock,flags);
1299 }
1300}
1301
1302/*
1303 * set or clear transmit break condition
1304 * break_state -1=set break condition, 0=clear
1305 */
1306static void set_break(struct tty_struct *tty, int break_state)
1307{
1308 struct slgt_info *info = tty->driver_data;
1309 unsigned short value;
1310 unsigned long flags;
1311
1312 if (sanity_check(info, tty->name, "set_break"))
1313 return;
1314 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1315
1316 spin_lock_irqsave(&info->lock,flags);
1317 value = rd_reg16(info, TCR);
1318 if (break_state == -1)
1319 value |= BIT6;
1320 else
1321 value &= ~BIT6;
1322 wr_reg16(info, TCR, value);
1323 spin_unlock_irqrestore(&info->lock,flags);
1324}
1325
1326#ifdef CONFIG_HDLC
1327
1328/**
1329 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1330 * set encoding and frame check sequence (FCS) options
1331 *
1332 * dev pointer to network device structure
1333 * encoding serial encoding setting
1334 * parity FCS setting
1335 *
1336 * returns 0 if success, otherwise error code
1337 */
1338static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1339 unsigned short parity)
1340{
1341 struct slgt_info *info = dev_to_port(dev);
1342 unsigned char new_encoding;
1343 unsigned short new_crctype;
1344
1345 /* return error if TTY interface open */
1346 if (info->count)
1347 return -EBUSY;
1348
1349 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1350
1351 switch (encoding)
1352 {
1353 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1354 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1355 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1356 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1357 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1358 default: return -EINVAL;
1359 }
1360
1361 switch (parity)
1362 {
1363 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1364 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1365 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1366 default: return -EINVAL;
1367 }
1368
1369 info->params.encoding = new_encoding;
1370 info->params.crc_type = new_crctype;;
1371
1372 /* if network interface up, reprogram hardware */
1373 if (info->netcount)
1374 program_hw(info);
1375
1376 return 0;
1377}
1378
1379/**
1380 * called by generic HDLC layer to send frame
1381 *
1382 * skb socket buffer containing HDLC frame
1383 * dev pointer to network device structure
1384 *
1385 * returns 0 if success, otherwise error code
1386 */
1387static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1388{
1389 struct slgt_info *info = dev_to_port(dev);
1390 struct net_device_stats *stats = hdlc_stats(dev);
1391 unsigned long flags;
1392
1393 DBGINFO(("%s hdlc_xmit\n", dev->name));
1394
1395 /* stop sending until this frame completes */
1396 netif_stop_queue(dev);
1397
1398 /* copy data to device buffers */
1399 info->tx_count = skb->len;
1400 tx_load(info, skb->data, skb->len);
1401
1402 /* update network statistics */
1403 stats->tx_packets++;
1404 stats->tx_bytes += skb->len;
1405
1406 /* done with socket buffer, so free it */
1407 dev_kfree_skb(skb);
1408
1409 /* save start time for transmit timeout detection */
1410 dev->trans_start = jiffies;
1411
1412 /* start hardware transmitter if necessary */
1413 spin_lock_irqsave(&info->lock,flags);
1414 if (!info->tx_active)
1415 tx_start(info);
1416 spin_unlock_irqrestore(&info->lock,flags);
1417
1418 return 0;
1419}
1420
1421/**
1422 * called by network layer when interface enabled
1423 * claim resources and initialize hardware
1424 *
1425 * dev pointer to network device structure
1426 *
1427 * returns 0 if success, otherwise error code
1428 */
1429static int hdlcdev_open(struct net_device *dev)
1430{
1431 struct slgt_info *info = dev_to_port(dev);
1432 int rc;
1433 unsigned long flags;
1434
1435 DBGINFO(("%s hdlcdev_open\n", dev->name));
1436
1437 /* generic HDLC layer open processing */
1438 if ((rc = hdlc_open(dev)))
1439 return rc;
1440
1441 /* arbitrate between network and tty opens */
1442 spin_lock_irqsave(&info->netlock, flags);
1443 if (info->count != 0 || info->netcount != 0) {
1444 DBGINFO(("%s hdlc_open busy\n", dev->name));
1445 spin_unlock_irqrestore(&info->netlock, flags);
1446 return -EBUSY;
1447 }
1448 info->netcount=1;
1449 spin_unlock_irqrestore(&info->netlock, flags);
1450
1451 /* claim resources and init adapter */
1452 if ((rc = startup(info)) != 0) {
1453 spin_lock_irqsave(&info->netlock, flags);
1454 info->netcount=0;
1455 spin_unlock_irqrestore(&info->netlock, flags);
1456 return rc;
1457 }
1458
1459 /* assert DTR and RTS, apply hardware settings */
1460 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1461 program_hw(info);
1462
1463 /* enable network layer transmit */
1464 dev->trans_start = jiffies;
1465 netif_start_queue(dev);
1466
1467 /* inform generic HDLC layer of current DCD status */
1468 spin_lock_irqsave(&info->lock, flags);
1469 get_signals(info);
1470 spin_unlock_irqrestore(&info->lock, flags);
1471 hdlc_set_carrier(info->signals & SerialSignal_DCD, dev);
1472
1473 return 0;
1474}
1475
1476/**
1477 * called by network layer when interface is disabled
1478 * shutdown hardware and release resources
1479 *
1480 * dev pointer to network device structure
1481 *
1482 * returns 0 if success, otherwise error code
1483 */
1484static int hdlcdev_close(struct net_device *dev)
1485{
1486 struct slgt_info *info = dev_to_port(dev);
1487 unsigned long flags;
1488
1489 DBGINFO(("%s hdlcdev_close\n", dev->name));
1490
1491 netif_stop_queue(dev);
1492
1493 /* shutdown adapter and release resources */
1494 shutdown(info);
1495
1496 hdlc_close(dev);
1497
1498 spin_lock_irqsave(&info->netlock, flags);
1499 info->netcount=0;
1500 spin_unlock_irqrestore(&info->netlock, flags);
1501
1502 return 0;
1503}
1504
1505/**
1506 * called by network layer to process IOCTL call to network device
1507 *
1508 * dev pointer to network device structure
1509 * ifr pointer to network interface request structure
1510 * cmd IOCTL command code
1511 *
1512 * returns 0 if success, otherwise error code
1513 */
1514static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1515{
1516 const size_t size = sizeof(sync_serial_settings);
1517 sync_serial_settings new_line;
1518 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1519 struct slgt_info *info = dev_to_port(dev);
1520 unsigned int flags;
1521
1522 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1523
1524 /* return error if TTY interface open */
1525 if (info->count)
1526 return -EBUSY;
1527
1528 if (cmd != SIOCWANDEV)
1529 return hdlc_ioctl(dev, ifr, cmd);
1530
1531 switch(ifr->ifr_settings.type) {
1532 case IF_GET_IFACE: /* return current sync_serial_settings */
1533
1534 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1535 if (ifr->ifr_settings.size < size) {
1536 ifr->ifr_settings.size = size; /* data size wanted */
1537 return -ENOBUFS;
1538 }
1539
1540 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1541 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1542 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1543 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1544
1545 switch (flags){
1546 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1547 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1548 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1549 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1550 default: new_line.clock_type = CLOCK_DEFAULT;
1551 }
1552
1553 new_line.clock_rate = info->params.clock_speed;
1554 new_line.loopback = info->params.loopback ? 1:0;
1555
1556 if (copy_to_user(line, &new_line, size))
1557 return -EFAULT;
1558 return 0;
1559
1560 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1561
1562 if(!capable(CAP_NET_ADMIN))
1563 return -EPERM;
1564 if (copy_from_user(&new_line, line, size))
1565 return -EFAULT;
1566
1567 switch (new_line.clock_type)
1568 {
1569 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1570 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1571 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1572 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1573 case CLOCK_DEFAULT: flags = info->params.flags &
1574 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1575 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1576 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1577 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1578 default: return -EINVAL;
1579 }
1580
1581 if (new_line.loopback != 0 && new_line.loopback != 1)
1582 return -EINVAL;
1583
1584 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1585 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1586 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1587 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1588 info->params.flags |= flags;
1589
1590 info->params.loopback = new_line.loopback;
1591
1592 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1593 info->params.clock_speed = new_line.clock_rate;
1594 else
1595 info->params.clock_speed = 0;
1596
1597 /* if network interface up, reprogram hardware */
1598 if (info->netcount)
1599 program_hw(info);
1600 return 0;
1601
1602 default:
1603 return hdlc_ioctl(dev, ifr, cmd);
1604 }
1605}
1606
1607/**
1608 * called by network layer when transmit timeout is detected
1609 *
1610 * dev pointer to network device structure
1611 */
1612static void hdlcdev_tx_timeout(struct net_device *dev)
1613{
1614 struct slgt_info *info = dev_to_port(dev);
1615 struct net_device_stats *stats = hdlc_stats(dev);
1616 unsigned long flags;
1617
1618 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1619
1620 stats->tx_errors++;
1621 stats->tx_aborted_errors++;
1622
1623 spin_lock_irqsave(&info->lock,flags);
1624 tx_stop(info);
1625 spin_unlock_irqrestore(&info->lock,flags);
1626
1627 netif_wake_queue(dev);
1628}
1629
1630/**
1631 * called by device driver when transmit completes
1632 * reenable network layer transmit if stopped
1633 *
1634 * info pointer to device instance information
1635 */
1636static void hdlcdev_tx_done(struct slgt_info *info)
1637{
1638 if (netif_queue_stopped(info->netdev))
1639 netif_wake_queue(info->netdev);
1640}
1641
1642/**
1643 * called by device driver when frame received
1644 * pass frame to network layer
1645 *
1646 * info pointer to device instance information
1647 * buf pointer to buffer contianing frame data
1648 * size count of data bytes in buf
1649 */
1650static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1651{
1652 struct sk_buff *skb = dev_alloc_skb(size);
1653 struct net_device *dev = info->netdev;
1654 struct net_device_stats *stats = hdlc_stats(dev);
1655
1656 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1657
1658 if (skb == NULL) {
1659 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1660 stats->rx_dropped++;
1661 return;
1662 }
1663
1664 memcpy(skb_put(skb, size),buf,size);
1665
1666 skb->protocol = hdlc_type_trans(skb, info->netdev);
1667
1668 stats->rx_packets++;
1669 stats->rx_bytes += size;
1670
1671 netif_rx(skb);
1672
1673 info->netdev->last_rx = jiffies;
1674}
1675
1676/**
1677 * called by device driver when adding device instance
1678 * do generic HDLC initialization
1679 *
1680 * info pointer to device instance information
1681 *
1682 * returns 0 if success, otherwise error code
1683 */
1684static int hdlcdev_init(struct slgt_info *info)
1685{
1686 int rc;
1687 struct net_device *dev;
1688 hdlc_device *hdlc;
1689
1690 /* allocate and initialize network and HDLC layer objects */
1691
1692 if (!(dev = alloc_hdlcdev(info))) {
1693 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1694 return -ENOMEM;
1695 }
1696
1697 /* for network layer reporting purposes only */
1698 dev->mem_start = info->phys_reg_addr;
1699 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1700 dev->irq = info->irq_level;
1701
1702 /* network layer callbacks and settings */
1703 dev->do_ioctl = hdlcdev_ioctl;
1704 dev->open = hdlcdev_open;
1705 dev->stop = hdlcdev_close;
1706 dev->tx_timeout = hdlcdev_tx_timeout;
1707 dev->watchdog_timeo = 10*HZ;
1708 dev->tx_queue_len = 50;
1709
1710 /* generic HDLC layer callbacks and settings */
1711 hdlc = dev_to_hdlc(dev);
1712 hdlc->attach = hdlcdev_attach;
1713 hdlc->xmit = hdlcdev_xmit;
1714
1715 /* register objects with HDLC layer */
1716 if ((rc = register_hdlc_device(dev))) {
1717 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1718 free_netdev(dev);
1719 return rc;
1720 }
1721
1722 info->netdev = dev;
1723 return 0;
1724}
1725
1726/**
1727 * called by device driver when removing device instance
1728 * do generic HDLC cleanup
1729 *
1730 * info pointer to device instance information
1731 */
1732static void hdlcdev_exit(struct slgt_info *info)
1733{
1734 unregister_hdlc_device(info->netdev);
1735 free_netdev(info->netdev);
1736 info->netdev = NULL;
1737}
1738
1739#endif /* ifdef CONFIG_HDLC */
1740
1741/*
1742 * get async data from rx DMA buffers
1743 */
1744static void rx_async(struct slgt_info *info)
1745{
1746 struct tty_struct *tty = info->tty;
1747 struct mgsl_icount *icount = &info->icount;
1748 unsigned int start, end;
1749 unsigned char *p;
1750 unsigned char status;
1751 struct slgt_desc *bufs = info->rbufs;
1752 int i, count;
1753
1754 start = end = info->rbuf_current;
1755
1756 while(desc_complete(bufs[end])) {
1757 count = desc_count(bufs[end]) - info->rbuf_index;
1758 p = bufs[end].buf + info->rbuf_index;
1759
1760 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1761 DBGDATA(info, p, count, "rx");
1762
1763 for(i=0 ; i < count; i+=2, p+=2) {
1764 if (tty) {
1765 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1766 tty_flip_buffer_push(tty);
1767 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1768 break;
1769 *tty->flip.char_buf_ptr = *p;
1770 *tty->flip.flag_buf_ptr = 0;
1771 }
1772 icount->rx++;
1773
1774 if ((status = *(p+1) & (BIT9 + BIT8))) {
1775 if (status & BIT9)
1776 icount->parity++;
1777 else if (status & BIT8)
1778 icount->frame++;
1779 /* discard char if tty control flags say so */
1780 if (status & info->ignore_status_mask)
1781 continue;
1782 if (tty) {
1783 if (status & BIT9)
1784 *tty->flip.flag_buf_ptr = TTY_PARITY;
1785 else if (status & BIT8)
1786 *tty->flip.flag_buf_ptr = TTY_FRAME;
1787 }
1788 }
1789 if (tty) {
1790 tty->flip.flag_buf_ptr++;
1791 tty->flip.char_buf_ptr++;
1792 tty->flip.count++;
1793 }
1794 }
1795
1796 if (i < count) {
1797 /* receive buffer not completed */
1798 info->rbuf_index += i;
1799 info->rx_timer.expires = jiffies + 1;
1800 add_timer(&info->rx_timer);
1801 break;
1802 }
1803
1804 info->rbuf_index = 0;
1805 free_rbufs(info, end, end);
1806
1807 if (++end == info->rbuf_count)
1808 end = 0;
1809
1810 /* if entire list searched then no frame available */
1811 if (end == start)
1812 break;
1813 }
1814
1815 if (tty && tty->flip.count)
1816 tty_flip_buffer_push(tty);
1817}
1818
1819/*
1820 * return next bottom half action to perform
1821 */
1822static int bh_action(struct slgt_info *info)
1823{
1824 unsigned long flags;
1825 int rc;
1826
1827 spin_lock_irqsave(&info->lock,flags);
1828
1829 if (info->pending_bh & BH_RECEIVE) {
1830 info->pending_bh &= ~BH_RECEIVE;
1831 rc = BH_RECEIVE;
1832 } else if (info->pending_bh & BH_TRANSMIT) {
1833 info->pending_bh &= ~BH_TRANSMIT;
1834 rc = BH_TRANSMIT;
1835 } else if (info->pending_bh & BH_STATUS) {
1836 info->pending_bh &= ~BH_STATUS;
1837 rc = BH_STATUS;
1838 } else {
1839 /* Mark BH routine as complete */
1840 info->bh_running = 0;
1841 info->bh_requested = 0;
1842 rc = 0;
1843 }
1844
1845 spin_unlock_irqrestore(&info->lock,flags);
1846
1847 return rc;
1848}
1849
1850/*
1851 * perform bottom half processing
1852 */
1853static void bh_handler(void* context)
1854{
1855 struct slgt_info *info = context;
1856 int action;
1857
1858 if (!info)
1859 return;
1860 info->bh_running = 1;
1861
1862 while((action = bh_action(info))) {
1863 switch (action) {
1864 case BH_RECEIVE:
1865 DBGBH(("%s bh receive\n", info->device_name));
1866 switch(info->params.mode) {
1867 case MGSL_MODE_ASYNC:
1868 rx_async(info);
1869 break;
1870 case MGSL_MODE_HDLC:
1871 while(rx_get_frame(info));
1872 break;
1873 case MGSL_MODE_RAW:
1874 while(rx_get_buf(info));
1875 break;
1876 }
1877 /* restart receiver if rx DMA buffers exhausted */
1878 if (info->rx_restart)
1879 rx_start(info);
1880 break;
1881 case BH_TRANSMIT:
1882 bh_transmit(info);
1883 break;
1884 case BH_STATUS:
1885 DBGBH(("%s bh status\n", info->device_name));
1886 info->ri_chkcount = 0;
1887 info->dsr_chkcount = 0;
1888 info->dcd_chkcount = 0;
1889 info->cts_chkcount = 0;
1890 break;
1891 default:
1892 DBGBH(("%s unknown action\n", info->device_name));
1893 break;
1894 }
1895 }
1896 DBGBH(("%s bh_handler exit\n", info->device_name));
1897}
1898
1899static void bh_transmit(struct slgt_info *info)
1900{
1901 struct tty_struct *tty = info->tty;
1902
1903 DBGBH(("%s bh_transmit\n", info->device_name));
1904 if (tty) {
1905 tty_wakeup(tty);
1906 wake_up_interruptible(&tty->write_wait);
1907 }
1908}
1909
1910static void dsr_change(struct slgt_info *info)
1911{
1912 get_signals(info);
1913 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1914 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1915 slgt_irq_off(info, IRQ_DSR);
1916 return;
1917 }
1918 info->icount.dsr++;
1919 if (info->signals & SerialSignal_DSR)
1920 info->input_signal_events.dsr_up++;
1921 else
1922 info->input_signal_events.dsr_down++;
1923 wake_up_interruptible(&info->status_event_wait_q);
1924 wake_up_interruptible(&info->event_wait_q);
1925 info->pending_bh |= BH_STATUS;
1926}
1927
1928static void cts_change(struct slgt_info *info)
1929{
1930 get_signals(info);
1931 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1932 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1933 slgt_irq_off(info, IRQ_CTS);
1934 return;
1935 }
1936 info->icount.cts++;
1937 if (info->signals & SerialSignal_CTS)
1938 info->input_signal_events.cts_up++;
1939 else
1940 info->input_signal_events.cts_down++;
1941 wake_up_interruptible(&info->status_event_wait_q);
1942 wake_up_interruptible(&info->event_wait_q);
1943 info->pending_bh |= BH_STATUS;
1944
1945 if (info->flags & ASYNC_CTS_FLOW) {
1946 if (info->tty) {
1947 if (info->tty->hw_stopped) {
1948 if (info->signals & SerialSignal_CTS) {
1949 info->tty->hw_stopped = 0;
1950 info->pending_bh |= BH_TRANSMIT;
1951 return;
1952 }
1953 } else {
1954 if (!(info->signals & SerialSignal_CTS))
1955 info->tty->hw_stopped = 1;
1956 }
1957 }
1958 }
1959}
1960
1961static void dcd_change(struct slgt_info *info)
1962{
1963 get_signals(info);
1964 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1965 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1966 slgt_irq_off(info, IRQ_DCD);
1967 return;
1968 }
1969 info->icount.dcd++;
1970 if (info->signals & SerialSignal_DCD) {
1971 info->input_signal_events.dcd_up++;
1972 } else {
1973 info->input_signal_events.dcd_down++;
1974 }
1975#ifdef CONFIG_HDLC
1976 if (info->netcount)
1977 hdlc_set_carrier(info->signals & SerialSignal_DCD, info->netdev);
1978#endif
1979 wake_up_interruptible(&info->status_event_wait_q);
1980 wake_up_interruptible(&info->event_wait_q);
1981 info->pending_bh |= BH_STATUS;
1982
1983 if (info->flags & ASYNC_CHECK_CD) {
1984 if (info->signals & SerialSignal_DCD)
1985 wake_up_interruptible(&info->open_wait);
1986 else {
1987 if (info->tty)
1988 tty_hangup(info->tty);
1989 }
1990 }
1991}
1992
1993static void ri_change(struct slgt_info *info)
1994{
1995 get_signals(info);
1996 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
1997 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1998 slgt_irq_off(info, IRQ_RI);
1999 return;
2000 }
2001 info->icount.dcd++;
2002 if (info->signals & SerialSignal_RI) {
2003 info->input_signal_events.ri_up++;
2004 } else {
2005 info->input_signal_events.ri_down++;
2006 }
2007 wake_up_interruptible(&info->status_event_wait_q);
2008 wake_up_interruptible(&info->event_wait_q);
2009 info->pending_bh |= BH_STATUS;
2010}
2011
2012static void isr_serial(struct slgt_info *info)
2013{
2014 unsigned short status = rd_reg16(info, SSR);
2015
2016 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2017
2018 wr_reg16(info, SSR, status); /* clear pending */
2019
2020 info->irq_occurred = 1;
2021
2022 if (info->params.mode == MGSL_MODE_ASYNC) {
2023 if (status & IRQ_TXIDLE) {
2024 if (info->tx_count)
2025 isr_txeom(info, status);
2026 }
2027 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2028 info->icount.brk++;
2029 /* process break detection if tty control allows */
2030 if (info->tty) {
2031 if (!(status & info->ignore_status_mask)) {
2032 if (info->read_status_mask & MASK_BREAK) {
2033 *info->tty->flip.flag_buf_ptr = TTY_BREAK;
2034 if (info->flags & ASYNC_SAK)
2035 do_SAK(info->tty);
2036 }
2037 }
2038 }
2039 }
2040 } else {
2041 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2042 isr_txeom(info, status);
2043
2044 if (status & IRQ_RXIDLE) {
2045 if (status & RXIDLE)
2046 info->icount.rxidle++;
2047 else
2048 info->icount.exithunt++;
2049 wake_up_interruptible(&info->event_wait_q);
2050 }
2051
2052 if (status & IRQ_RXOVER)
2053 rx_start(info);
2054 }
2055
2056 if (status & IRQ_DSR)
2057 dsr_change(info);
2058 if (status & IRQ_CTS)
2059 cts_change(info);
2060 if (status & IRQ_DCD)
2061 dcd_change(info);
2062 if (status & IRQ_RI)
2063 ri_change(info);
2064}
2065
2066static void isr_rdma(struct slgt_info *info)
2067{
2068 unsigned int status = rd_reg32(info, RDCSR);
2069
2070 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2071
2072 /* RDCSR (rx DMA control/status)
2073 *
2074 * 31..07 reserved
2075 * 06 save status byte to DMA buffer
2076 * 05 error
2077 * 04 eol (end of list)
2078 * 03 eob (end of buffer)
2079 * 02 IRQ enable
2080 * 01 reset
2081 * 00 enable
2082 */
2083 wr_reg32(info, RDCSR, status); /* clear pending */
2084
2085 if (status & (BIT5 + BIT4)) {
2086 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2087 info->rx_restart = 1;
2088 }
2089 info->pending_bh |= BH_RECEIVE;
2090}
2091
2092static void isr_tdma(struct slgt_info *info)
2093{
2094 unsigned int status = rd_reg32(info, TDCSR);
2095
2096 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2097
2098 /* TDCSR (tx DMA control/status)
2099 *
2100 * 31..06 reserved
2101 * 05 error
2102 * 04 eol (end of list)
2103 * 03 eob (end of buffer)
2104 * 02 IRQ enable
2105 * 01 reset
2106 * 00 enable
2107 */
2108 wr_reg32(info, TDCSR, status); /* clear pending */
2109
2110 if (status & (BIT5 + BIT4 + BIT3)) {
2111 // another transmit buffer has completed
2112 // run bottom half to get more send data from user
2113 info->pending_bh |= BH_TRANSMIT;
2114 }
2115}
2116
2117static void isr_txeom(struct slgt_info *info, unsigned short status)
2118{
2119 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2120
2121 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2122 tdma_reset(info);
2123 reset_tbufs(info);
2124 if (status & IRQ_TXUNDER) {
2125 unsigned short val = rd_reg16(info, TCR);
2126 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2127 wr_reg16(info, TCR, val); /* clear reset bit */
2128 }
2129
2130 if (info->tx_active) {
2131 if (info->params.mode != MGSL_MODE_ASYNC) {
2132 if (status & IRQ_TXUNDER)
2133 info->icount.txunder++;
2134 else if (status & IRQ_TXIDLE)
2135 info->icount.txok++;
2136 }
2137
2138 info->tx_active = 0;
2139 info->tx_count = 0;
2140
2141 del_timer(&info->tx_timer);
2142
2143 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2144 info->signals &= ~SerialSignal_RTS;
2145 info->drop_rts_on_tx_done = 0;
2146 set_signals(info);
2147 }
2148
2149#ifdef CONFIG_HDLC
2150 if (info->netcount)
2151 hdlcdev_tx_done(info);
2152 else
2153#endif
2154 {
2155 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2156 tx_stop(info);
2157 return;
2158 }
2159 info->pending_bh |= BH_TRANSMIT;
2160 }
2161 }
2162}
2163
2164/* interrupt service routine
2165 *
2166 * irq interrupt number
2167 * dev_id device ID supplied during interrupt registration
2168 * regs interrupted processor context
2169 */
2170static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2171{
2172 struct slgt_info *info;
2173 unsigned int gsr;
2174 unsigned int i;
2175
2176 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2177
2178 info = dev_id;
2179 if (!info)
2180 return IRQ_NONE;
2181
2182 spin_lock(&info->lock);
2183
2184 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2185 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2186 info->irq_occurred = 1;
2187 for(i=0; i < info->port_count ; i++) {
2188 if (info->port_array[i] == NULL)
2189 continue;
2190 if (gsr & (BIT8 << i))
2191 isr_serial(info->port_array[i]);
2192 if (gsr & (BIT16 << (i*2)))
2193 isr_rdma(info->port_array[i]);
2194 if (gsr & (BIT17 << (i*2)))
2195 isr_tdma(info->port_array[i]);
2196 }
2197 }
2198
2199 for(i=0; i < info->port_count ; i++) {
2200 struct slgt_info *port = info->port_array[i];
2201
2202 if (port && (port->count || port->netcount) &&
2203 port->pending_bh && !port->bh_running &&
2204 !port->bh_requested) {
2205 DBGISR(("%s bh queued\n", port->device_name));
2206 schedule_work(&port->task);
2207 port->bh_requested = 1;
2208 }
2209 }
2210
2211 spin_unlock(&info->lock);
2212
2213 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2214 return IRQ_HANDLED;
2215}
2216
2217static int startup(struct slgt_info *info)
2218{
2219 DBGINFO(("%s startup\n", info->device_name));
2220
2221 if (info->flags & ASYNC_INITIALIZED)
2222 return 0;
2223
2224 if (!info->tx_buf) {
2225 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2226 if (!info->tx_buf) {
2227 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2228 return -ENOMEM;
2229 }
2230 }
2231
2232 info->pending_bh = 0;
2233
2234 memset(&info->icount, 0, sizeof(info->icount));
2235
2236 /* program hardware for current parameters */
2237 change_params(info);
2238
2239 if (info->tty)
2240 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2241
2242 info->flags |= ASYNC_INITIALIZED;
2243
2244 return 0;
2245}
2246
2247/*
2248 * called by close() and hangup() to shutdown hardware
2249 */
2250static void shutdown(struct slgt_info *info)
2251{
2252 unsigned long flags;
2253
2254 if (!(info->flags & ASYNC_INITIALIZED))
2255 return;
2256
2257 DBGINFO(("%s shutdown\n", info->device_name));
2258
2259 /* clear status wait queue because status changes */
2260 /* can't happen after shutting down the hardware */
2261 wake_up_interruptible(&info->status_event_wait_q);
2262 wake_up_interruptible(&info->event_wait_q);
2263
2264 del_timer_sync(&info->tx_timer);
2265 del_timer_sync(&info->rx_timer);
2266
2267 kfree(info->tx_buf);
2268 info->tx_buf = NULL;
2269
2270 spin_lock_irqsave(&info->lock,flags);
2271
2272 tx_stop(info);
2273 rx_stop(info);
2274
2275 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2276
2277 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2278 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2279 set_signals(info);
2280 }
2281
2282 spin_unlock_irqrestore(&info->lock,flags);
2283
2284 if (info->tty)
2285 set_bit(TTY_IO_ERROR, &info->tty->flags);
2286
2287 info->flags &= ~ASYNC_INITIALIZED;
2288}
2289
2290static void program_hw(struct slgt_info *info)
2291{
2292 unsigned long flags;
2293
2294 spin_lock_irqsave(&info->lock,flags);
2295
2296 rx_stop(info);
2297 tx_stop(info);
2298
2299 if (info->params.mode == MGSL_MODE_HDLC ||
2300 info->params.mode == MGSL_MODE_RAW ||
2301 info->netcount)
2302 hdlc_mode(info);
2303 else
2304 async_mode(info);
2305
2306 set_signals(info);
2307
2308 info->dcd_chkcount = 0;
2309 info->cts_chkcount = 0;
2310 info->ri_chkcount = 0;
2311 info->dsr_chkcount = 0;
2312
2313 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2314 get_signals(info);
2315
2316 if (info->netcount ||
2317 (info->tty && info->tty->termios->c_cflag & CREAD))
2318 rx_start(info);
2319
2320 spin_unlock_irqrestore(&info->lock,flags);
2321}
2322
2323/*
2324 * reconfigure adapter based on new parameters
2325 */
2326static void change_params(struct slgt_info *info)
2327{
2328 unsigned cflag;
2329 int bits_per_char;
2330
2331 if (!info->tty || !info->tty->termios)
2332 return;
2333 DBGINFO(("%s change_params\n", info->device_name));
2334
2335 cflag = info->tty->termios->c_cflag;
2336
2337 /* if B0 rate (hangup) specified then negate DTR and RTS */
2338 /* otherwise assert DTR and RTS */
2339 if (cflag & CBAUD)
2340 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2341 else
2342 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2343
2344 /* byte size and parity */
2345
2346 switch (cflag & CSIZE) {
2347 case CS5: info->params.data_bits = 5; break;
2348 case CS6: info->params.data_bits = 6; break;
2349 case CS7: info->params.data_bits = 7; break;
2350 case CS8: info->params.data_bits = 8; break;
2351 default: info->params.data_bits = 7; break;
2352 }
2353
2354 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2355
2356 if (cflag & PARENB)
2357 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2358 else
2359 info->params.parity = ASYNC_PARITY_NONE;
2360
2361 /* calculate number of jiffies to transmit a full
2362 * FIFO (32 bytes) at specified data rate
2363 */
2364 bits_per_char = info->params.data_bits +
2365 info->params.stop_bits + 1;
2366
2367 info->params.data_rate = tty_get_baud_rate(info->tty);
2368
2369 if (info->params.data_rate) {
2370 info->timeout = (32*HZ*bits_per_char) /
2371 info->params.data_rate;
2372 }
2373 info->timeout += HZ/50; /* Add .02 seconds of slop */
2374
2375 if (cflag & CRTSCTS)
2376 info->flags |= ASYNC_CTS_FLOW;
2377 else
2378 info->flags &= ~ASYNC_CTS_FLOW;
2379
2380 if (cflag & CLOCAL)
2381 info->flags &= ~ASYNC_CHECK_CD;
2382 else
2383 info->flags |= ASYNC_CHECK_CD;
2384
2385 /* process tty input control flags */
2386
2387 info->read_status_mask = IRQ_RXOVER;
2388 if (I_INPCK(info->tty))
2389 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2390 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2391 info->read_status_mask |= MASK_BREAK;
2392 if (I_IGNPAR(info->tty))
2393 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2394 if (I_IGNBRK(info->tty)) {
2395 info->ignore_status_mask |= MASK_BREAK;
2396 /* If ignoring parity and break indicators, ignore
2397 * overruns too. (For real raw support).
2398 */
2399 if (I_IGNPAR(info->tty))
2400 info->ignore_status_mask |= MASK_OVERRUN;
2401 }
2402
2403 program_hw(info);
2404}
2405
2406static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2407{
2408 DBGINFO(("%s get_stats\n", info->device_name));
2409 if (!user_icount) {
2410 memset(&info->icount, 0, sizeof(info->icount));
2411 } else {
2412 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2413 return -EFAULT;
2414 }
2415 return 0;
2416}
2417
2418static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2419{
2420 DBGINFO(("%s get_params\n", info->device_name));
2421 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2422 return -EFAULT;
2423 return 0;
2424}
2425
2426static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2427{
2428 unsigned long flags;
2429 MGSL_PARAMS tmp_params;
2430
2431 DBGINFO(("%s set_params\n", info->device_name));
2432 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2433 return -EFAULT;
2434
2435 spin_lock_irqsave(&info->lock, flags);
2436 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2437 spin_unlock_irqrestore(&info->lock, flags);
2438
2439 change_params(info);
2440
2441 return 0;
2442}
2443
2444static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2445{
2446 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2447 if (put_user(info->idle_mode, idle_mode))
2448 return -EFAULT;
2449 return 0;
2450}
2451
2452static int set_txidle(struct slgt_info *info, int idle_mode)
2453{
2454 unsigned long flags;
2455 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2456 spin_lock_irqsave(&info->lock,flags);
2457 info->idle_mode = idle_mode;
2458 tx_set_idle(info);
2459 spin_unlock_irqrestore(&info->lock,flags);
2460 return 0;
2461}
2462
2463static int tx_enable(struct slgt_info *info, int enable)
2464{
2465 unsigned long flags;
2466 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2467 spin_lock_irqsave(&info->lock,flags);
2468 if (enable) {
2469 if (!info->tx_enabled)
2470 tx_start(info);
2471 } else {
2472 if (info->tx_enabled)
2473 tx_stop(info);
2474 }
2475 spin_unlock_irqrestore(&info->lock,flags);
2476 return 0;
2477}
2478
2479/*
2480 * abort transmit HDLC frame
2481 */
2482static int tx_abort(struct slgt_info *info)
2483{
2484 unsigned long flags;
2485 DBGINFO(("%s tx_abort\n", info->device_name));
2486 spin_lock_irqsave(&info->lock,flags);
2487 tdma_reset(info);
2488 spin_unlock_irqrestore(&info->lock,flags);
2489 return 0;
2490}
2491
2492static int rx_enable(struct slgt_info *info, int enable)
2493{
2494 unsigned long flags;
2495 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2496 spin_lock_irqsave(&info->lock,flags);
2497 if (enable) {
2498 if (!info->rx_enabled)
2499 rx_start(info);
2500 } else {
2501 if (info->rx_enabled)
2502 rx_stop(info);
2503 }
2504 spin_unlock_irqrestore(&info->lock,flags);
2505 return 0;
2506}
2507
2508/*
2509 * wait for specified event to occur
2510 */
2511static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2512{
2513 unsigned long flags;
2514 int s;
2515 int rc=0;
2516 struct mgsl_icount cprev, cnow;
2517 int events;
2518 int mask;
2519 struct _input_signal_events oldsigs, newsigs;
2520 DECLARE_WAITQUEUE(wait, current);
2521
2522 if (get_user(mask, mask_ptr))
2523 return -EFAULT;
2524
2525 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2526
2527 spin_lock_irqsave(&info->lock,flags);
2528
2529 /* return immediately if state matches requested events */
2530 get_signals(info);
2531 s = info->signals;
2532
2533 events = mask &
2534 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2535 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2536 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2537 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2538 if (events) {
2539 spin_unlock_irqrestore(&info->lock,flags);
2540 goto exit;
2541 }
2542
2543 /* save current irq counts */
2544 cprev = info->icount;
2545 oldsigs = info->input_signal_events;
2546
2547 /* enable hunt and idle irqs if needed */
2548 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2549 unsigned short val = rd_reg16(info, SCR);
2550 if (!(val & IRQ_RXIDLE))
2551 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2552 }
2553
2554 set_current_state(TASK_INTERRUPTIBLE);
2555 add_wait_queue(&info->event_wait_q, &wait);
2556
2557 spin_unlock_irqrestore(&info->lock,flags);
2558
2559 for(;;) {
2560 schedule();
2561 if (signal_pending(current)) {
2562 rc = -ERESTARTSYS;
2563 break;
2564 }
2565
2566 /* get current irq counts */
2567 spin_lock_irqsave(&info->lock,flags);
2568 cnow = info->icount;
2569 newsigs = info->input_signal_events;
2570 set_current_state(TASK_INTERRUPTIBLE);
2571 spin_unlock_irqrestore(&info->lock,flags);
2572
2573 /* if no change, wait aborted for some reason */
2574 if (newsigs.dsr_up == oldsigs.dsr_up &&
2575 newsigs.dsr_down == oldsigs.dsr_down &&
2576 newsigs.dcd_up == oldsigs.dcd_up &&
2577 newsigs.dcd_down == oldsigs.dcd_down &&
2578 newsigs.cts_up == oldsigs.cts_up &&
2579 newsigs.cts_down == oldsigs.cts_down &&
2580 newsigs.ri_up == oldsigs.ri_up &&
2581 newsigs.ri_down == oldsigs.ri_down &&
2582 cnow.exithunt == cprev.exithunt &&
2583 cnow.rxidle == cprev.rxidle) {
2584 rc = -EIO;
2585 break;
2586 }
2587
2588 events = mask &
2589 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2590 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2591 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2592 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2593 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2594 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2595 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2596 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2597 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2598 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2599 if (events)
2600 break;
2601
2602 cprev = cnow;
2603 oldsigs = newsigs;
2604 }
2605
2606 remove_wait_queue(&info->event_wait_q, &wait);
2607 set_current_state(TASK_RUNNING);
2608
2609
2610 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2611 spin_lock_irqsave(&info->lock,flags);
2612 if (!waitqueue_active(&info->event_wait_q)) {
2613 /* disable enable exit hunt mode/idle rcvd IRQs */
2614 wr_reg16(info, SCR,
2615 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2616 }
2617 spin_unlock_irqrestore(&info->lock,flags);
2618 }
2619exit:
2620 if (rc == 0)
2621 rc = put_user(events, mask_ptr);
2622 return rc;
2623}
2624
2625static int get_interface(struct slgt_info *info, int __user *if_mode)
2626{
2627 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2628 if (put_user(info->if_mode, if_mode))
2629 return -EFAULT;
2630 return 0;
2631}
2632
2633static int set_interface(struct slgt_info *info, int if_mode)
2634{
2635 unsigned long flags;
2636 unsigned char val;
2637
2638 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2639 spin_lock_irqsave(&info->lock,flags);
2640 info->if_mode = if_mode;
2641
2642 msc_set_vcr(info);
2643
2644 /* TCR (tx control) 07 1=RTS driver control */
2645 val = rd_reg16(info, TCR);
2646 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2647 val |= BIT7;
2648 else
2649 val &= ~BIT7;
2650 wr_reg16(info, TCR, val);
2651
2652 spin_unlock_irqrestore(&info->lock,flags);
2653 return 0;
2654}
2655
2656static int modem_input_wait(struct slgt_info *info,int arg)
2657{
2658 unsigned long flags;
2659 int rc;
2660 struct mgsl_icount cprev, cnow;
2661 DECLARE_WAITQUEUE(wait, current);
2662
2663 /* save current irq counts */
2664 spin_lock_irqsave(&info->lock,flags);
2665 cprev = info->icount;
2666 add_wait_queue(&info->status_event_wait_q, &wait);
2667 set_current_state(TASK_INTERRUPTIBLE);
2668 spin_unlock_irqrestore(&info->lock,flags);
2669
2670 for(;;) {
2671 schedule();
2672 if (signal_pending(current)) {
2673 rc = -ERESTARTSYS;
2674 break;
2675 }
2676
2677 /* get new irq counts */
2678 spin_lock_irqsave(&info->lock,flags);
2679 cnow = info->icount;
2680 set_current_state(TASK_INTERRUPTIBLE);
2681 spin_unlock_irqrestore(&info->lock,flags);
2682
2683 /* if no change, wait aborted for some reason */
2684 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2685 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2686 rc = -EIO;
2687 break;
2688 }
2689
2690 /* check for change in caller specified modem input */
2691 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2692 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2693 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2694 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2695 rc = 0;
2696 break;
2697 }
2698
2699 cprev = cnow;
2700 }
2701 remove_wait_queue(&info->status_event_wait_q, &wait);
2702 set_current_state(TASK_RUNNING);
2703 return rc;
2704}
2705
2706/*
2707 * return state of serial control and status signals
2708 */
2709static int tiocmget(struct tty_struct *tty, struct file *file)
2710{
2711 struct slgt_info *info = tty->driver_data;
2712 unsigned int result;
2713 unsigned long flags;
2714
2715 spin_lock_irqsave(&info->lock,flags);
2716 get_signals(info);
2717 spin_unlock_irqrestore(&info->lock,flags);
2718
2719 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2720 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2721 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2722 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2723 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2724 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2725
2726 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2727 return result;
2728}
2729
2730/*
2731 * set modem control signals (DTR/RTS)
2732 *
2733 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2734 * TIOCMSET = set/clear signal values
2735 * value bit mask for command
2736 */
2737static int tiocmset(struct tty_struct *tty, struct file *file,
2738 unsigned int set, unsigned int clear)
2739{
2740 struct slgt_info *info = tty->driver_data;
2741 unsigned long flags;
2742
2743 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2744
2745 if (set & TIOCM_RTS)
2746 info->signals |= SerialSignal_RTS;
2747 if (set & TIOCM_DTR)
2748 info->signals |= SerialSignal_DTR;
2749 if (clear & TIOCM_RTS)
2750 info->signals &= ~SerialSignal_RTS;
2751 if (clear & TIOCM_DTR)
2752 info->signals &= ~SerialSignal_DTR;
2753
2754 spin_lock_irqsave(&info->lock,flags);
2755 set_signals(info);
2756 spin_unlock_irqrestore(&info->lock,flags);
2757 return 0;
2758}
2759
2760/*
2761 * block current process until the device is ready to open
2762 */
2763static int block_til_ready(struct tty_struct *tty, struct file *filp,
2764 struct slgt_info *info)
2765{
2766 DECLARE_WAITQUEUE(wait, current);
2767 int retval;
2768 int do_clocal = 0, extra_count = 0;
2769 unsigned long flags;
2770
2771 DBGINFO(("%s block_til_ready\n", tty->driver->name));
2772
2773 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
2774 /* nonblock mode is set or port is not enabled */
2775 info->flags |= ASYNC_NORMAL_ACTIVE;
2776 return 0;
2777 }
2778
2779 if (tty->termios->c_cflag & CLOCAL)
2780 do_clocal = 1;
2781
2782 /* Wait for carrier detect and the line to become
2783 * free (i.e., not in use by the callout). While we are in
2784 * this loop, info->count is dropped by one, so that
2785 * close() knows when to free things. We restore it upon
2786 * exit, either normal or abnormal.
2787 */
2788
2789 retval = 0;
2790 add_wait_queue(&info->open_wait, &wait);
2791
2792 spin_lock_irqsave(&info->lock, flags);
2793 if (!tty_hung_up_p(filp)) {
2794 extra_count = 1;
2795 info->count--;
2796 }
2797 spin_unlock_irqrestore(&info->lock, flags);
2798 info->blocked_open++;
2799
2800 while (1) {
2801 if ((tty->termios->c_cflag & CBAUD)) {
2802 spin_lock_irqsave(&info->lock,flags);
2803 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2804 set_signals(info);
2805 spin_unlock_irqrestore(&info->lock,flags);
2806 }
2807
2808 set_current_state(TASK_INTERRUPTIBLE);
2809
2810 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
2811 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
2812 -EAGAIN : -ERESTARTSYS;
2813 break;
2814 }
2815
2816 spin_lock_irqsave(&info->lock,flags);
2817 get_signals(info);
2818 spin_unlock_irqrestore(&info->lock,flags);
2819
2820 if (!(info->flags & ASYNC_CLOSING) &&
2821 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
2822 break;
2823 }
2824
2825 if (signal_pending(current)) {
2826 retval = -ERESTARTSYS;
2827 break;
2828 }
2829
2830 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
2831 schedule();
2832 }
2833
2834 set_current_state(TASK_RUNNING);
2835 remove_wait_queue(&info->open_wait, &wait);
2836
2837 if (extra_count)
2838 info->count++;
2839 info->blocked_open--;
2840
2841 if (!retval)
2842 info->flags |= ASYNC_NORMAL_ACTIVE;
2843
2844 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
2845 return retval;
2846}
2847
2848static int alloc_tmp_rbuf(struct slgt_info *info)
2849{
2850 info->tmp_rbuf = kmalloc(info->max_frame_size, GFP_KERNEL);
2851 if (info->tmp_rbuf == NULL)
2852 return -ENOMEM;
2853 return 0;
2854}
2855
2856static void free_tmp_rbuf(struct slgt_info *info)
2857{
2858 kfree(info->tmp_rbuf);
2859 info->tmp_rbuf = NULL;
2860}
2861
2862/*
2863 * allocate DMA descriptor lists.
2864 */
2865static int alloc_desc(struct slgt_info *info)
2866{
2867 unsigned int i;
2868 unsigned int pbufs;
2869
2870 /* allocate memory to hold descriptor lists */
2871 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
2872 if (info->bufs == NULL)
2873 return -ENOMEM;
2874
2875 memset(info->bufs, 0, DESC_LIST_SIZE);
2876
2877 info->rbufs = (struct slgt_desc*)info->bufs;
2878 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
2879
2880 pbufs = (unsigned int)info->bufs_dma_addr;
2881
2882 /*
2883 * Build circular lists of descriptors
2884 */
2885
2886 for (i=0; i < info->rbuf_count; i++) {
2887 /* physical address of this descriptor */
2888 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
2889
2890 /* physical address of next descriptor */
2891 if (i == info->rbuf_count - 1)
2892 info->rbufs[i].next = cpu_to_le32(pbufs);
2893 else
2894 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
2895 set_desc_count(info->rbufs[i], DMABUFSIZE);
2896 }
2897
2898 for (i=0; i < info->tbuf_count; i++) {
2899 /* physical address of this descriptor */
2900 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
2901
2902 /* physical address of next descriptor */
2903 if (i == info->tbuf_count - 1)
2904 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
2905 else
2906 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
2907 }
2908
2909 return 0;
2910}
2911
2912static void free_desc(struct slgt_info *info)
2913{
2914 if (info->bufs != NULL) {
2915 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
2916 info->bufs = NULL;
2917 info->rbufs = NULL;
2918 info->tbufs = NULL;
2919 }
2920}
2921
2922static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
2923{
2924 int i;
2925 for (i=0; i < count; i++) {
2926 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
2927 return -ENOMEM;
2928 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
2929 }
2930 return 0;
2931}
2932
2933static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
2934{
2935 int i;
2936 for (i=0; i < count; i++) {
2937 if (bufs[i].buf == NULL)
2938 continue;
2939 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
2940 bufs[i].buf = NULL;
2941 }
2942}
2943
2944static int alloc_dma_bufs(struct slgt_info *info)
2945{
2946 info->rbuf_count = 32;
2947 info->tbuf_count = 32;
2948
2949 if (alloc_desc(info) < 0 ||
2950 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
2951 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
2952 alloc_tmp_rbuf(info) < 0) {
2953 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
2954 return -ENOMEM;
2955 }
2956 reset_rbufs(info);
2957 return 0;
2958}
2959
2960static void free_dma_bufs(struct slgt_info *info)
2961{
2962 if (info->bufs) {
2963 free_bufs(info, info->rbufs, info->rbuf_count);
2964 free_bufs(info, info->tbufs, info->tbuf_count);
2965 free_desc(info);
2966 }
2967 free_tmp_rbuf(info);
2968}
2969
2970static int claim_resources(struct slgt_info *info)
2971{
2972 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
2973 DBGERR(("%s reg addr conflict, addr=%08X\n",
2974 info->device_name, info->phys_reg_addr));
2975 info->init_error = DiagStatus_AddressConflict;
2976 goto errout;
2977 }
2978 else
2979 info->reg_addr_requested = 1;
2980
2981 info->reg_addr = ioremap(info->phys_reg_addr, PAGE_SIZE);
2982 if (!info->reg_addr) {
2983 DBGERR(("%s cant map device registers, addr=%08X\n",
2984 info->device_name, info->phys_reg_addr));
2985 info->init_error = DiagStatus_CantAssignPciResources;
2986 goto errout;
2987 }
2988 info->reg_addr += info->reg_offset;
2989 return 0;
2990
2991errout:
2992 release_resources(info);
2993 return -ENODEV;
2994}
2995
2996static void release_resources(struct slgt_info *info)
2997{
2998 if (info->irq_requested) {
2999 free_irq(info->irq_level, info);
3000 info->irq_requested = 0;
3001 }
3002
3003 if (info->reg_addr_requested) {
3004 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3005 info->reg_addr_requested = 0;
3006 }
3007
3008 if (info->reg_addr) {
3009 iounmap(info->reg_addr - info->reg_offset);
3010 info->reg_addr = NULL;
3011 }
3012}
3013
3014/* Add the specified device instance data structure to the
3015 * global linked list of devices and increment the device count.
3016 */
3017static void add_device(struct slgt_info *info)
3018{
3019 char *devstr;
3020
3021 info->next_device = NULL;
3022 info->line = slgt_device_count;
3023 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3024
3025 if (info->line < MAX_DEVICES) {
3026 if (maxframe[info->line])
3027 info->max_frame_size = maxframe[info->line];
3028 info->dosyncppp = dosyncppp[info->line];
3029 }
3030
3031 slgt_device_count++;
3032
3033 if (!slgt_device_list)
3034 slgt_device_list = info;
3035 else {
3036 struct slgt_info *current_dev = slgt_device_list;
3037 while(current_dev->next_device)
3038 current_dev = current_dev->next_device;
3039 current_dev->next_device = info;
3040 }
3041
3042 if (info->max_frame_size < 4096)
3043 info->max_frame_size = 4096;
3044 else if (info->max_frame_size > 65535)
3045 info->max_frame_size = 65535;
3046
3047 switch(info->pdev->device) {
3048 case SYNCLINK_GT_DEVICE_ID:
3049 devstr = "GT";
3050 break;
3051 case SYNCLINK_GT4_DEVICE_ID:
3052 devstr = "GT4";
3053 break;
3054 case SYNCLINK_AC_DEVICE_ID:
3055 devstr = "AC";
3056 info->params.mode = MGSL_MODE_ASYNC;
3057 break;
3058 default:
3059 devstr = "(unknown model)";
3060 }
3061 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3062 devstr, info->device_name, info->phys_reg_addr,
3063 info->irq_level, info->max_frame_size);
3064
3065#ifdef CONFIG_HDLC
3066 hdlcdev_init(info);
3067#endif
3068}
3069
3070/*
3071 * allocate device instance structure, return NULL on failure
3072 */
3073static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3074{
3075 struct slgt_info *info;
3076
3077 info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3078
3079 if (!info) {
3080 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3081 driver_name, adapter_num, port_num));
3082 } else {
3083 memset(info, 0, sizeof(struct slgt_info));
3084 info->magic = MGSL_MAGIC;
3085 INIT_WORK(&info->task, bh_handler, info);
3086 info->max_frame_size = 4096;
3087 info->raw_rx_size = DMABUFSIZE;
3088 info->close_delay = 5*HZ/10;
3089 info->closing_wait = 30*HZ;
3090 init_waitqueue_head(&info->open_wait);
3091 init_waitqueue_head(&info->close_wait);
3092 init_waitqueue_head(&info->status_event_wait_q);
3093 init_waitqueue_head(&info->event_wait_q);
3094 spin_lock_init(&info->netlock);
3095 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3096 info->idle_mode = HDLC_TXIDLE_FLAGS;
3097 info->adapter_num = adapter_num;
3098 info->port_num = port_num;
3099
3100 init_timer(&info->tx_timer);
3101 info->tx_timer.data = (unsigned long)info;
3102 info->tx_timer.function = tx_timeout;
3103
3104 init_timer(&info->rx_timer);
3105 info->rx_timer.data = (unsigned long)info;
3106 info->rx_timer.function = rx_timeout;
3107
3108 /* Copy configuration info to device instance data */
3109 info->pdev = pdev;
3110 info->irq_level = pdev->irq;
3111 info->phys_reg_addr = pci_resource_start(pdev,0);
3112
3113 /* veremap works on page boundaries
3114 * map full page starting at the page boundary
3115 */
3116 info->reg_offset = info->phys_reg_addr & (PAGE_SIZE-1);
3117 info->phys_reg_addr &= ~(PAGE_SIZE-1);
3118
3119 info->bus_type = MGSL_BUS_TYPE_PCI;
3120 info->irq_flags = SA_SHIRQ;
3121
3122 info->init_error = -1; /* assume error, set to 0 on successful init */
3123 }
3124
3125 return info;
3126}
3127
3128static void device_init(int adapter_num, struct pci_dev *pdev)
3129{
3130 struct slgt_info *port_array[SLGT_MAX_PORTS];
3131 int i;
3132 int port_count = 1;
3133
3134 if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3135 port_count = 4;
3136
3137 /* allocate device instances for all ports */
3138 for (i=0; i < port_count; ++i) {
3139 port_array[i] = alloc_dev(adapter_num, i, pdev);
3140 if (port_array[i] == NULL) {
3141 for (--i; i >= 0; --i)
3142 kfree(port_array[i]);
3143 return;
3144 }
3145 }
3146
3147 /* give copy of port_array to all ports and add to device list */
3148 for (i=0; i < port_count; ++i) {
3149 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3150 add_device(port_array[i]);
3151 port_array[i]->port_count = port_count;
3152 spin_lock_init(&port_array[i]->lock);
3153 }
3154
3155 /* Allocate and claim adapter resources */
3156 if (!claim_resources(port_array[0])) {
3157
3158 alloc_dma_bufs(port_array[0]);
3159
3160 /* copy resource information from first port to others */
3161 for (i = 1; i < port_count; ++i) {
3162 port_array[i]->lock = port_array[0]->lock;
3163 port_array[i]->irq_level = port_array[0]->irq_level;
3164 port_array[i]->reg_addr = port_array[0]->reg_addr;
3165 alloc_dma_bufs(port_array[i]);
3166 }
3167
3168 if (request_irq(port_array[0]->irq_level,
3169 slgt_interrupt,
3170 port_array[0]->irq_flags,
3171 port_array[0]->device_name,
3172 port_array[0]) < 0) {
3173 DBGERR(("%s request_irq failed IRQ=%d\n",
3174 port_array[0]->device_name,
3175 port_array[0]->irq_level));
3176 } else {
3177 port_array[0]->irq_requested = 1;
3178 adapter_test(port_array[0]);
3179 for (i=1 ; i < port_count ; i++)
3180 port_array[i]->init_error = port_array[0]->init_error;
3181 }
3182 }
3183}
3184
3185static int __devinit init_one(struct pci_dev *dev,
3186 const struct pci_device_id *ent)
3187{
3188 if (pci_enable_device(dev)) {
3189 printk("error enabling pci device %p\n", dev);
3190 return -EIO;
3191 }
3192 pci_set_master(dev);
3193 device_init(slgt_device_count, dev);
3194 return 0;
3195}
3196
3197static void __devexit remove_one(struct pci_dev *dev)
3198{
3199}
3200
3201static struct tty_operations ops = {
3202 .open = open,
3203 .close = close,
3204 .write = write,
3205 .put_char = put_char,
3206 .flush_chars = flush_chars,
3207 .write_room = write_room,
3208 .chars_in_buffer = chars_in_buffer,
3209 .flush_buffer = flush_buffer,
3210 .ioctl = ioctl,
3211 .throttle = throttle,
3212 .unthrottle = unthrottle,
3213 .send_xchar = send_xchar,
3214 .break_ctl = set_break,
3215 .wait_until_sent = wait_until_sent,
3216 .read_proc = read_proc,
3217 .set_termios = set_termios,
3218 .stop = tx_hold,
3219 .start = tx_release,
3220 .hangup = hangup,
3221 .tiocmget = tiocmget,
3222 .tiocmset = tiocmset,
3223};
3224
3225static void slgt_cleanup(void)
3226{
3227 int rc;
3228 struct slgt_info *info;
3229 struct slgt_info *tmp;
3230
3231 printk("unload %s %s\n", driver_name, driver_version);
3232
3233 if (serial_driver) {
3234 if ((rc = tty_unregister_driver(serial_driver)))
3235 DBGERR(("tty_unregister_driver error=%d\n", rc));
3236 put_tty_driver(serial_driver);
3237 }
3238
3239 /* reset devices */
3240 info = slgt_device_list;
3241 while(info) {
3242 reset_port(info);
3243 info = info->next_device;
3244 }
3245
3246 /* release devices */
3247 info = slgt_device_list;
3248 while(info) {
3249#ifdef CONFIG_HDLC
3250 hdlcdev_exit(info);
3251#endif
3252 free_dma_bufs(info);
3253 free_tmp_rbuf(info);
3254 if (info->port_num == 0)
3255 release_resources(info);
3256 tmp = info;
3257 info = info->next_device;
3258 kfree(tmp);
3259 }
3260
3261 if (pci_registered)
3262 pci_unregister_driver(&pci_driver);
3263}
3264
3265/*
3266 * Driver initialization entry point.
3267 */
3268static int __init slgt_init(void)
3269{
3270 int rc;
3271
3272 printk("%s %s\n", driver_name, driver_version);
3273
3274 slgt_device_count = 0;
3275 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3276 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3277 return rc;
3278 }
3279 pci_registered = 1;
3280
3281 if (!slgt_device_list) {
3282 printk("%s no devices found\n",driver_name);
3283 return -ENODEV;
3284 }
3285
3286 serial_driver = alloc_tty_driver(MAX_DEVICES);
3287 if (!serial_driver) {
3288 rc = -ENOMEM;
3289 goto error;
3290 }
3291
3292 /* Initialize the tty_driver structure */
3293
3294 serial_driver->owner = THIS_MODULE;
3295 serial_driver->driver_name = tty_driver_name;
3296 serial_driver->name = tty_dev_prefix;
3297 serial_driver->major = ttymajor;
3298 serial_driver->minor_start = 64;
3299 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3300 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3301 serial_driver->init_termios = tty_std_termios;
3302 serial_driver->init_termios.c_cflag =
3303 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3304 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3305 tty_set_operations(serial_driver, &ops);
3306 if ((rc = tty_register_driver(serial_driver)) < 0) {
3307 DBGERR(("%s can't register serial driver\n", driver_name));
3308 put_tty_driver(serial_driver);
3309 serial_driver = NULL;
3310 goto error;
3311 }
3312
3313 printk("%s %s, tty major#%d\n",
3314 driver_name, driver_version,
3315 serial_driver->major);
3316
3317 return 0;
3318
3319error:
3320 slgt_cleanup();
3321 return rc;
3322}
3323
3324static void __exit slgt_exit(void)
3325{
3326 slgt_cleanup();
3327}
3328
3329module_init(slgt_init);
3330module_exit(slgt_exit);
3331
3332/*
3333 * register access routines
3334 */
3335
3336#define CALC_REGADDR() \
3337 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3338 if (addr >= 0x80) \
3339 reg_addr += (info->port_num) * 32;
3340
3341static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3342{
3343 CALC_REGADDR();
3344 return readb((void __iomem *)reg_addr);
3345}
3346
3347static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3348{
3349 CALC_REGADDR();
3350 writeb(value, (void __iomem *)reg_addr);
3351}
3352
3353static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3354{
3355 CALC_REGADDR();
3356 return readw((void __iomem *)reg_addr);
3357}
3358
3359static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3360{
3361 CALC_REGADDR();
3362 writew(value, (void __iomem *)reg_addr);
3363}
3364
3365static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3366{
3367 CALC_REGADDR();
3368 return readl((void __iomem *)reg_addr);
3369}
3370
3371static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3372{
3373 CALC_REGADDR();
3374 writel(value, (void __iomem *)reg_addr);
3375}
3376
3377static void rdma_reset(struct slgt_info *info)
3378{
3379 unsigned int i;
3380
3381 /* set reset bit */
3382 wr_reg32(info, RDCSR, BIT1);
3383
3384 /* wait for enable bit cleared */
3385 for(i=0 ; i < 1000 ; i++)
3386 if (!(rd_reg32(info, RDCSR) & BIT0))
3387 break;
3388}
3389
3390static void tdma_reset(struct slgt_info *info)
3391{
3392 unsigned int i;
3393
3394 /* set reset bit */
3395 wr_reg32(info, TDCSR, BIT1);
3396
3397 /* wait for enable bit cleared */
3398 for(i=0 ; i < 1000 ; i++)
3399 if (!(rd_reg32(info, TDCSR) & BIT0))
3400 break;
3401}
3402
3403/*
3404 * enable internal loopback
3405 * TxCLK and RxCLK are generated from BRG
3406 * and TxD is looped back to RxD internally.
3407 */
3408static void enable_loopback(struct slgt_info *info)
3409{
3410 /* SCR (serial control) BIT2=looopback enable */
3411 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3412
3413 if (info->params.mode != MGSL_MODE_ASYNC) {
3414 /* CCR (clock control)
3415 * 07..05 tx clock source (010 = BRG)
3416 * 04..02 rx clock source (010 = BRG)
3417 * 01 auxclk enable (0 = disable)
3418 * 00 BRG enable (1 = enable)
3419 *
3420 * 0100 1001
3421 */
3422 wr_reg8(info, CCR, 0x49);
3423
3424 /* set speed if available, otherwise use default */
3425 if (info->params.clock_speed)
3426 set_rate(info, info->params.clock_speed);
3427 else
3428 set_rate(info, 3686400);
3429 }
3430}
3431
3432/*
3433 * set baud rate generator to specified rate
3434 */
3435static void set_rate(struct slgt_info *info, u32 rate)
3436{
3437 unsigned int div;
3438 static unsigned int osc = 14745600;
3439
3440 /* div = osc/rate - 1
3441 *
3442 * Round div up if osc/rate is not integer to
3443 * force to next slowest rate.
3444 */
3445
3446 if (rate) {
3447 div = osc/rate;
3448 if (!(osc % rate) && div)
3449 div--;
3450 wr_reg16(info, BDR, (unsigned short)div);
3451 }
3452}
3453
3454static void rx_stop(struct slgt_info *info)
3455{
3456 unsigned short val;
3457
3458 /* disable and reset receiver */
3459 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3460 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3461 wr_reg16(info, RCR, val); /* clear reset bit */
3462
3463 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3464
3465 /* clear pending rx interrupts */
3466 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3467
3468 rdma_reset(info);
3469
3470 info->rx_enabled = 0;
3471 info->rx_restart = 0;
3472}
3473
3474static void rx_start(struct slgt_info *info)
3475{
3476 unsigned short val;
3477
3478 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3479
3480 /* clear pending rx overrun IRQ */
3481 wr_reg16(info, SSR, IRQ_RXOVER);
3482
3483 /* reset and disable receiver */
3484 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3485 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3486 wr_reg16(info, RCR, val); /* clear reset bit */
3487
3488 rdma_reset(info);
3489 reset_rbufs(info);
3490
3491 /* set 1st descriptor address */
3492 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3493
3494 if (info->params.mode != MGSL_MODE_ASYNC) {
3495 /* enable rx DMA and DMA interrupt */
3496 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3497 } else {
3498 /* enable saving of rx status, rx DMA and DMA interrupt */
3499 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3500 }
3501
3502 slgt_irq_on(info, IRQ_RXOVER);
3503
3504 /* enable receiver */
3505 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3506
3507 info->rx_restart = 0;
3508 info->rx_enabled = 1;
3509}
3510
3511static void tx_start(struct slgt_info *info)
3512{
3513 if (!info->tx_enabled) {
3514 wr_reg16(info, TCR,
3515 (unsigned short)(rd_reg16(info, TCR) | BIT1));
3516 info->tx_enabled = TRUE;
3517 }
3518
3519 if (info->tx_count) {
3520 info->drop_rts_on_tx_done = 0;
3521
3522 if (info->params.mode != MGSL_MODE_ASYNC) {
3523 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3524 get_signals(info);
3525 if (!(info->signals & SerialSignal_RTS)) {
3526 info->signals |= SerialSignal_RTS;
3527 set_signals(info);
3528 info->drop_rts_on_tx_done = 1;
3529 }
3530 }
3531
3532 slgt_irq_off(info, IRQ_TXDATA);
3533 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3534 /* clear tx idle and underrun status bits */
3535 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3536
3537 if (!(rd_reg32(info, TDCSR) & BIT0)) {
3538 /* tx DMA stopped, restart tx DMA */
3539 tdma_reset(info);
3540 /* set 1st descriptor address */
3541 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3542 if (info->params.mode == MGSL_MODE_RAW)
3543 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3544 else
3545 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3546 }
3547
3548 if (info->params.mode != MGSL_MODE_RAW) {
3549 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3550 add_timer(&info->tx_timer);
3551 }
3552 } else {
3553 tdma_reset(info);
3554 /* set 1st descriptor address */
3555 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3556
3557 slgt_irq_off(info, IRQ_TXDATA);
3558 slgt_irq_on(info, IRQ_TXIDLE);
3559 /* clear tx idle status bit */
3560 wr_reg16(info, SSR, IRQ_TXIDLE);
3561
3562 /* enable tx DMA */
3563 wr_reg32(info, TDCSR, BIT0);
3564 }
3565
3566 info->tx_active = 1;
3567 }
3568}
3569
3570static void tx_stop(struct slgt_info *info)
3571{
3572 unsigned short val;
3573
3574 del_timer(&info->tx_timer);
3575
3576 tdma_reset(info);
3577
3578 /* reset and disable transmitter */
3579 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3580 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3581 wr_reg16(info, TCR, val); /* clear reset */
3582
3583 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3584
3585 /* clear tx idle and underrun status bit */
3586 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3587
3588 reset_tbufs(info);
3589
3590 info->tx_enabled = 0;
3591 info->tx_active = 0;
3592}
3593
3594static void reset_port(struct slgt_info *info)
3595{
3596 if (!info->reg_addr)
3597 return;
3598
3599 tx_stop(info);
3600 rx_stop(info);
3601
3602 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3603 set_signals(info);
3604
3605 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3606}
3607
3608static void reset_adapter(struct slgt_info *info)
3609{
3610 int i;
3611 for (i=0; i < info->port_count; ++i) {
3612 if (info->port_array[i])
3613 reset_port(info->port_array[i]);
3614 }
3615}
3616
3617static void async_mode(struct slgt_info *info)
3618{
3619 unsigned short val;
3620
3621 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3622 tx_stop(info);
3623 rx_stop(info);
3624
3625 /* TCR (tx control)
3626 *
3627 * 15..13 mode, 010=async
3628 * 12..10 encoding, 000=NRZ
3629 * 09 parity enable
3630 * 08 1=odd parity, 0=even parity
3631 * 07 1=RTS driver control
3632 * 06 1=break enable
3633 * 05..04 character length
3634 * 00=5 bits
3635 * 01=6 bits
3636 * 10=7 bits
3637 * 11=8 bits
3638 * 03 0=1 stop bit, 1=2 stop bits
3639 * 02 reset
3640 * 01 enable
3641 * 00 auto-CTS enable
3642 */
3643 val = 0x4000;
3644
3645 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3646 val |= BIT7;
3647
3648 if (info->params.parity != ASYNC_PARITY_NONE) {
3649 val |= BIT9;
3650 if (info->params.parity == ASYNC_PARITY_ODD)
3651 val |= BIT8;
3652 }
3653
3654 switch (info->params.data_bits)
3655 {
3656 case 6: val |= BIT4; break;
3657 case 7: val |= BIT5; break;
3658 case 8: val |= BIT5 + BIT4; break;
3659 }
3660
3661 if (info->params.stop_bits != 1)
3662 val |= BIT3;
3663
3664 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3665 val |= BIT0;
3666
3667 wr_reg16(info, TCR, val);
3668
3669 /* RCR (rx control)
3670 *
3671 * 15..13 mode, 010=async
3672 * 12..10 encoding, 000=NRZ
3673 * 09 parity enable
3674 * 08 1=odd parity, 0=even parity
3675 * 07..06 reserved, must be 0
3676 * 05..04 character length
3677 * 00=5 bits
3678 * 01=6 bits
3679 * 10=7 bits
3680 * 11=8 bits
3681 * 03 reserved, must be zero
3682 * 02 reset
3683 * 01 enable
3684 * 00 auto-DCD enable
3685 */
3686 val = 0x4000;
3687
3688 if (info->params.parity != ASYNC_PARITY_NONE) {
3689 val |= BIT9;
3690 if (info->params.parity == ASYNC_PARITY_ODD)
3691 val |= BIT8;
3692 }
3693
3694 switch (info->params.data_bits)
3695 {
3696 case 6: val |= BIT4; break;
3697 case 7: val |= BIT5; break;
3698 case 8: val |= BIT5 + BIT4; break;
3699 }
3700
3701 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3702 val |= BIT0;
3703
3704 wr_reg16(info, RCR, val);
3705
3706 /* CCR (clock control)
3707 *
3708 * 07..05 011 = tx clock source is BRG/16
3709 * 04..02 010 = rx clock source is BRG
3710 * 01 0 = auxclk disabled
3711 * 00 1 = BRG enabled
3712 *
3713 * 0110 1001
3714 */
3715 wr_reg8(info, CCR, 0x69);
3716
3717 msc_set_vcr(info);
3718
3719 tx_set_idle(info);
3720
3721 /* SCR (serial control)
3722 *
3723 * 15 1=tx req on FIFO half empty
3724 * 14 1=rx req on FIFO half full
3725 * 13 tx data IRQ enable
3726 * 12 tx idle IRQ enable
3727 * 11 rx break on IRQ enable
3728 * 10 rx data IRQ enable
3729 * 09 rx break off IRQ enable
3730 * 08 overrun IRQ enable
3731 * 07 DSR IRQ enable
3732 * 06 CTS IRQ enable
3733 * 05 DCD IRQ enable
3734 * 04 RI IRQ enable
3735 * 03 reserved, must be zero
3736 * 02 1=txd->rxd internal loopback enable
3737 * 01 reserved, must be zero
3738 * 00 1=master IRQ enable
3739 */
3740 val = BIT15 + BIT14 + BIT0;
3741 wr_reg16(info, SCR, val);
3742
3743 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3744
3745 set_rate(info, info->params.data_rate * 16);
3746
3747 if (info->params.loopback)
3748 enable_loopback(info);
3749}
3750
3751static void hdlc_mode(struct slgt_info *info)
3752{
3753 unsigned short val;
3754
3755 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3756 tx_stop(info);
3757 rx_stop(info);
3758
3759 /* TCR (tx control)
3760 *
3761 * 15..13 mode, 000=HDLC 001=raw sync
3762 * 12..10 encoding
3763 * 09 CRC enable
3764 * 08 CRC32
3765 * 07 1=RTS driver control
3766 * 06 preamble enable
3767 * 05..04 preamble length
3768 * 03 share open/close flag
3769 * 02 reset
3770 * 01 enable
3771 * 00 auto-CTS enable
3772 */
3773 val = 0;
3774
3775 if (info->params.mode == MGSL_MODE_RAW)
3776 val |= BIT13;
3777 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3778 val |= BIT7;
3779
3780 switch(info->params.encoding)
3781 {
3782 case HDLC_ENCODING_NRZB: val |= BIT10; break;
3783 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
3784 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
3785 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
3786 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
3787 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
3788 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
3789 }
3790
3791 switch (info->params.crc_type)
3792 {
3793 case HDLC_CRC_16_CCITT: val |= BIT9; break;
3794 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
3795 }
3796
3797 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3798 val |= BIT6;
3799
3800 switch (info->params.preamble_length)
3801 {
3802 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
3803 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
3804 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
3805 }
3806
3807 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3808 val |= BIT0;
3809
3810 wr_reg16(info, TCR, val);
3811
3812 /* TPR (transmit preamble) */
3813
3814 switch (info->params.preamble)
3815 {
3816 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3817 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3818 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
3819 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
3820 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
3821 default: val = 0x7e; break;
3822 }
3823 wr_reg8(info, TPR, (unsigned char)val);
3824
3825 /* RCR (rx control)
3826 *
3827 * 15..13 mode, 000=HDLC 001=raw sync
3828 * 12..10 encoding
3829 * 09 CRC enable
3830 * 08 CRC32
3831 * 07..03 reserved, must be 0
3832 * 02 reset
3833 * 01 enable
3834 * 00 auto-DCD enable
3835 */
3836 val = 0;
3837
3838 if (info->params.mode == MGSL_MODE_RAW)
3839 val |= BIT13;
3840
3841 switch(info->params.encoding)
3842 {
3843 case HDLC_ENCODING_NRZB: val |= BIT10; break;
3844 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
3845 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
3846 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
3847 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
3848 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
3849 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
3850 }
3851
3852 switch (info->params.crc_type)
3853 {
3854 case HDLC_CRC_16_CCITT: val |= BIT9; break;
3855 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
3856 }
3857
3858 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3859 val |= BIT0;
3860
3861 wr_reg16(info, RCR, val);
3862
3863 /* CCR (clock control)
3864 *
3865 * 07..05 tx clock source
3866 * 04..02 rx clock source
3867 * 01 auxclk enable
3868 * 00 BRG enable
3869 */
3870 val = 0;
3871
3872 if (info->params.flags & HDLC_FLAG_TXC_BRG)
3873 {
3874 // when RxC source is DPLL, BRG generates 16X DPLL
3875 // reference clock, so take TxC from BRG/16 to get
3876 // transmit clock at actual data rate
3877 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3878 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
3879 else
3880 val |= BIT6; /* 010, txclk = BRG */
3881 }
3882 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
3883 val |= BIT7; /* 100, txclk = DPLL Input */
3884 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
3885 val |= BIT5; /* 001, txclk = RXC Input */
3886
3887 if (info->params.flags & HDLC_FLAG_RXC_BRG)
3888 val |= BIT3; /* 010, rxclk = BRG */
3889 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3890 val |= BIT4; /* 100, rxclk = DPLL */
3891 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
3892 val |= BIT2; /* 001, rxclk = TXC Input */
3893
3894 if (info->params.clock_speed)
3895 val |= BIT1 + BIT0;
3896
3897 wr_reg8(info, CCR, (unsigned char)val);
3898
3899 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
3900 {
3901 // program DPLL mode
3902 switch(info->params.encoding)
3903 {
3904 case HDLC_ENCODING_BIPHASE_MARK:
3905 case HDLC_ENCODING_BIPHASE_SPACE:
3906 val = BIT7; break;
3907 case HDLC_ENCODING_BIPHASE_LEVEL:
3908 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
3909 val = BIT7 + BIT6; break;
3910 default: val = BIT6; // NRZ encodings
3911 }
3912 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
3913
3914 // DPLL requires a 16X reference clock from BRG
3915 set_rate(info, info->params.clock_speed * 16);
3916 }
3917 else
3918 set_rate(info, info->params.clock_speed);
3919
3920 tx_set_idle(info);
3921
3922 msc_set_vcr(info);
3923
3924 /* SCR (serial control)
3925 *
3926 * 15 1=tx req on FIFO half empty
3927 * 14 1=rx req on FIFO half full
3928 * 13 tx data IRQ enable
3929 * 12 tx idle IRQ enable
3930 * 11 underrun IRQ enable
3931 * 10 rx data IRQ enable
3932 * 09 rx idle IRQ enable
3933 * 08 overrun IRQ enable
3934 * 07 DSR IRQ enable
3935 * 06 CTS IRQ enable
3936 * 05 DCD IRQ enable
3937 * 04 RI IRQ enable
3938 * 03 reserved, must be zero
3939 * 02 1=txd->rxd internal loopback enable
3940 * 01 reserved, must be zero
3941 * 00 1=master IRQ enable
3942 */
3943 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
3944
3945 if (info->params.loopback)
3946 enable_loopback(info);
3947}
3948
3949/*
3950 * set transmit idle mode
3951 */
3952static void tx_set_idle(struct slgt_info *info)
3953{
3954 unsigned char val = 0xff;
3955
3956 switch(info->idle_mode)
3957 {
3958 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
3959 case HDLC_TXIDLE_ALT_ZEROS_ONES: val = 0xaa; break;
3960 case HDLC_TXIDLE_ZEROS: val = 0x00; break;
3961 case HDLC_TXIDLE_ONES: val = 0xff; break;
3962 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
3963 case HDLC_TXIDLE_SPACE: val = 0x00; break;
3964 case HDLC_TXIDLE_MARK: val = 0xff; break;
3965 }
3966
3967 wr_reg8(info, TIR, val);
3968}
3969
3970/*
3971 * get state of V24 status (input) signals
3972 */
3973static void get_signals(struct slgt_info *info)
3974{
3975 unsigned short status = rd_reg16(info, SSR);
3976
3977 /* clear all serial signals except DTR and RTS */
3978 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
3979
3980 if (status & BIT3)
3981 info->signals |= SerialSignal_DSR;
3982 if (status & BIT2)
3983 info->signals |= SerialSignal_CTS;
3984 if (status & BIT1)
3985 info->signals |= SerialSignal_DCD;
3986 if (status & BIT0)
3987 info->signals |= SerialSignal_RI;
3988}
3989
3990/*
3991 * set V.24 Control Register based on current configuration
3992 */
3993static void msc_set_vcr(struct slgt_info *info)
3994{
3995 unsigned char val = 0;
3996
3997 /* VCR (V.24 control)
3998 *
3999 * 07..04 serial IF select
4000 * 03 DTR
4001 * 02 RTS
4002 * 01 LL
4003 * 00 RL
4004 */
4005
4006 switch(info->if_mode & MGSL_INTERFACE_MASK)
4007 {
4008 case MGSL_INTERFACE_RS232:
4009 val |= BIT5; /* 0010 */
4010 break;
4011 case MGSL_INTERFACE_V35:
4012 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4013 break;
4014 case MGSL_INTERFACE_RS422:
4015 val |= BIT6; /* 0100 */
4016 break;
4017 }
4018
4019 if (info->signals & SerialSignal_DTR)
4020 val |= BIT3;
4021 if (info->signals & SerialSignal_RTS)
4022 val |= BIT2;
4023 if (info->if_mode & MGSL_INTERFACE_LL)
4024 val |= BIT1;
4025 if (info->if_mode & MGSL_INTERFACE_RL)
4026 val |= BIT0;
4027 wr_reg8(info, VCR, val);
4028}
4029
4030/*
4031 * set state of V24 control (output) signals
4032 */
4033static void set_signals(struct slgt_info *info)
4034{
4035 unsigned char val = rd_reg8(info, VCR);
4036 if (info->signals & SerialSignal_DTR)
4037 val |= BIT3;
4038 else
4039 val &= ~BIT3;
4040 if (info->signals & SerialSignal_RTS)
4041 val |= BIT2;
4042 else
4043 val &= ~BIT2;
4044 wr_reg8(info, VCR, val);
4045}
4046
4047/*
4048 * free range of receive DMA buffers (i to last)
4049 */
4050static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4051{
4052 int done = 0;
4053
4054 while(!done) {
4055 /* reset current buffer for reuse */
4056 info->rbufs[i].status = 0;
4057 if (info->params.mode == MGSL_MODE_RAW)
4058 set_desc_count(info->rbufs[i], info->raw_rx_size);
4059 else
4060 set_desc_count(info->rbufs[i], DMABUFSIZE);
4061
4062 if (i == last)
4063 done = 1;
4064 if (++i == info->rbuf_count)
4065 i = 0;
4066 }
4067 info->rbuf_current = i;
4068}
4069
4070/*
4071 * mark all receive DMA buffers as free
4072 */
4073static void reset_rbufs(struct slgt_info *info)
4074{
4075 free_rbufs(info, 0, info->rbuf_count - 1);
4076}
4077
4078/*
4079 * pass receive HDLC frame to upper layer
4080 *
4081 * return 1 if frame available, otherwise 0
4082 */
4083static int rx_get_frame(struct slgt_info *info)
4084{
4085 unsigned int start, end;
4086 unsigned short status;
4087 unsigned int framesize = 0;
4088 int rc = 0;
4089 unsigned long flags;
4090 struct tty_struct *tty = info->tty;
4091 unsigned char addr_field = 0xff;
4092
4093check_again:
4094
4095 framesize = 0;
4096 addr_field = 0xff;
4097 start = end = info->rbuf_current;
4098
4099 for (;;) {
4100 if (!desc_complete(info->rbufs[end]))
4101 goto cleanup;
4102
4103 if (framesize == 0 && info->params.addr_filter != 0xff)
4104 addr_field = info->rbufs[end].buf[0];
4105
4106 framesize += desc_count(info->rbufs[end]);
4107
4108 if (desc_eof(info->rbufs[end]))
4109 break;
4110
4111 if (++end == info->rbuf_count)
4112 end = 0;
4113
4114 if (end == info->rbuf_current) {
4115 if (info->rx_enabled){
4116 spin_lock_irqsave(&info->lock,flags);
4117 rx_start(info);
4118 spin_unlock_irqrestore(&info->lock,flags);
4119 }
4120 goto cleanup;
4121 }
4122 }
4123
4124 /* status
4125 *
4126 * 15 buffer complete
4127 * 14..06 reserved
4128 * 05..04 residue
4129 * 02 eof (end of frame)
4130 * 01 CRC error
4131 * 00 abort
4132 */
4133 status = desc_status(info->rbufs[end]);
4134
4135 /* ignore CRC bit if not using CRC (bit is undefined) */
4136 if (info->params.crc_type == HDLC_CRC_NONE)
4137 status &= ~BIT1;
4138
4139 if (framesize == 0 ||
4140 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4141 free_rbufs(info, start, end);
4142 goto check_again;
4143 }
4144
4145 if (framesize < 2 || status & (BIT1+BIT0)) {
4146 if (framesize < 2 || (status & BIT0))
4147 info->icount.rxshort++;
4148 else
4149 info->icount.rxcrc++;
4150 framesize = 0;
4151
4152#ifdef CONFIG_HDLC
4153 {
4154 struct net_device_stats *stats = hdlc_stats(info->netdev);
4155 stats->rx_errors++;
4156 stats->rx_frame_errors++;
4157 }
4158#endif
4159 } else {
4160 /* adjust frame size for CRC, if any */
4161 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4162 framesize -= 2;
4163 else if (info->params.crc_type == HDLC_CRC_32_CCITT)
4164 framesize -= 4;
4165 }
4166
4167 DBGBH(("%s rx frame status=%04X size=%d\n",
4168 info->device_name, status, framesize));
4169 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4170
4171 if (framesize) {
4172 if (framesize > info->max_frame_size)
4173 info->icount.rxlong++;
4174 else {
4175 /* copy dma buffer(s) to contiguous temp buffer */
4176 int copy_count = framesize;
4177 int i = start;
4178 unsigned char *p = info->tmp_rbuf;
4179 info->tmp_rbuf_count = framesize;
4180
4181 info->icount.rxok++;
4182
4183 while(copy_count) {
4184 int partial_count = min(copy_count, DMABUFSIZE);
4185 memcpy(p, info->rbufs[i].buf, partial_count);
4186 p += partial_count;
4187 copy_count -= partial_count;
4188 if (++i == info->rbuf_count)
4189 i = 0;
4190 }
4191
4192#ifdef CONFIG_HDLC
4193 if (info->netcount)
4194 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4195 else
4196#endif
4197 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4198 }
4199 }
4200 free_rbufs(info, start, end);
4201 rc = 1;
4202
4203cleanup:
4204 return rc;
4205}
4206
4207/*
4208 * pass receive buffer (RAW synchronous mode) to tty layer
4209 * return 1 if buffer available, otherwise 0
4210 */
4211static int rx_get_buf(struct slgt_info *info)
4212{
4213 unsigned int i = info->rbuf_current;
4214
4215 if (!desc_complete(info->rbufs[i]))
4216 return 0;
4217 DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx");
4218 DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i])));
4219 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4220 info->flag_buf, desc_count(info->rbufs[i]));
4221 free_rbufs(info, i, i);
4222 return 1;
4223}
4224
4225static void reset_tbufs(struct slgt_info *info)
4226{
4227 unsigned int i;
4228 info->tbuf_current = 0;
4229 for (i=0 ; i < info->tbuf_count ; i++) {
4230 info->tbufs[i].status = 0;
4231 info->tbufs[i].count = 0;
4232 }
4233}
4234
4235/*
4236 * return number of free transmit DMA buffers
4237 */
4238static unsigned int free_tbuf_count(struct slgt_info *info)
4239{
4240 unsigned int count = 0;
4241 unsigned int i = info->tbuf_current;
4242
4243 do
4244 {
4245 if (desc_count(info->tbufs[i]))
4246 break; /* buffer in use */
4247 ++count;
4248 if (++i == info->tbuf_count)
4249 i=0;
4250 } while (i != info->tbuf_current);
4251
4252 /* last buffer with zero count may be in use, assume it is */
4253 if (count)
4254 --count;
4255
4256 return count;
4257}
4258
4259/*
4260 * load transmit DMA buffer(s) with data
4261 */
4262static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4263{
4264 unsigned short count;
4265 unsigned int i;
4266 struct slgt_desc *d;
4267
4268 if (size == 0)
4269 return;
4270
4271 DBGDATA(info, buf, size, "tx");
4272
4273 info->tbuf_start = i = info->tbuf_current;
4274
4275 while (size) {
4276 d = &info->tbufs[i];
4277 if (++i == info->tbuf_count)
4278 i = 0;
4279
4280 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4281 memcpy(d->buf, buf, count);
4282
4283 size -= count;
4284 buf += count;
4285
4286 if (!size && info->params.mode != MGSL_MODE_RAW)
4287 set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */
4288 else
4289 set_desc_eof(*d, 0);
4290
4291 set_desc_count(*d, count);
4292 }
4293
4294 info->tbuf_current = i;
4295}
4296
4297static int register_test(struct slgt_info *info)
4298{
4299 static unsigned short patterns[] =
4300 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4301 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4302 unsigned int i;
4303 int rc = 0;
4304
4305 for (i=0 ; i < count ; i++) {
4306 wr_reg16(info, TIR, patterns[i]);
4307 wr_reg16(info, BDR, patterns[(i+1)%count]);
4308 if ((rd_reg16(info, TIR) != patterns[i]) ||
4309 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4310 rc = -ENODEV;
4311 break;
4312 }
4313 }
4314
4315 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4316 return rc;
4317}
4318
4319static int irq_test(struct slgt_info *info)
4320{
4321 unsigned long timeout;
4322 unsigned long flags;
4323 struct tty_struct *oldtty = info->tty;
4324 u32 speed = info->params.data_rate;
4325
4326 info->params.data_rate = 921600;
4327 info->tty = NULL;
4328
4329 spin_lock_irqsave(&info->lock, flags);
4330 async_mode(info);
4331 slgt_irq_on(info, IRQ_TXIDLE);
4332
4333 /* enable transmitter */
4334 wr_reg16(info, TCR,
4335 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4336
4337 /* write one byte and wait for tx idle */
4338 wr_reg16(info, TDR, 0);
4339
4340 /* assume failure */
4341 info->init_error = DiagStatus_IrqFailure;
4342 info->irq_occurred = FALSE;
4343
4344 spin_unlock_irqrestore(&info->lock, flags);
4345
4346 timeout=100;
4347 while(timeout-- && !info->irq_occurred)
4348 msleep_interruptible(10);
4349
4350 spin_lock_irqsave(&info->lock,flags);
4351 reset_port(info);
4352 spin_unlock_irqrestore(&info->lock,flags);
4353
4354 info->params.data_rate = speed;
4355 info->tty = oldtty;
4356
4357 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4358 return info->irq_occurred ? 0 : -ENODEV;
4359}
4360
4361static int loopback_test_rx(struct slgt_info *info)
4362{
4363 unsigned char *src, *dest;
4364 int count;
4365
4366 if (desc_complete(info->rbufs[0])) {
4367 count = desc_count(info->rbufs[0]);
4368 src = info->rbufs[0].buf;
4369 dest = info->tmp_rbuf;
4370
4371 for( ; count ; count-=2, src+=2) {
4372 /* src=data byte (src+1)=status byte */
4373 if (!(*(src+1) & (BIT9 + BIT8))) {
4374 *dest = *src;
4375 dest++;
4376 info->tmp_rbuf_count++;
4377 }
4378 }
4379 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4380 return 1;
4381 }
4382 return 0;
4383}
4384
4385static int loopback_test(struct slgt_info *info)
4386{
4387#define TESTFRAMESIZE 20
4388
4389 unsigned long timeout;
4390 u16 count = TESTFRAMESIZE;
4391 unsigned char buf[TESTFRAMESIZE];
4392 int rc = -ENODEV;
4393 unsigned long flags;
4394
4395 struct tty_struct *oldtty = info->tty;
4396 MGSL_PARAMS params;
4397
4398 memcpy(&params, &info->params, sizeof(params));
4399
4400 info->params.mode = MGSL_MODE_ASYNC;
4401 info->params.data_rate = 921600;
4402 info->params.loopback = 1;
4403 info->tty = NULL;
4404
4405 /* build and send transmit frame */
4406 for (count = 0; count < TESTFRAMESIZE; ++count)
4407 buf[count] = (unsigned char)count;
4408
4409 info->tmp_rbuf_count = 0;
4410 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4411
4412 /* program hardware for HDLC and enabled receiver */
4413 spin_lock_irqsave(&info->lock,flags);
4414 async_mode(info);
4415 rx_start(info);
4416 info->tx_count = count;
4417 tx_load(info, buf, count);
4418 tx_start(info);
4419 spin_unlock_irqrestore(&info->lock, flags);
4420
4421 /* wait for receive complete */
4422 for (timeout = 100; timeout; --timeout) {
4423 msleep_interruptible(10);
4424 if (loopback_test_rx(info)) {
4425 rc = 0;
4426 break;
4427 }
4428 }
4429
4430 /* verify received frame length and contents */
4431 if (!rc && (info->tmp_rbuf_count != count ||
4432 memcmp(buf, info->tmp_rbuf, count))) {
4433 rc = -ENODEV;
4434 }
4435
4436 spin_lock_irqsave(&info->lock,flags);
4437 reset_adapter(info);
4438 spin_unlock_irqrestore(&info->lock,flags);
4439
4440 memcpy(&info->params, &params, sizeof(info->params));
4441 info->tty = oldtty;
4442
4443 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4444 return rc;
4445}
4446
4447static int adapter_test(struct slgt_info *info)
4448{
4449 DBGINFO(("testing %s\n", info->device_name));
4450 if ((info->init_error = register_test(info)) < 0) {
4451 printk("register test failure %s addr=%08X\n",
4452 info->device_name, info->phys_reg_addr);
4453 } else if ((info->init_error = irq_test(info)) < 0) {
4454 printk("IRQ test failure %s IRQ=%d\n",
4455 info->device_name, info->irq_level);
4456 } else if ((info->init_error = loopback_test(info)) < 0) {
4457 printk("loopback test failure %s\n", info->device_name);
4458 }
4459 return info->init_error;
4460}
4461
4462/*
4463 * transmit timeout handler
4464 */
4465static void tx_timeout(unsigned long context)
4466{
4467 struct slgt_info *info = (struct slgt_info*)context;
4468 unsigned long flags;
4469
4470 DBGINFO(("%s tx_timeout\n", info->device_name));
4471 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4472 info->icount.txtimeout++;
4473 }
4474 spin_lock_irqsave(&info->lock,flags);
4475 info->tx_active = 0;
4476 info->tx_count = 0;
4477 spin_unlock_irqrestore(&info->lock,flags);
4478
4479#ifdef CONFIG_HDLC
4480 if (info->netcount)
4481 hdlcdev_tx_done(info);
4482 else
4483#endif
4484 bh_transmit(info);
4485}
4486
4487/*
4488 * receive buffer polling timer
4489 */
4490static void rx_timeout(unsigned long context)
4491{
4492 struct slgt_info *info = (struct slgt_info*)context;
4493 unsigned long flags;
4494
4495 DBGINFO(("%s rx_timeout\n", info->device_name));
4496 spin_lock_irqsave(&info->lock, flags);
4497 info->pending_bh |= BH_RECEIVE;
4498 spin_unlock_irqrestore(&info->lock, flags);
4499 bh_handler(info);
4500}
4501