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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* ibmmpeg2.h - IBM MPEGCD21 definitions */
2
3#ifndef __IBM_MPEG2__
4#define __IBM_MPEG2__
5
6/* Define all MPEG Decoder registers */
7/* Chip Control and Status */
8#define IBM_MP2_CHIP_CONTROL 0x200*2
9#define IBM_MP2_CHIP_MODE 0x201*2
10/* Timer Control and Status */
11#define IBM_MP2_SYNC_STC2 0x202*2
12#define IBM_MP2_SYNC_STC1 0x203*2
13#define IBM_MP2_SYNC_STC0 0x204*2
14#define IBM_MP2_SYNC_PTS2 0x205*2
15#define IBM_MP2_SYNC_PTS1 0x206*2
16#define IBM_MP2_SYNC_PTS0 0x207*2
17/* Video FIFO Control */
18#define IBM_MP2_FIFO 0x208*2
19#define IBM_MP2_FIFOW 0x100*2
20#define IBM_MP2_FIFO_STAT 0x209*2
21#define IBM_MP2_RB_THRESHOLD 0x22b*2
22/* Command buffer */
23#define IBM_MP2_COMMAND 0x20a*2
24#define IBM_MP2_CMD_DATA 0x20b*2
25#define IBM_MP2_CMD_STAT 0x20c*2
26#define IBM_MP2_CMD_ADDR 0x20d*2
27/* Internal Processor Control and Status */
28#define IBM_MP2_PROC_IADDR 0x20e*2
29#define IBM_MP2_PROC_IDATA 0x20f*2
30#define IBM_MP2_WR_PROT 0x235*2
31/* DRAM Access */
32#define IBM_MP2_DRAM_ADDR 0x210*2
33#define IBM_MP2_DRAM_DATA 0x212*2
34#define IBM_MP2_DRAM_CMD_STAT 0x213*2
35#define IBM_MP2_BLOCK_SIZE 0x23b*2
36#define IBM_MP2_SRC_ADDR 0x23c*2
37/* Onscreen Display */
38#define IBM_MP2_OSD_ADDR 0x214*2
39#define IBM_MP2_OSD_DATA 0x215*2
40#define IBM_MP2_OSD_MODE 0x217*2
41#define IBM_MP2_OSD_LINK_ADDR 0x229*2
42#define IBM_MP2_OSD_SIZE 0x22a*2
43/* Interrupt Control */
44#define IBM_MP2_HOST_INT 0x218*2
45#define IBM_MP2_MASK0 0x219*2
46#define IBM_MP2_HOST_INT1 0x23e*2
47#define IBM_MP2_MASK1 0x23f*2
48/* Audio Control */
49#define IBM_MP2_AUD_IADDR 0x21a*2
50#define IBM_MP2_AUD_IDATA 0x21b*2
51#define IBM_MP2_AUD_FIFO 0x21c*2
52#define IBM_MP2_AUD_FIFOW 0x101*2
53#define IBM_MP2_AUD_CTL 0x21d*2
54#define IBM_MP2_BEEP_CTL 0x21e*2
55#define IBM_MP2_FRNT_ATTEN 0x22d*2
56/* Display Control */
57#define IBM_MP2_DISP_MODE 0x220*2
58#define IBM_MP2_DISP_DLY 0x221*2
59#define IBM_MP2_VBI_CTL 0x222*2
60#define IBM_MP2_DISP_LBOR 0x223*2
61#define IBM_MP2_DISP_TBOR 0x224*2
62/* Polarity Control */
63#define IBM_MP2_INFC_CTL 0x22c*2
64
65/* control commands */
66#define IBM_MP2_PLAY 0
67#define IBM_MP2_PAUSE 1
68#define IBM_MP2_SINGLE_FRAME 2
69#define IBM_MP2_FAST_FORWARD 3
70#define IBM_MP2_SLOW_MOTION 4
71#define IBM_MP2_IMED_NORM_PLAY 5
72#define IBM_MP2_RESET_WINDOW 6
73#define IBM_MP2_FREEZE_FRAME 7
74#define IBM_MP2_RESET_VID_RATE 8
75#define IBM_MP2_CONFIG_DECODER 9
76#define IBM_MP2_CHANNEL_SWITCH 10
77#define IBM_MP2_RESET_AUD_RATE 11
78#define IBM_MP2_PRE_OP_CHN_SW 12
79#define IBM_MP2_SET_STILL_MODE 14
80
81/* Define Xilinx FPGA Internal Registers */
82
83/* general control register 0 */
84#define XILINX_CTL0 0x600
85/* genlock delay resister 1 */
86#define XILINX_GLDELAY 0x602
87/* send 16 bits to CS3310 port */
88#define XILINX_CS3310 0x604
89/* send 16 bits to CS3310 and complete */
90#define XILINX_CS3310_CMPLT 0x60c
91/* pulse width modulator control */
92#define XILINX_PWM 0x606
93
94#endif