Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Marvell International Ltd. All rights reserved. |
| 3 | * Author: Chao Xie <chao.xie@marvell.com> |
| 4 | * Neil Zhang <zhangwm@marvell.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 12 | #include <linux/module.h> |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/dma-mapping.h> |
| 15 | #include <linux/dmapool.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/ioport.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/errno.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/timer.h> |
| 24 | #include <linux/list.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/moduleparam.h> |
| 27 | #include <linux/device.h> |
| 28 | #include <linux/usb/ch9.h> |
| 29 | #include <linux/usb/gadget.h> |
| 30 | #include <linux/usb/otg.h> |
| 31 | #include <linux/pm.h> |
| 32 | #include <linux/io.h> |
| 33 | #include <linux/irq.h> |
| 34 | #include <linux/platform_device.h> |
| 35 | #include <linux/clk.h> |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 36 | #include <linux/platform_data/mv_usb.h> |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 37 | #include <asm/system.h> |
| 38 | #include <asm/unaligned.h> |
| 39 | |
| 40 | #include "mv_udc.h" |
| 41 | |
| 42 | #define DRIVER_DESC "Marvell PXA USB Device Controller driver" |
| 43 | #define DRIVER_VERSION "8 Nov 2010" |
| 44 | |
| 45 | #define ep_dir(ep) (((ep)->ep_num == 0) ? \ |
| 46 | ((ep)->udc->ep0_dir) : ((ep)->direction)) |
| 47 | |
| 48 | /* timeout value -- usec */ |
| 49 | #define RESET_TIMEOUT 10000 |
| 50 | #define FLUSH_TIMEOUT 10000 |
| 51 | #define EPSTATUS_TIMEOUT 10000 |
| 52 | #define PRIME_TIMEOUT 10000 |
| 53 | #define READSAFE_TIMEOUT 1000 |
| 54 | #define DTD_TIMEOUT 1000 |
| 55 | |
| 56 | #define LOOPS_USEC_SHIFT 4 |
| 57 | #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT) |
| 58 | #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT) |
| 59 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 60 | static DECLARE_COMPLETION(release_done); |
| 61 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 62 | static const char driver_name[] = "mv_udc"; |
| 63 | static const char driver_desc[] = DRIVER_DESC; |
| 64 | |
| 65 | /* controller device global variable */ |
| 66 | static struct mv_udc *the_controller; |
| 67 | int mv_usb_otgsc; |
| 68 | |
| 69 | static void nuke(struct mv_ep *ep, int status); |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 70 | static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 71 | |
| 72 | /* for endpoint 0 operations */ |
| 73 | static const struct usb_endpoint_descriptor mv_ep0_desc = { |
| 74 | .bLength = USB_DT_ENDPOINT_SIZE, |
| 75 | .bDescriptorType = USB_DT_ENDPOINT, |
| 76 | .bEndpointAddress = 0, |
| 77 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, |
| 78 | .wMaxPacketSize = EP0_MAX_PKT_SIZE, |
| 79 | }; |
| 80 | |
| 81 | static void ep0_reset(struct mv_udc *udc) |
| 82 | { |
| 83 | struct mv_ep *ep; |
| 84 | u32 epctrlx; |
| 85 | int i = 0; |
| 86 | |
| 87 | /* ep0 in and out */ |
| 88 | for (i = 0; i < 2; i++) { |
| 89 | ep = &udc->eps[i]; |
| 90 | ep->udc = udc; |
| 91 | |
| 92 | /* ep0 dQH */ |
| 93 | ep->dqh = &udc->ep_dqh[i]; |
| 94 | |
| 95 | /* configure ep0 endpoint capabilities in dQH */ |
| 96 | ep->dqh->max_packet_length = |
| 97 | (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) |
| 98 | | EP_QUEUE_HEAD_IOS; |
| 99 | |
Neil Zhang | fbebe1f | 2011-10-12 16:49:29 +0800 | [diff] [blame] | 100 | ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE; |
| 101 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 102 | epctrlx = readl(&udc->op_regs->epctrlx[0]); |
| 103 | if (i) { /* TX */ |
Neil Zhang | 43ad9f3 | 2011-10-12 16:49:28 +0800 | [diff] [blame] | 104 | epctrlx |= EPCTRL_TX_ENABLE |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 105 | | (USB_ENDPOINT_XFER_CONTROL |
| 106 | << EPCTRL_TX_EP_TYPE_SHIFT); |
| 107 | |
| 108 | } else { /* RX */ |
Neil Zhang | 43ad9f3 | 2011-10-12 16:49:28 +0800 | [diff] [blame] | 109 | epctrlx |= EPCTRL_RX_ENABLE |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 110 | | (USB_ENDPOINT_XFER_CONTROL |
| 111 | << EPCTRL_RX_EP_TYPE_SHIFT); |
| 112 | } |
| 113 | |
| 114 | writel(epctrlx, &udc->op_regs->epctrlx[0]); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | /* protocol ep0 stall, will automatically be cleared on new transaction */ |
| 119 | static void ep0_stall(struct mv_udc *udc) |
| 120 | { |
| 121 | u32 epctrlx; |
| 122 | |
| 123 | /* set TX and RX to stall */ |
| 124 | epctrlx = readl(&udc->op_regs->epctrlx[0]); |
| 125 | epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL; |
| 126 | writel(epctrlx, &udc->op_regs->epctrlx[0]); |
| 127 | |
| 128 | /* update ep0 state */ |
| 129 | udc->ep0_state = WAIT_FOR_SETUP; |
| 130 | udc->ep0_dir = EP_DIR_OUT; |
| 131 | } |
| 132 | |
| 133 | static int process_ep_req(struct mv_udc *udc, int index, |
| 134 | struct mv_req *curr_req) |
| 135 | { |
| 136 | struct mv_dtd *curr_dtd; |
| 137 | struct mv_dqh *curr_dqh; |
| 138 | int td_complete, actual, remaining_length; |
| 139 | int i, direction; |
| 140 | int retval = 0; |
| 141 | u32 errors; |
Neil Zhang | daec765 | 2011-10-12 16:49:36 +0800 | [diff] [blame] | 142 | u32 bit_pos; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 143 | |
| 144 | curr_dqh = &udc->ep_dqh[index]; |
| 145 | direction = index % 2; |
| 146 | |
| 147 | curr_dtd = curr_req->head; |
| 148 | td_complete = 0; |
| 149 | actual = curr_req->req.length; |
| 150 | |
| 151 | for (i = 0; i < curr_req->dtd_count; i++) { |
| 152 | if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) { |
| 153 | dev_dbg(&udc->dev->dev, "%s, dTD not completed\n", |
| 154 | udc->eps[index].name); |
| 155 | return 1; |
| 156 | } |
| 157 | |
| 158 | errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK; |
| 159 | if (!errors) { |
Neil Zhang | daec765 | 2011-10-12 16:49:36 +0800 | [diff] [blame] | 160 | remaining_length = |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 161 | (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE) |
| 162 | >> DTD_LENGTH_BIT_POS; |
| 163 | actual -= remaining_length; |
Neil Zhang | daec765 | 2011-10-12 16:49:36 +0800 | [diff] [blame] | 164 | |
| 165 | if (remaining_length) { |
| 166 | if (direction) { |
| 167 | dev_dbg(&udc->dev->dev, |
| 168 | "TX dTD remains data\n"); |
| 169 | retval = -EPROTO; |
| 170 | break; |
| 171 | } else |
| 172 | break; |
| 173 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 174 | } else { |
| 175 | dev_info(&udc->dev->dev, |
| 176 | "complete_tr error: ep=%d %s: error = 0x%x\n", |
| 177 | index >> 1, direction ? "SEND" : "RECV", |
| 178 | errors); |
| 179 | if (errors & DTD_STATUS_HALTED) { |
| 180 | /* Clear the errors and Halt condition */ |
| 181 | curr_dqh->size_ioc_int_sts &= ~errors; |
| 182 | retval = -EPIPE; |
| 183 | } else if (errors & DTD_STATUS_DATA_BUFF_ERR) { |
| 184 | retval = -EPROTO; |
| 185 | } else if (errors & DTD_STATUS_TRANSACTION_ERR) { |
| 186 | retval = -EILSEQ; |
| 187 | } |
| 188 | } |
| 189 | if (i != curr_req->dtd_count - 1) |
| 190 | curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt; |
| 191 | } |
| 192 | if (retval) |
| 193 | return retval; |
| 194 | |
Neil Zhang | daec765 | 2011-10-12 16:49:36 +0800 | [diff] [blame] | 195 | if (direction == EP_DIR_OUT) |
| 196 | bit_pos = 1 << curr_req->ep->ep_num; |
| 197 | else |
| 198 | bit_pos = 1 << (16 + curr_req->ep->ep_num); |
| 199 | |
| 200 | while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) { |
| 201 | if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) { |
| 202 | while (readl(&udc->op_regs->epstatus) & bit_pos) |
| 203 | udelay(1); |
| 204 | break; |
| 205 | } |
| 206 | udelay(1); |
| 207 | } |
| 208 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 209 | curr_req->req.actual = actual; |
| 210 | |
| 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | /* |
| 215 | * done() - retire a request; caller blocked irqs |
| 216 | * @status : request status to be set, only works when |
| 217 | * request is still in progress. |
| 218 | */ |
| 219 | static void done(struct mv_ep *ep, struct mv_req *req, int status) |
| 220 | { |
| 221 | struct mv_udc *udc = NULL; |
| 222 | unsigned char stopped = ep->stopped; |
| 223 | struct mv_dtd *curr_td, *next_td; |
| 224 | int j; |
| 225 | |
| 226 | udc = (struct mv_udc *)ep->udc; |
| 227 | /* Removed the req from fsl_ep->queue */ |
| 228 | list_del_init(&req->queue); |
| 229 | |
| 230 | /* req.status should be set as -EINPROGRESS in ep_queue() */ |
| 231 | if (req->req.status == -EINPROGRESS) |
| 232 | req->req.status = status; |
| 233 | else |
| 234 | status = req->req.status; |
| 235 | |
| 236 | /* Free dtd for the request */ |
| 237 | next_td = req->head; |
| 238 | for (j = 0; j < req->dtd_count; j++) { |
| 239 | curr_td = next_td; |
| 240 | if (j != req->dtd_count - 1) |
| 241 | next_td = curr_td->next_dtd_virt; |
| 242 | dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma); |
| 243 | } |
| 244 | |
| 245 | if (req->mapped) { |
| 246 | dma_unmap_single(ep->udc->gadget.dev.parent, |
| 247 | req->req.dma, req->req.length, |
| 248 | ((ep_dir(ep) == EP_DIR_IN) ? |
| 249 | DMA_TO_DEVICE : DMA_FROM_DEVICE)); |
| 250 | req->req.dma = DMA_ADDR_INVALID; |
| 251 | req->mapped = 0; |
| 252 | } else |
| 253 | dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, |
| 254 | req->req.dma, req->req.length, |
| 255 | ((ep_dir(ep) == EP_DIR_IN) ? |
| 256 | DMA_TO_DEVICE : DMA_FROM_DEVICE)); |
| 257 | |
| 258 | if (status && (status != -ESHUTDOWN)) |
| 259 | dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u", |
| 260 | ep->ep.name, &req->req, status, |
| 261 | req->req.actual, req->req.length); |
| 262 | |
| 263 | ep->stopped = 1; |
| 264 | |
| 265 | spin_unlock(&ep->udc->lock); |
| 266 | /* |
| 267 | * complete() is from gadget layer, |
| 268 | * eg fsg->bulk_in_complete() |
| 269 | */ |
| 270 | if (req->req.complete) |
| 271 | req->req.complete(&ep->ep, &req->req); |
| 272 | |
| 273 | spin_lock(&ep->udc->lock); |
| 274 | ep->stopped = stopped; |
| 275 | } |
| 276 | |
| 277 | static int queue_dtd(struct mv_ep *ep, struct mv_req *req) |
| 278 | { |
| 279 | u32 tmp, epstatus, bit_pos, direction; |
| 280 | struct mv_udc *udc; |
| 281 | struct mv_dqh *dqh; |
| 282 | unsigned int loops; |
| 283 | int readsafe, retval = 0; |
| 284 | |
| 285 | udc = ep->udc; |
| 286 | direction = ep_dir(ep); |
| 287 | dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]); |
| 288 | bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num); |
| 289 | |
| 290 | /* check if the pipe is empty */ |
| 291 | if (!(list_empty(&ep->queue))) { |
| 292 | struct mv_req *lastreq; |
| 293 | lastreq = list_entry(ep->queue.prev, struct mv_req, queue); |
| 294 | lastreq->tail->dtd_next = |
| 295 | req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; |
| 296 | if (readl(&udc->op_regs->epprime) & bit_pos) { |
| 297 | loops = LOOPS(PRIME_TIMEOUT); |
| 298 | while (readl(&udc->op_regs->epprime) & bit_pos) { |
| 299 | if (loops == 0) { |
| 300 | retval = -ETIME; |
| 301 | goto done; |
| 302 | } |
| 303 | udelay(LOOPS_USEC); |
| 304 | loops--; |
| 305 | } |
| 306 | if (readl(&udc->op_regs->epstatus) & bit_pos) |
| 307 | goto done; |
| 308 | } |
| 309 | readsafe = 0; |
| 310 | loops = LOOPS(READSAFE_TIMEOUT); |
| 311 | while (readsafe == 0) { |
| 312 | if (loops == 0) { |
| 313 | retval = -ETIME; |
| 314 | goto done; |
| 315 | } |
| 316 | /* start with setting the semaphores */ |
| 317 | tmp = readl(&udc->op_regs->usbcmd); |
| 318 | tmp |= USBCMD_ATDTW_TRIPWIRE_SET; |
| 319 | writel(tmp, &udc->op_regs->usbcmd); |
| 320 | |
| 321 | /* read the endpoint status */ |
| 322 | epstatus = readl(&udc->op_regs->epstatus) & bit_pos; |
| 323 | |
| 324 | /* |
| 325 | * Reread the ATDTW semaphore bit to check if it is |
| 326 | * cleared. When hardware see a hazard, it will clear |
| 327 | * the bit or else we remain set to 1 and we can |
| 328 | * proceed with priming of endpoint if not already |
| 329 | * primed. |
| 330 | */ |
| 331 | if (readl(&udc->op_regs->usbcmd) |
| 332 | & USBCMD_ATDTW_TRIPWIRE_SET) { |
| 333 | readsafe = 1; |
| 334 | } |
| 335 | loops--; |
| 336 | udelay(LOOPS_USEC); |
| 337 | } |
| 338 | |
| 339 | /* Clear the semaphore */ |
| 340 | tmp = readl(&udc->op_regs->usbcmd); |
| 341 | tmp &= USBCMD_ATDTW_TRIPWIRE_CLEAR; |
| 342 | writel(tmp, &udc->op_regs->usbcmd); |
| 343 | |
| 344 | /* If endpoint is not active, we activate it now. */ |
| 345 | if (!epstatus) { |
| 346 | if (direction == EP_DIR_IN) { |
| 347 | struct mv_dtd *curr_dtd = dma_to_virt( |
| 348 | &udc->dev->dev, dqh->curr_dtd_ptr); |
| 349 | |
| 350 | loops = LOOPS(DTD_TIMEOUT); |
| 351 | while (curr_dtd->size_ioc_sts |
| 352 | & DTD_STATUS_ACTIVE) { |
| 353 | if (loops == 0) { |
| 354 | retval = -ETIME; |
| 355 | goto done; |
| 356 | } |
| 357 | loops--; |
| 358 | udelay(LOOPS_USEC); |
| 359 | } |
| 360 | } |
| 361 | /* No other transfers on the queue */ |
| 362 | |
| 363 | /* Write dQH next pointer and terminate bit to 0 */ |
| 364 | dqh->next_dtd_ptr = req->head->td_dma |
| 365 | & EP_QUEUE_HEAD_NEXT_POINTER_MASK; |
| 366 | dqh->size_ioc_int_sts = 0; |
| 367 | |
| 368 | /* |
| 369 | * Ensure that updates to the QH will |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 370 | * occur before priming. |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 371 | */ |
| 372 | wmb(); |
| 373 | |
| 374 | /* Prime the Endpoint */ |
| 375 | writel(bit_pos, &udc->op_regs->epprime); |
| 376 | } |
| 377 | } else { |
| 378 | /* Write dQH next pointer and terminate bit to 0 */ |
| 379 | dqh->next_dtd_ptr = req->head->td_dma |
Justin P. Mattock | 6993248 | 2011-07-26 23:06:29 -0700 | [diff] [blame] | 380 | & EP_QUEUE_HEAD_NEXT_POINTER_MASK; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 381 | dqh->size_ioc_int_sts = 0; |
| 382 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 383 | /* Ensure that updates to the QH will occur before priming. */ |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 384 | wmb(); |
| 385 | |
| 386 | /* Prime the Endpoint */ |
| 387 | writel(bit_pos, &udc->op_regs->epprime); |
| 388 | |
| 389 | if (direction == EP_DIR_IN) { |
| 390 | /* FIXME add status check after prime the IN ep */ |
| 391 | int prime_again; |
| 392 | u32 curr_dtd_ptr = dqh->curr_dtd_ptr; |
| 393 | |
| 394 | loops = LOOPS(DTD_TIMEOUT); |
| 395 | prime_again = 0; |
| 396 | while ((curr_dtd_ptr != req->head->td_dma)) { |
| 397 | curr_dtd_ptr = dqh->curr_dtd_ptr; |
| 398 | if (loops == 0) { |
| 399 | dev_err(&udc->dev->dev, |
| 400 | "failed to prime %s\n", |
| 401 | ep->name); |
| 402 | retval = -ETIME; |
| 403 | goto done; |
| 404 | } |
| 405 | loops--; |
| 406 | udelay(LOOPS_USEC); |
| 407 | |
| 408 | if (loops == (LOOPS(DTD_TIMEOUT) >> 2)) { |
| 409 | if (prime_again) |
| 410 | goto done; |
| 411 | dev_info(&udc->dev->dev, |
| 412 | "prime again\n"); |
| 413 | writel(bit_pos, |
| 414 | &udc->op_regs->epprime); |
| 415 | prime_again = 1; |
| 416 | } |
| 417 | } |
| 418 | } |
| 419 | } |
| 420 | done: |
Justin P. Mattock | 6993248 | 2011-07-26 23:06:29 -0700 | [diff] [blame] | 421 | return retval; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 422 | } |
| 423 | |
| 424 | static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length, |
| 425 | dma_addr_t *dma, int *is_last) |
| 426 | { |
| 427 | u32 temp; |
| 428 | struct mv_dtd *dtd; |
| 429 | struct mv_udc *udc; |
| 430 | |
| 431 | /* how big will this transfer be? */ |
| 432 | *length = min(req->req.length - req->req.actual, |
| 433 | (unsigned)EP_MAX_LENGTH_TRANSFER); |
| 434 | |
| 435 | udc = req->ep->udc; |
| 436 | |
| 437 | /* |
| 438 | * Be careful that no _GFP_HIGHMEM is set, |
| 439 | * or we can not use dma_to_virt |
| 440 | */ |
| 441 | dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma); |
| 442 | if (dtd == NULL) |
| 443 | return dtd; |
| 444 | |
| 445 | dtd->td_dma = *dma; |
| 446 | /* initialize buffer page pointers */ |
| 447 | temp = (u32)(req->req.dma + req->req.actual); |
| 448 | dtd->buff_ptr0 = cpu_to_le32(temp); |
| 449 | temp &= ~0xFFF; |
| 450 | dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000); |
| 451 | dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000); |
| 452 | dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000); |
| 453 | dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000); |
| 454 | |
| 455 | req->req.actual += *length; |
| 456 | |
| 457 | /* zlp is needed if req->req.zero is set */ |
| 458 | if (req->req.zero) { |
| 459 | if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) |
| 460 | *is_last = 1; |
| 461 | else |
| 462 | *is_last = 0; |
| 463 | } else if (req->req.length == req->req.actual) |
| 464 | *is_last = 1; |
| 465 | else |
| 466 | *is_last = 0; |
| 467 | |
| 468 | /* Fill in the transfer size; set active bit */ |
| 469 | temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); |
| 470 | |
| 471 | /* Enable interrupt for the last dtd of a request */ |
| 472 | if (*is_last && !req->req.no_interrupt) |
| 473 | temp |= DTD_IOC; |
| 474 | |
| 475 | dtd->size_ioc_sts = temp; |
| 476 | |
| 477 | mb(); |
| 478 | |
| 479 | return dtd; |
| 480 | } |
| 481 | |
| 482 | /* generate dTD linked list for a request */ |
| 483 | static int req_to_dtd(struct mv_req *req) |
| 484 | { |
| 485 | unsigned count; |
| 486 | int is_last, is_first = 1; |
| 487 | struct mv_dtd *dtd, *last_dtd = NULL; |
| 488 | struct mv_udc *udc; |
| 489 | dma_addr_t dma; |
| 490 | |
| 491 | udc = req->ep->udc; |
| 492 | |
| 493 | do { |
| 494 | dtd = build_dtd(req, &count, &dma, &is_last); |
| 495 | if (dtd == NULL) |
| 496 | return -ENOMEM; |
| 497 | |
| 498 | if (is_first) { |
| 499 | is_first = 0; |
| 500 | req->head = dtd; |
| 501 | } else { |
| 502 | last_dtd->dtd_next = dma; |
| 503 | last_dtd->next_dtd_virt = dtd; |
| 504 | } |
| 505 | last_dtd = dtd; |
| 506 | req->dtd_count++; |
| 507 | } while (!is_last); |
| 508 | |
| 509 | /* set terminate bit to 1 for the last dTD */ |
| 510 | dtd->dtd_next = DTD_NEXT_TERMINATE; |
| 511 | |
| 512 | req->tail = dtd; |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
| 517 | static int mv_ep_enable(struct usb_ep *_ep, |
| 518 | const struct usb_endpoint_descriptor *desc) |
| 519 | { |
| 520 | struct mv_udc *udc; |
| 521 | struct mv_ep *ep; |
| 522 | struct mv_dqh *dqh; |
| 523 | u16 max = 0; |
| 524 | u32 bit_pos, epctrlx, direction; |
| 525 | unsigned char zlt = 0, ios = 0, mult = 0; |
Neil Zhang | 27cec2b | 2011-10-12 16:49:31 +0800 | [diff] [blame] | 526 | unsigned long flags; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 527 | |
| 528 | ep = container_of(_ep, struct mv_ep, ep); |
| 529 | udc = ep->udc; |
| 530 | |
| 531 | if (!_ep || !desc || ep->desc |
| 532 | || desc->bDescriptorType != USB_DT_ENDPOINT) |
| 533 | return -EINVAL; |
| 534 | |
| 535 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) |
| 536 | return -ESHUTDOWN; |
| 537 | |
| 538 | direction = ep_dir(ep); |
Kuninori Morimoto | 29cc889 | 2011-08-23 03:12:03 -0700 | [diff] [blame] | 539 | max = usb_endpoint_maxp(desc); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 540 | |
| 541 | /* |
| 542 | * disable HW zero length termination select |
| 543 | * driver handles zero length packet through req->req.zero |
| 544 | */ |
| 545 | zlt = 1; |
| 546 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 547 | bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num); |
| 548 | |
| 549 | /* Check if the Endpoint is Primed */ |
| 550 | if ((readl(&udc->op_regs->epprime) & bit_pos) |
| 551 | || (readl(&udc->op_regs->epstatus) & bit_pos)) { |
| 552 | dev_info(&udc->dev->dev, |
| 553 | "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x," |
| 554 | " ENDPTSTATUS=0x%x, bit_pos=0x%x\n", |
| 555 | (unsigned)ep->ep_num, direction ? "SEND" : "RECV", |
| 556 | (unsigned)readl(&udc->op_regs->epprime), |
| 557 | (unsigned)readl(&udc->op_regs->epstatus), |
| 558 | (unsigned)bit_pos); |
| 559 | goto en_done; |
| 560 | } |
| 561 | /* Set the max packet length, interrupt on Setup and Mult fields */ |
| 562 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
| 563 | case USB_ENDPOINT_XFER_BULK: |
| 564 | zlt = 1; |
| 565 | mult = 0; |
| 566 | break; |
| 567 | case USB_ENDPOINT_XFER_CONTROL: |
| 568 | ios = 1; |
| 569 | case USB_ENDPOINT_XFER_INT: |
| 570 | mult = 0; |
| 571 | break; |
| 572 | case USB_ENDPOINT_XFER_ISOC: |
| 573 | /* Calculate transactions needed for high bandwidth iso */ |
| 574 | mult = (unsigned char)(1 + ((max >> 11) & 0x03)); |
Neil Zhang | bedcff9 | 2011-10-12 16:49:27 +0800 | [diff] [blame] | 575 | max = max & 0x7ff; /* bit 0~10 */ |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 576 | /* 3 transactions at most */ |
| 577 | if (mult > 3) |
| 578 | goto en_done; |
| 579 | break; |
| 580 | default: |
| 581 | goto en_done; |
| 582 | } |
Neil Zhang | 27cec2b | 2011-10-12 16:49:31 +0800 | [diff] [blame] | 583 | |
| 584 | spin_lock_irqsave(&udc->lock, flags); |
| 585 | /* Get the endpoint queue head address */ |
| 586 | dqh = ep->dqh; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 587 | dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) |
| 588 | | (mult << EP_QUEUE_HEAD_MULT_POS) |
| 589 | | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0) |
| 590 | | (ios ? EP_QUEUE_HEAD_IOS : 0); |
| 591 | dqh->next_dtd_ptr = 1; |
| 592 | dqh->size_ioc_int_sts = 0; |
| 593 | |
| 594 | ep->ep.maxpacket = max; |
| 595 | ep->desc = desc; |
| 596 | ep->stopped = 0; |
| 597 | |
| 598 | /* Enable the endpoint for Rx or Tx and set the endpoint type */ |
| 599 | epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); |
| 600 | if (direction == EP_DIR_IN) { |
| 601 | epctrlx &= ~EPCTRL_TX_ALL_MASK; |
| 602 | epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST |
| 603 | | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) |
| 604 | << EPCTRL_TX_EP_TYPE_SHIFT); |
| 605 | } else { |
| 606 | epctrlx &= ~EPCTRL_RX_ALL_MASK; |
| 607 | epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST |
| 608 | | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) |
| 609 | << EPCTRL_RX_EP_TYPE_SHIFT); |
| 610 | } |
| 611 | writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); |
| 612 | |
| 613 | /* |
| 614 | * Implement Guideline (GL# USB-7) The unused endpoint type must |
| 615 | * be programmed to bulk. |
| 616 | */ |
| 617 | epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); |
| 618 | if ((epctrlx & EPCTRL_RX_ENABLE) == 0) { |
Neil Zhang | 615268b | 2011-10-12 16:49:32 +0800 | [diff] [blame] | 619 | epctrlx |= (USB_ENDPOINT_XFER_BULK |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 620 | << EPCTRL_RX_EP_TYPE_SHIFT); |
| 621 | writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); |
| 622 | } |
| 623 | |
| 624 | epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); |
| 625 | if ((epctrlx & EPCTRL_TX_ENABLE) == 0) { |
Neil Zhang | 615268b | 2011-10-12 16:49:32 +0800 | [diff] [blame] | 626 | epctrlx |= (USB_ENDPOINT_XFER_BULK |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 627 | << EPCTRL_TX_EP_TYPE_SHIFT); |
| 628 | writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); |
| 629 | } |
| 630 | |
Neil Zhang | 27cec2b | 2011-10-12 16:49:31 +0800 | [diff] [blame] | 631 | spin_unlock_irqrestore(&udc->lock, flags); |
| 632 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 633 | return 0; |
| 634 | en_done: |
| 635 | return -EINVAL; |
| 636 | } |
| 637 | |
| 638 | static int mv_ep_disable(struct usb_ep *_ep) |
| 639 | { |
| 640 | struct mv_udc *udc; |
| 641 | struct mv_ep *ep; |
| 642 | struct mv_dqh *dqh; |
| 643 | u32 bit_pos, epctrlx, direction; |
Neil Zhang | 27cec2b | 2011-10-12 16:49:31 +0800 | [diff] [blame] | 644 | unsigned long flags; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 645 | |
| 646 | ep = container_of(_ep, struct mv_ep, ep); |
| 647 | if ((_ep == NULL) || !ep->desc) |
| 648 | return -EINVAL; |
| 649 | |
| 650 | udc = ep->udc; |
| 651 | |
| 652 | /* Get the endpoint queue head address */ |
| 653 | dqh = ep->dqh; |
| 654 | |
Neil Zhang | 27cec2b | 2011-10-12 16:49:31 +0800 | [diff] [blame] | 655 | spin_lock_irqsave(&udc->lock, flags); |
| 656 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 657 | direction = ep_dir(ep); |
| 658 | bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num); |
| 659 | |
| 660 | /* Reset the max packet length and the interrupt on Setup */ |
| 661 | dqh->max_packet_length = 0; |
| 662 | |
| 663 | /* Disable the endpoint for Rx or Tx and reset the endpoint type */ |
| 664 | epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); |
| 665 | epctrlx &= ~((direction == EP_DIR_IN) |
| 666 | ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE) |
| 667 | : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE)); |
| 668 | writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); |
| 669 | |
| 670 | /* nuke all pending requests (does flush) */ |
| 671 | nuke(ep, -ESHUTDOWN); |
| 672 | |
| 673 | ep->desc = NULL; |
| 674 | ep->stopped = 1; |
Neil Zhang | 27cec2b | 2011-10-12 16:49:31 +0800 | [diff] [blame] | 675 | |
| 676 | spin_unlock_irqrestore(&udc->lock, flags); |
| 677 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 678 | return 0; |
| 679 | } |
| 680 | |
| 681 | static struct usb_request * |
| 682 | mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) |
| 683 | { |
| 684 | struct mv_req *req = NULL; |
| 685 | |
| 686 | req = kzalloc(sizeof *req, gfp_flags); |
| 687 | if (!req) |
| 688 | return NULL; |
| 689 | |
| 690 | req->req.dma = DMA_ADDR_INVALID; |
| 691 | INIT_LIST_HEAD(&req->queue); |
| 692 | |
| 693 | return &req->req; |
| 694 | } |
| 695 | |
| 696 | static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req) |
| 697 | { |
| 698 | struct mv_req *req = NULL; |
| 699 | |
| 700 | req = container_of(_req, struct mv_req, req); |
| 701 | |
| 702 | if (_req) |
| 703 | kfree(req); |
| 704 | } |
| 705 | |
| 706 | static void mv_ep_fifo_flush(struct usb_ep *_ep) |
| 707 | { |
| 708 | struct mv_udc *udc; |
| 709 | u32 bit_pos, direction; |
Neil Zhang | 0c70840 | 2011-10-12 16:49:33 +0800 | [diff] [blame] | 710 | struct mv_ep *ep; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 711 | unsigned int loops; |
| 712 | |
Neil Zhang | 0c70840 | 2011-10-12 16:49:33 +0800 | [diff] [blame] | 713 | if (!_ep) |
| 714 | return; |
| 715 | |
| 716 | ep = container_of(_ep, struct mv_ep, ep); |
| 717 | if (!ep->desc) |
| 718 | return; |
| 719 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 720 | udc = ep->udc; |
| 721 | direction = ep_dir(ep); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 722 | |
Neil Zhang | 0c70840 | 2011-10-12 16:49:33 +0800 | [diff] [blame] | 723 | if (ep->ep_num == 0) |
| 724 | bit_pos = (1 << 16) | 1; |
| 725 | else if (direction == EP_DIR_OUT) |
| 726 | bit_pos = 1 << ep->ep_num; |
| 727 | else |
| 728 | bit_pos = 1 << (16 + ep->ep_num); |
| 729 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 730 | loops = LOOPS(EPSTATUS_TIMEOUT); |
Neil Zhang | 0c70840 | 2011-10-12 16:49:33 +0800 | [diff] [blame] | 731 | do { |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 732 | unsigned int inter_loops; |
| 733 | |
| 734 | if (loops == 0) { |
| 735 | dev_err(&udc->dev->dev, |
| 736 | "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n", |
| 737 | (unsigned)readl(&udc->op_regs->epstatus), |
| 738 | (unsigned)bit_pos); |
| 739 | return; |
| 740 | } |
| 741 | /* Write 1 to the Flush register */ |
| 742 | writel(bit_pos, &udc->op_regs->epflush); |
| 743 | |
| 744 | /* Wait until flushing completed */ |
| 745 | inter_loops = LOOPS(FLUSH_TIMEOUT); |
Neil Zhang | 0c70840 | 2011-10-12 16:49:33 +0800 | [diff] [blame] | 746 | while (readl(&udc->op_regs->epflush)) { |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 747 | /* |
| 748 | * ENDPTFLUSH bit should be cleared to indicate this |
| 749 | * operation is complete |
| 750 | */ |
| 751 | if (inter_loops == 0) { |
| 752 | dev_err(&udc->dev->dev, |
| 753 | "TIMEOUT for ENDPTFLUSH=0x%x," |
| 754 | "bit_pos=0x%x\n", |
| 755 | (unsigned)readl(&udc->op_regs->epflush), |
| 756 | (unsigned)bit_pos); |
| 757 | return; |
| 758 | } |
| 759 | inter_loops--; |
| 760 | udelay(LOOPS_USEC); |
| 761 | } |
| 762 | loops--; |
Neil Zhang | 0c70840 | 2011-10-12 16:49:33 +0800 | [diff] [blame] | 763 | } while (readl(&udc->op_regs->epstatus) & bit_pos); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 764 | } |
| 765 | |
| 766 | /* queues (submits) an I/O request to an endpoint */ |
| 767 | static int |
| 768 | mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
| 769 | { |
| 770 | struct mv_ep *ep = container_of(_ep, struct mv_ep, ep); |
| 771 | struct mv_req *req = container_of(_req, struct mv_req, req); |
| 772 | struct mv_udc *udc = ep->udc; |
| 773 | unsigned long flags; |
| 774 | |
| 775 | /* catch various bogus parameters */ |
| 776 | if (!_req || !req->req.complete || !req->req.buf |
| 777 | || !list_empty(&req->queue)) { |
| 778 | dev_err(&udc->dev->dev, "%s, bad params", __func__); |
| 779 | return -EINVAL; |
| 780 | } |
| 781 | if (unlikely(!_ep || !ep->desc)) { |
| 782 | dev_err(&udc->dev->dev, "%s, bad ep", __func__); |
| 783 | return -EINVAL; |
| 784 | } |
| 785 | if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { |
| 786 | if (req->req.length > ep->ep.maxpacket) |
| 787 | return -EMSGSIZE; |
| 788 | } |
| 789 | |
| 790 | udc = ep->udc; |
| 791 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) |
| 792 | return -ESHUTDOWN; |
| 793 | |
| 794 | req->ep = ep; |
| 795 | |
| 796 | /* map virtual address to hardware */ |
| 797 | if (req->req.dma == DMA_ADDR_INVALID) { |
| 798 | req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, |
| 799 | req->req.buf, |
| 800 | req->req.length, ep_dir(ep) |
| 801 | ? DMA_TO_DEVICE |
| 802 | : DMA_FROM_DEVICE); |
| 803 | req->mapped = 1; |
| 804 | } else { |
| 805 | dma_sync_single_for_device(ep->udc->gadget.dev.parent, |
| 806 | req->req.dma, req->req.length, |
| 807 | ep_dir(ep) |
| 808 | ? DMA_TO_DEVICE |
| 809 | : DMA_FROM_DEVICE); |
| 810 | req->mapped = 0; |
| 811 | } |
| 812 | |
| 813 | req->req.status = -EINPROGRESS; |
| 814 | req->req.actual = 0; |
| 815 | req->dtd_count = 0; |
| 816 | |
| 817 | spin_lock_irqsave(&udc->lock, flags); |
| 818 | |
| 819 | /* build dtds and push them to device queue */ |
| 820 | if (!req_to_dtd(req)) { |
| 821 | int retval; |
| 822 | retval = queue_dtd(ep, req); |
| 823 | if (retval) { |
| 824 | spin_unlock_irqrestore(&udc->lock, flags); |
| 825 | return retval; |
| 826 | } |
| 827 | } else { |
| 828 | spin_unlock_irqrestore(&udc->lock, flags); |
| 829 | return -ENOMEM; |
| 830 | } |
| 831 | |
| 832 | /* Update ep0 state */ |
| 833 | if (ep->ep_num == 0) |
| 834 | udc->ep0_state = DATA_STATE_XMIT; |
| 835 | |
| 836 | /* irq handler advances the queue */ |
| 837 | if (req != NULL) |
| 838 | list_add_tail(&req->queue, &ep->queue); |
| 839 | spin_unlock_irqrestore(&udc->lock, flags); |
| 840 | |
| 841 | return 0; |
| 842 | } |
| 843 | |
| 844 | /* dequeues (cancels, unlinks) an I/O request from an endpoint */ |
| 845 | static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
| 846 | { |
| 847 | struct mv_ep *ep = container_of(_ep, struct mv_ep, ep); |
| 848 | struct mv_req *req; |
| 849 | struct mv_udc *udc = ep->udc; |
| 850 | unsigned long flags; |
| 851 | int stopped, ret = 0; |
| 852 | u32 epctrlx; |
| 853 | |
| 854 | if (!_ep || !_req) |
| 855 | return -EINVAL; |
| 856 | |
| 857 | spin_lock_irqsave(&ep->udc->lock, flags); |
| 858 | stopped = ep->stopped; |
| 859 | |
| 860 | /* Stop the ep before we deal with the queue */ |
| 861 | ep->stopped = 1; |
| 862 | epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); |
| 863 | if (ep_dir(ep) == EP_DIR_IN) |
| 864 | epctrlx &= ~EPCTRL_TX_ENABLE; |
| 865 | else |
| 866 | epctrlx &= ~EPCTRL_RX_ENABLE; |
| 867 | writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); |
| 868 | |
| 869 | /* make sure it's actually queued on this endpoint */ |
| 870 | list_for_each_entry(req, &ep->queue, queue) { |
| 871 | if (&req->req == _req) |
| 872 | break; |
| 873 | } |
| 874 | if (&req->req != _req) { |
| 875 | ret = -EINVAL; |
| 876 | goto out; |
| 877 | } |
| 878 | |
| 879 | /* The request is in progress, or completed but not dequeued */ |
| 880 | if (ep->queue.next == &req->queue) { |
| 881 | _req->status = -ECONNRESET; |
| 882 | mv_ep_fifo_flush(_ep); /* flush current transfer */ |
| 883 | |
| 884 | /* The request isn't the last request in this ep queue */ |
| 885 | if (req->queue.next != &ep->queue) { |
| 886 | struct mv_dqh *qh; |
| 887 | struct mv_req *next_req; |
| 888 | |
| 889 | qh = ep->dqh; |
| 890 | next_req = list_entry(req->queue.next, struct mv_req, |
| 891 | queue); |
| 892 | |
| 893 | /* Point the QH to the first TD of next request */ |
| 894 | writel((u32) next_req->head, &qh->curr_dtd_ptr); |
| 895 | } else { |
| 896 | struct mv_dqh *qh; |
| 897 | |
| 898 | qh = ep->dqh; |
| 899 | qh->next_dtd_ptr = 1; |
| 900 | qh->size_ioc_int_sts = 0; |
| 901 | } |
| 902 | |
| 903 | /* The request hasn't been processed, patch up the TD chain */ |
| 904 | } else { |
| 905 | struct mv_req *prev_req; |
| 906 | |
| 907 | prev_req = list_entry(req->queue.prev, struct mv_req, queue); |
| 908 | writel(readl(&req->tail->dtd_next), |
| 909 | &prev_req->tail->dtd_next); |
| 910 | |
| 911 | } |
| 912 | |
| 913 | done(ep, req, -ECONNRESET); |
| 914 | |
| 915 | /* Enable EP */ |
| 916 | out: |
| 917 | epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]); |
| 918 | if (ep_dir(ep) == EP_DIR_IN) |
| 919 | epctrlx |= EPCTRL_TX_ENABLE; |
| 920 | else |
| 921 | epctrlx |= EPCTRL_RX_ENABLE; |
| 922 | writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); |
| 923 | ep->stopped = stopped; |
| 924 | |
| 925 | spin_unlock_irqrestore(&ep->udc->lock, flags); |
| 926 | return ret; |
| 927 | } |
| 928 | |
| 929 | static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall) |
| 930 | { |
| 931 | u32 epctrlx; |
| 932 | |
| 933 | epctrlx = readl(&udc->op_regs->epctrlx[ep_num]); |
| 934 | |
| 935 | if (stall) { |
| 936 | if (direction == EP_DIR_IN) |
| 937 | epctrlx |= EPCTRL_TX_EP_STALL; |
| 938 | else |
| 939 | epctrlx |= EPCTRL_RX_EP_STALL; |
| 940 | } else { |
| 941 | if (direction == EP_DIR_IN) { |
| 942 | epctrlx &= ~EPCTRL_TX_EP_STALL; |
| 943 | epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST; |
| 944 | } else { |
| 945 | epctrlx &= ~EPCTRL_RX_EP_STALL; |
| 946 | epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST; |
| 947 | } |
| 948 | } |
| 949 | writel(epctrlx, &udc->op_regs->epctrlx[ep_num]); |
| 950 | } |
| 951 | |
| 952 | static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction) |
| 953 | { |
| 954 | u32 epctrlx; |
| 955 | |
| 956 | epctrlx = readl(&udc->op_regs->epctrlx[ep_num]); |
| 957 | |
| 958 | if (direction == EP_DIR_OUT) |
| 959 | return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0; |
| 960 | else |
| 961 | return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0; |
| 962 | } |
| 963 | |
| 964 | static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge) |
| 965 | { |
| 966 | struct mv_ep *ep; |
| 967 | unsigned long flags = 0; |
| 968 | int status = 0; |
| 969 | struct mv_udc *udc; |
| 970 | |
| 971 | ep = container_of(_ep, struct mv_ep, ep); |
| 972 | udc = ep->udc; |
| 973 | if (!_ep || !ep->desc) { |
| 974 | status = -EINVAL; |
| 975 | goto out; |
| 976 | } |
| 977 | |
| 978 | if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { |
| 979 | status = -EOPNOTSUPP; |
| 980 | goto out; |
| 981 | } |
| 982 | |
| 983 | /* |
| 984 | * Attempt to halt IN ep will fail if any transfer requests |
| 985 | * are still queue |
| 986 | */ |
| 987 | if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) { |
| 988 | status = -EAGAIN; |
| 989 | goto out; |
| 990 | } |
| 991 | |
| 992 | spin_lock_irqsave(&ep->udc->lock, flags); |
| 993 | ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt); |
| 994 | if (halt && wedge) |
| 995 | ep->wedge = 1; |
| 996 | else if (!halt) |
| 997 | ep->wedge = 0; |
| 998 | spin_unlock_irqrestore(&ep->udc->lock, flags); |
| 999 | |
| 1000 | if (ep->ep_num == 0) { |
| 1001 | udc->ep0_state = WAIT_FOR_SETUP; |
| 1002 | udc->ep0_dir = EP_DIR_OUT; |
| 1003 | } |
| 1004 | out: |
| 1005 | return status; |
| 1006 | } |
| 1007 | |
| 1008 | static int mv_ep_set_halt(struct usb_ep *_ep, int halt) |
| 1009 | { |
| 1010 | return mv_ep_set_halt_wedge(_ep, halt, 0); |
| 1011 | } |
| 1012 | |
| 1013 | static int mv_ep_set_wedge(struct usb_ep *_ep) |
| 1014 | { |
| 1015 | return mv_ep_set_halt_wedge(_ep, 1, 1); |
| 1016 | } |
| 1017 | |
| 1018 | static struct usb_ep_ops mv_ep_ops = { |
| 1019 | .enable = mv_ep_enable, |
| 1020 | .disable = mv_ep_disable, |
| 1021 | |
| 1022 | .alloc_request = mv_alloc_request, |
| 1023 | .free_request = mv_free_request, |
| 1024 | |
| 1025 | .queue = mv_ep_queue, |
| 1026 | .dequeue = mv_ep_dequeue, |
| 1027 | |
| 1028 | .set_wedge = mv_ep_set_wedge, |
| 1029 | .set_halt = mv_ep_set_halt, |
| 1030 | .fifo_flush = mv_ep_fifo_flush, /* flush fifo */ |
| 1031 | }; |
| 1032 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 1033 | static void udc_clock_enable(struct mv_udc *udc) |
| 1034 | { |
| 1035 | unsigned int i; |
| 1036 | |
| 1037 | for (i = 0; i < udc->clknum; i++) |
| 1038 | clk_enable(udc->clk[i]); |
| 1039 | } |
| 1040 | |
| 1041 | static void udc_clock_disable(struct mv_udc *udc) |
| 1042 | { |
| 1043 | unsigned int i; |
| 1044 | |
| 1045 | for (i = 0; i < udc->clknum; i++) |
| 1046 | clk_disable(udc->clk[i]); |
| 1047 | } |
| 1048 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1049 | static void udc_stop(struct mv_udc *udc) |
| 1050 | { |
| 1051 | u32 tmp; |
| 1052 | |
| 1053 | /* Disable interrupts */ |
| 1054 | tmp = readl(&udc->op_regs->usbintr); |
| 1055 | tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN | |
| 1056 | USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN); |
| 1057 | writel(tmp, &udc->op_regs->usbintr); |
| 1058 | |
| 1059 | /* Reset the Run the bit in the command register to stop VUSB */ |
| 1060 | tmp = readl(&udc->op_regs->usbcmd); |
| 1061 | tmp &= ~USBCMD_RUN_STOP; |
| 1062 | writel(tmp, &udc->op_regs->usbcmd); |
| 1063 | } |
| 1064 | |
| 1065 | static void udc_start(struct mv_udc *udc) |
| 1066 | { |
| 1067 | u32 usbintr; |
| 1068 | |
| 1069 | usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN |
| 1070 | | USBINTR_PORT_CHANGE_DETECT_EN |
| 1071 | | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND; |
| 1072 | /* Enable interrupts */ |
| 1073 | writel(usbintr, &udc->op_regs->usbintr); |
| 1074 | |
| 1075 | /* Set the Run bit in the command register */ |
| 1076 | writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd); |
| 1077 | } |
| 1078 | |
| 1079 | static int udc_reset(struct mv_udc *udc) |
| 1080 | { |
| 1081 | unsigned int loops; |
| 1082 | u32 tmp, portsc; |
| 1083 | |
| 1084 | /* Stop the controller */ |
| 1085 | tmp = readl(&udc->op_regs->usbcmd); |
| 1086 | tmp &= ~USBCMD_RUN_STOP; |
| 1087 | writel(tmp, &udc->op_regs->usbcmd); |
| 1088 | |
| 1089 | /* Reset the controller to get default values */ |
| 1090 | writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd); |
| 1091 | |
| 1092 | /* wait for reset to complete */ |
| 1093 | loops = LOOPS(RESET_TIMEOUT); |
| 1094 | while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) { |
| 1095 | if (loops == 0) { |
| 1096 | dev_err(&udc->dev->dev, |
| 1097 | "Wait for RESET completed TIMEOUT\n"); |
| 1098 | return -ETIMEDOUT; |
| 1099 | } |
| 1100 | loops--; |
| 1101 | udelay(LOOPS_USEC); |
| 1102 | } |
| 1103 | |
| 1104 | /* set controller to device mode */ |
| 1105 | tmp = readl(&udc->op_regs->usbmode); |
| 1106 | tmp |= USBMODE_CTRL_MODE_DEVICE; |
| 1107 | |
| 1108 | /* turn setup lockout off, require setup tripwire in usbcmd */ |
| 1109 | tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE; |
| 1110 | |
| 1111 | writel(tmp, &udc->op_regs->usbmode); |
| 1112 | |
| 1113 | writel(0x0, &udc->op_regs->epsetupstat); |
| 1114 | |
| 1115 | /* Configure the Endpoint List Address */ |
| 1116 | writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK, |
| 1117 | &udc->op_regs->eplistaddr); |
| 1118 | |
| 1119 | portsc = readl(&udc->op_regs->portsc[0]); |
| 1120 | if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC) |
| 1121 | portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER); |
| 1122 | |
| 1123 | if (udc->force_fs) |
| 1124 | portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT; |
| 1125 | else |
| 1126 | portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT); |
| 1127 | |
| 1128 | writel(portsc, &udc->op_regs->portsc[0]); |
| 1129 | |
| 1130 | tmp = readl(&udc->op_regs->epctrlx[0]); |
| 1131 | tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL); |
| 1132 | writel(tmp, &udc->op_regs->epctrlx[0]); |
| 1133 | |
| 1134 | return 0; |
| 1135 | } |
| 1136 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1137 | static int mv_udc_enable(struct mv_udc *udc) |
| 1138 | { |
| 1139 | int retval; |
| 1140 | |
| 1141 | if (udc->clock_gating == 0 || udc->active) |
| 1142 | return 0; |
| 1143 | |
| 1144 | dev_dbg(&udc->dev->dev, "enable udc\n"); |
| 1145 | udc_clock_enable(udc); |
| 1146 | if (udc->pdata->phy_init) { |
| 1147 | retval = udc->pdata->phy_init(udc->phy_regs); |
| 1148 | if (retval) { |
| 1149 | dev_err(&udc->dev->dev, |
| 1150 | "init phy error %d\n", retval); |
| 1151 | udc_clock_disable(udc); |
| 1152 | return retval; |
| 1153 | } |
| 1154 | } |
| 1155 | udc->active = 1; |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
| 1160 | static void mv_udc_disable(struct mv_udc *udc) |
| 1161 | { |
| 1162 | if (udc->clock_gating && udc->active) { |
| 1163 | dev_dbg(&udc->dev->dev, "disable udc\n"); |
| 1164 | if (udc->pdata->phy_deinit) |
| 1165 | udc->pdata->phy_deinit(udc->phy_regs); |
| 1166 | udc_clock_disable(udc); |
| 1167 | udc->active = 0; |
| 1168 | } |
| 1169 | } |
| 1170 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1171 | static int mv_udc_get_frame(struct usb_gadget *gadget) |
| 1172 | { |
| 1173 | struct mv_udc *udc; |
| 1174 | u16 retval; |
| 1175 | |
| 1176 | if (!gadget) |
| 1177 | return -ENODEV; |
| 1178 | |
| 1179 | udc = container_of(gadget, struct mv_udc, gadget); |
| 1180 | |
| 1181 | retval = readl(udc->op_regs->frindex) & USB_FRINDEX_MASKS; |
| 1182 | |
| 1183 | return retval; |
| 1184 | } |
| 1185 | |
| 1186 | /* Tries to wake up the host connected to this gadget */ |
| 1187 | static int mv_udc_wakeup(struct usb_gadget *gadget) |
| 1188 | { |
| 1189 | struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget); |
| 1190 | u32 portsc; |
| 1191 | |
| 1192 | /* Remote wakeup feature not enabled by host */ |
| 1193 | if (!udc->remote_wakeup) |
| 1194 | return -ENOTSUPP; |
| 1195 | |
| 1196 | portsc = readl(&udc->op_regs->portsc); |
| 1197 | /* not suspended? */ |
| 1198 | if (!(portsc & PORTSCX_PORT_SUSPEND)) |
| 1199 | return 0; |
| 1200 | /* trigger force resume */ |
| 1201 | portsc |= PORTSCX_PORT_FORCE_RESUME; |
| 1202 | writel(portsc, &udc->op_regs->portsc[0]); |
| 1203 | return 0; |
| 1204 | } |
| 1205 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1206 | static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active) |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1207 | { |
| 1208 | struct mv_udc *udc; |
| 1209 | unsigned long flags; |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1210 | int retval = 0; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1211 | |
| 1212 | udc = container_of(gadget, struct mv_udc, gadget); |
| 1213 | spin_lock_irqsave(&udc->lock, flags); |
| 1214 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1215 | dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n", |
| 1216 | __func__, udc->softconnect, udc->vbus_active); |
| 1217 | |
| 1218 | udc->vbus_active = (is_active != 0); |
| 1219 | if (udc->driver && udc->softconnect && udc->vbus_active) { |
| 1220 | retval = mv_udc_enable(udc); |
| 1221 | if (retval == 0) { |
| 1222 | /* Clock is disabled, need re-init registers */ |
| 1223 | udc_reset(udc); |
| 1224 | ep0_reset(udc); |
| 1225 | udc_start(udc); |
| 1226 | } |
| 1227 | } else if (udc->driver && udc->softconnect) { |
| 1228 | /* stop all the transfer in queue*/ |
| 1229 | stop_activity(udc, udc->driver); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1230 | udc_stop(udc); |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1231 | mv_udc_disable(udc); |
| 1232 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1233 | |
| 1234 | spin_unlock_irqrestore(&udc->lock, flags); |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1235 | return retval; |
| 1236 | } |
| 1237 | |
| 1238 | static int mv_udc_pullup(struct usb_gadget *gadget, int is_on) |
| 1239 | { |
| 1240 | struct mv_udc *udc; |
| 1241 | unsigned long flags; |
| 1242 | int retval = 0; |
| 1243 | |
| 1244 | udc = container_of(gadget, struct mv_udc, gadget); |
| 1245 | spin_lock_irqsave(&udc->lock, flags); |
| 1246 | |
| 1247 | dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n", |
| 1248 | __func__, udc->softconnect, udc->vbus_active); |
| 1249 | |
| 1250 | udc->softconnect = (is_on != 0); |
| 1251 | if (udc->driver && udc->softconnect && udc->vbus_active) { |
| 1252 | retval = mv_udc_enable(udc); |
| 1253 | if (retval == 0) { |
| 1254 | /* Clock is disabled, need re-init registers */ |
| 1255 | udc_reset(udc); |
| 1256 | ep0_reset(udc); |
| 1257 | udc_start(udc); |
| 1258 | } |
| 1259 | } else if (udc->driver && udc->vbus_active) { |
| 1260 | /* stop all the transfer in queue*/ |
| 1261 | stop_activity(udc, udc->driver); |
| 1262 | udc_stop(udc); |
| 1263 | mv_udc_disable(udc); |
| 1264 | } |
| 1265 | |
| 1266 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1267 | return retval; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1268 | } |
| 1269 | |
Sebastian Andrzej Siewior | 0f91349 | 2011-06-28 16:33:47 +0300 | [diff] [blame] | 1270 | static int mv_udc_start(struct usb_gadget_driver *driver, |
| 1271 | int (*bind)(struct usb_gadget *)); |
| 1272 | static int mv_udc_stop(struct usb_gadget_driver *driver); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1273 | /* device controller usb_gadget_ops structure */ |
| 1274 | static const struct usb_gadget_ops mv_ops = { |
| 1275 | |
| 1276 | /* returns the current frame number */ |
| 1277 | .get_frame = mv_udc_get_frame, |
| 1278 | |
| 1279 | /* tries to wake up the host connected to this gadget */ |
| 1280 | .wakeup = mv_udc_wakeup, |
| 1281 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1282 | /* notify controller that VBUS is powered or not */ |
| 1283 | .vbus_session = mv_udc_vbus_session, |
| 1284 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1285 | /* D+ pullup, software-controlled connect/disconnect to USB host */ |
| 1286 | .pullup = mv_udc_pullup, |
Sebastian Andrzej Siewior | 0f91349 | 2011-06-28 16:33:47 +0300 | [diff] [blame] | 1287 | .start = mv_udc_start, |
| 1288 | .stop = mv_udc_stop, |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1289 | }; |
| 1290 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1291 | static int eps_init(struct mv_udc *udc) |
| 1292 | { |
| 1293 | struct mv_ep *ep; |
| 1294 | char name[14]; |
| 1295 | int i; |
| 1296 | |
| 1297 | /* initialize ep0 */ |
| 1298 | ep = &udc->eps[0]; |
| 1299 | ep->udc = udc; |
| 1300 | strncpy(ep->name, "ep0", sizeof(ep->name)); |
| 1301 | ep->ep.name = ep->name; |
| 1302 | ep->ep.ops = &mv_ep_ops; |
| 1303 | ep->wedge = 0; |
| 1304 | ep->stopped = 0; |
| 1305 | ep->ep.maxpacket = EP0_MAX_PKT_SIZE; |
| 1306 | ep->ep_num = 0; |
| 1307 | ep->desc = &mv_ep0_desc; |
| 1308 | INIT_LIST_HEAD(&ep->queue); |
| 1309 | |
| 1310 | ep->ep_type = USB_ENDPOINT_XFER_CONTROL; |
| 1311 | |
| 1312 | /* initialize other endpoints */ |
| 1313 | for (i = 2; i < udc->max_eps * 2; i++) { |
| 1314 | ep = &udc->eps[i]; |
| 1315 | if (i % 2) { |
| 1316 | snprintf(name, sizeof(name), "ep%din", i / 2); |
| 1317 | ep->direction = EP_DIR_IN; |
| 1318 | } else { |
| 1319 | snprintf(name, sizeof(name), "ep%dout", i / 2); |
| 1320 | ep->direction = EP_DIR_OUT; |
| 1321 | } |
| 1322 | ep->udc = udc; |
| 1323 | strncpy(ep->name, name, sizeof(ep->name)); |
| 1324 | ep->ep.name = ep->name; |
| 1325 | |
| 1326 | ep->ep.ops = &mv_ep_ops; |
| 1327 | ep->stopped = 0; |
| 1328 | ep->ep.maxpacket = (unsigned short) ~0; |
| 1329 | ep->ep_num = i / 2; |
| 1330 | |
| 1331 | INIT_LIST_HEAD(&ep->queue); |
| 1332 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); |
| 1333 | |
| 1334 | ep->dqh = &udc->ep_dqh[i]; |
| 1335 | } |
| 1336 | |
| 1337 | return 0; |
| 1338 | } |
| 1339 | |
| 1340 | /* delete all endpoint requests, called with spinlock held */ |
| 1341 | static void nuke(struct mv_ep *ep, int status) |
| 1342 | { |
| 1343 | /* called with spinlock held */ |
| 1344 | ep->stopped = 1; |
| 1345 | |
| 1346 | /* endpoint fifo flush */ |
| 1347 | mv_ep_fifo_flush(&ep->ep); |
| 1348 | |
| 1349 | while (!list_empty(&ep->queue)) { |
| 1350 | struct mv_req *req = NULL; |
| 1351 | req = list_entry(ep->queue.next, struct mv_req, queue); |
| 1352 | done(ep, req, status); |
| 1353 | } |
| 1354 | } |
| 1355 | |
| 1356 | /* stop all USB activities */ |
| 1357 | static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver) |
| 1358 | { |
| 1359 | struct mv_ep *ep; |
| 1360 | |
| 1361 | nuke(&udc->eps[0], -ESHUTDOWN); |
| 1362 | |
| 1363 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { |
| 1364 | nuke(ep, -ESHUTDOWN); |
| 1365 | } |
| 1366 | |
| 1367 | /* report disconnect; the driver is already quiesced */ |
| 1368 | if (driver) { |
| 1369 | spin_unlock(&udc->lock); |
| 1370 | driver->disconnect(&udc->gadget); |
| 1371 | spin_lock(&udc->lock); |
| 1372 | } |
| 1373 | } |
| 1374 | |
Sebastian Andrzej Siewior | 0f91349 | 2011-06-28 16:33:47 +0300 | [diff] [blame] | 1375 | static int mv_udc_start(struct usb_gadget_driver *driver, |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1376 | int (*bind)(struct usb_gadget *)) |
| 1377 | { |
| 1378 | struct mv_udc *udc = the_controller; |
| 1379 | int retval = 0; |
| 1380 | unsigned long flags; |
| 1381 | |
| 1382 | if (!udc) |
| 1383 | return -ENODEV; |
| 1384 | |
| 1385 | if (udc->driver) |
| 1386 | return -EBUSY; |
| 1387 | |
| 1388 | spin_lock_irqsave(&udc->lock, flags); |
| 1389 | |
| 1390 | /* hook up the driver ... */ |
| 1391 | driver->driver.bus = NULL; |
| 1392 | udc->driver = driver; |
| 1393 | udc->gadget.dev.driver = &driver->driver; |
| 1394 | |
| 1395 | udc->usb_state = USB_STATE_ATTACHED; |
| 1396 | udc->ep0_state = WAIT_FOR_SETUP; |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1397 | udc->ep0_dir = EP_DIR_OUT; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1398 | |
| 1399 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1400 | |
| 1401 | retval = bind(&udc->gadget); |
| 1402 | if (retval) { |
| 1403 | dev_err(&udc->dev->dev, "bind to driver %s --> %d\n", |
| 1404 | driver->driver.name, retval); |
| 1405 | udc->driver = NULL; |
| 1406 | udc->gadget.dev.driver = NULL; |
| 1407 | return retval; |
| 1408 | } |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1409 | |
| 1410 | /* pullup is always on */ |
| 1411 | mv_udc_pullup(&udc->gadget, 1); |
| 1412 | |
| 1413 | /* When boot with cable attached, there will be no vbus irq occurred */ |
| 1414 | if (udc->qwork) |
| 1415 | queue_work(udc->qwork, &udc->vbus_work); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1416 | |
| 1417 | return 0; |
| 1418 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1419 | |
Sebastian Andrzej Siewior | 0f91349 | 2011-06-28 16:33:47 +0300 | [diff] [blame] | 1420 | static int mv_udc_stop(struct usb_gadget_driver *driver) |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1421 | { |
| 1422 | struct mv_udc *udc = the_controller; |
| 1423 | unsigned long flags; |
| 1424 | |
| 1425 | if (!udc) |
| 1426 | return -ENODEV; |
| 1427 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1428 | spin_lock_irqsave(&udc->lock, flags); |
| 1429 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1430 | mv_udc_enable(udc); |
| 1431 | udc_stop(udc); |
| 1432 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1433 | /* stop all usb activities */ |
| 1434 | udc->gadget.speed = USB_SPEED_UNKNOWN; |
| 1435 | stop_activity(udc, driver); |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 1436 | mv_udc_disable(udc); |
| 1437 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1438 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1439 | |
| 1440 | /* unbind gadget driver */ |
| 1441 | driver->unbind(&udc->gadget); |
| 1442 | udc->gadget.dev.driver = NULL; |
| 1443 | udc->driver = NULL; |
| 1444 | |
| 1445 | return 0; |
| 1446 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1447 | |
Neil Zhang | fb22cba | 2011-10-12 16:49:38 +0800 | [diff] [blame] | 1448 | static void mv_set_ptc(struct mv_udc *udc, u32 mode) |
| 1449 | { |
| 1450 | u32 portsc; |
| 1451 | |
| 1452 | portsc = readl(&udc->op_regs->portsc[0]); |
| 1453 | portsc |= mode << 16; |
| 1454 | writel(portsc, &udc->op_regs->portsc[0]); |
| 1455 | } |
| 1456 | |
| 1457 | static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req) |
| 1458 | { |
| 1459 | struct mv_udc *udc = the_controller; |
| 1460 | struct mv_req *req = container_of(_req, struct mv_req, req); |
| 1461 | unsigned long flags; |
| 1462 | |
| 1463 | dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode); |
| 1464 | |
| 1465 | spin_lock_irqsave(&udc->lock, flags); |
| 1466 | if (req->test_mode) { |
| 1467 | mv_set_ptc(udc, req->test_mode); |
| 1468 | req->test_mode = 0; |
| 1469 | } |
| 1470 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1471 | } |
| 1472 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1473 | static int |
| 1474 | udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty) |
| 1475 | { |
| 1476 | int retval = 0; |
| 1477 | struct mv_req *req; |
| 1478 | struct mv_ep *ep; |
| 1479 | |
| 1480 | ep = &udc->eps[0]; |
| 1481 | udc->ep0_dir = direction; |
Neil Zhang | 3661622 | 2011-10-12 16:49:34 +0800 | [diff] [blame] | 1482 | udc->ep0_state = WAIT_FOR_OUT_STATUS; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1483 | |
| 1484 | req = udc->status_req; |
| 1485 | |
| 1486 | /* fill in the reqest structure */ |
| 1487 | if (empty == false) { |
| 1488 | *((u16 *) req->req.buf) = cpu_to_le16(status); |
| 1489 | req->req.length = 2; |
| 1490 | } else |
| 1491 | req->req.length = 0; |
| 1492 | |
| 1493 | req->ep = ep; |
| 1494 | req->req.status = -EINPROGRESS; |
| 1495 | req->req.actual = 0; |
Neil Zhang | fb22cba | 2011-10-12 16:49:38 +0800 | [diff] [blame] | 1496 | if (udc->test_mode) { |
| 1497 | req->req.complete = prime_status_complete; |
| 1498 | req->test_mode = udc->test_mode; |
| 1499 | udc->test_mode = 0; |
| 1500 | } else |
| 1501 | req->req.complete = NULL; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1502 | req->dtd_count = 0; |
| 1503 | |
Neil Zhang | 46e172d | 2011-10-12 16:49:37 +0800 | [diff] [blame] | 1504 | if (req->req.dma == DMA_ADDR_INVALID) { |
| 1505 | req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, |
| 1506 | req->req.buf, req->req.length, |
| 1507 | ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 1508 | req->mapped = 1; |
| 1509 | } |
| 1510 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1511 | /* prime the data phase */ |
| 1512 | if (!req_to_dtd(req)) |
| 1513 | retval = queue_dtd(ep, req); |
| 1514 | else{ /* no mem */ |
| 1515 | retval = -ENOMEM; |
| 1516 | goto out; |
| 1517 | } |
| 1518 | |
| 1519 | if (retval) { |
| 1520 | dev_err(&udc->dev->dev, "response error on GET_STATUS request\n"); |
| 1521 | goto out; |
| 1522 | } |
| 1523 | |
| 1524 | list_add_tail(&req->queue, &ep->queue); |
| 1525 | |
| 1526 | return 0; |
| 1527 | out: |
| 1528 | return retval; |
| 1529 | } |
| 1530 | |
Neil Zhang | fb22cba | 2011-10-12 16:49:38 +0800 | [diff] [blame] | 1531 | static void mv_udc_testmode(struct mv_udc *udc, u16 index) |
| 1532 | { |
| 1533 | if (index <= TEST_FORCE_EN) { |
| 1534 | udc->test_mode = index; |
| 1535 | if (udc_prime_status(udc, EP_DIR_IN, 0, true)) |
| 1536 | ep0_stall(udc); |
| 1537 | } else |
| 1538 | dev_err(&udc->dev->dev, |
| 1539 | "This test mode(%d) is not supported\n", index); |
| 1540 | } |
| 1541 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1542 | static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup) |
| 1543 | { |
| 1544 | udc->dev_addr = (u8)setup->wValue; |
| 1545 | |
| 1546 | /* update usb state */ |
| 1547 | udc->usb_state = USB_STATE_ADDRESS; |
| 1548 | |
| 1549 | if (udc_prime_status(udc, EP_DIR_IN, 0, true)) |
| 1550 | ep0_stall(udc); |
| 1551 | } |
| 1552 | |
| 1553 | static void ch9getstatus(struct mv_udc *udc, u8 ep_num, |
| 1554 | struct usb_ctrlrequest *setup) |
| 1555 | { |
Felipe Balbi | 431879a | 2011-10-13 20:27:54 +0300 | [diff] [blame] | 1556 | u16 status = 0; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1557 | int retval; |
| 1558 | |
| 1559 | if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) |
| 1560 | != (USB_DIR_IN | USB_TYPE_STANDARD)) |
| 1561 | return; |
| 1562 | |
| 1563 | if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) { |
| 1564 | status = 1 << USB_DEVICE_SELF_POWERED; |
| 1565 | status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; |
| 1566 | } else if ((setup->bRequestType & USB_RECIP_MASK) |
| 1567 | == USB_RECIP_INTERFACE) { |
| 1568 | /* get interface status */ |
| 1569 | status = 0; |
| 1570 | } else if ((setup->bRequestType & USB_RECIP_MASK) |
| 1571 | == USB_RECIP_ENDPOINT) { |
| 1572 | u8 ep_num, direction; |
| 1573 | |
| 1574 | ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK; |
| 1575 | direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK) |
| 1576 | ? EP_DIR_IN : EP_DIR_OUT; |
| 1577 | status = ep_is_stall(udc, ep_num, direction) |
| 1578 | << USB_ENDPOINT_HALT; |
| 1579 | } |
| 1580 | |
| 1581 | retval = udc_prime_status(udc, EP_DIR_IN, status, false); |
| 1582 | if (retval) |
| 1583 | ep0_stall(udc); |
Neil Zhang | 3661622 | 2011-10-12 16:49:34 +0800 | [diff] [blame] | 1584 | else |
| 1585 | udc->ep0_state = DATA_STATE_XMIT; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1586 | } |
| 1587 | |
| 1588 | static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup) |
| 1589 | { |
| 1590 | u8 ep_num; |
| 1591 | u8 direction; |
| 1592 | struct mv_ep *ep; |
| 1593 | |
| 1594 | if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK)) |
| 1595 | == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) { |
| 1596 | switch (setup->wValue) { |
| 1597 | case USB_DEVICE_REMOTE_WAKEUP: |
| 1598 | udc->remote_wakeup = 0; |
| 1599 | break; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1600 | default: |
| 1601 | goto out; |
| 1602 | } |
| 1603 | } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK)) |
| 1604 | == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) { |
| 1605 | switch (setup->wValue) { |
| 1606 | case USB_ENDPOINT_HALT: |
| 1607 | ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK; |
| 1608 | direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK) |
| 1609 | ? EP_DIR_IN : EP_DIR_OUT; |
| 1610 | if (setup->wValue != 0 || setup->wLength != 0 |
| 1611 | || ep_num > udc->max_eps) |
| 1612 | goto out; |
| 1613 | ep = &udc->eps[ep_num * 2 + direction]; |
| 1614 | if (ep->wedge == 1) |
| 1615 | break; |
| 1616 | spin_unlock(&udc->lock); |
| 1617 | ep_set_stall(udc, ep_num, direction, 0); |
| 1618 | spin_lock(&udc->lock); |
| 1619 | break; |
| 1620 | default: |
| 1621 | goto out; |
| 1622 | } |
| 1623 | } else |
| 1624 | goto out; |
| 1625 | |
| 1626 | if (udc_prime_status(udc, EP_DIR_IN, 0, true)) |
| 1627 | ep0_stall(udc); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1628 | out: |
| 1629 | return; |
| 1630 | } |
| 1631 | |
| 1632 | static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup) |
| 1633 | { |
| 1634 | u8 ep_num; |
| 1635 | u8 direction; |
| 1636 | |
| 1637 | if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK)) |
| 1638 | == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) { |
| 1639 | switch (setup->wValue) { |
| 1640 | case USB_DEVICE_REMOTE_WAKEUP: |
| 1641 | udc->remote_wakeup = 1; |
| 1642 | break; |
| 1643 | case USB_DEVICE_TEST_MODE: |
| 1644 | if (setup->wIndex & 0xFF |
Neil Zhang | fb22cba | 2011-10-12 16:49:38 +0800 | [diff] [blame] | 1645 | || udc->gadget.speed != USB_SPEED_HIGH) |
| 1646 | ep0_stall(udc); |
| 1647 | |
| 1648 | if (udc->usb_state != USB_STATE_CONFIGURED |
| 1649 | && udc->usb_state != USB_STATE_ADDRESS |
| 1650 | && udc->usb_state != USB_STATE_DEFAULT) |
| 1651 | ep0_stall(udc); |
| 1652 | |
| 1653 | mv_udc_testmode(udc, (setup->wIndex >> 8)); |
| 1654 | goto out; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1655 | default: |
| 1656 | goto out; |
| 1657 | } |
| 1658 | } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK)) |
| 1659 | == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) { |
| 1660 | switch (setup->wValue) { |
| 1661 | case USB_ENDPOINT_HALT: |
| 1662 | ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK; |
| 1663 | direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK) |
| 1664 | ? EP_DIR_IN : EP_DIR_OUT; |
| 1665 | if (setup->wValue != 0 || setup->wLength != 0 |
| 1666 | || ep_num > udc->max_eps) |
| 1667 | goto out; |
| 1668 | spin_unlock(&udc->lock); |
| 1669 | ep_set_stall(udc, ep_num, direction, 1); |
| 1670 | spin_lock(&udc->lock); |
| 1671 | break; |
| 1672 | default: |
| 1673 | goto out; |
| 1674 | } |
| 1675 | } else |
| 1676 | goto out; |
| 1677 | |
| 1678 | if (udc_prime_status(udc, EP_DIR_IN, 0, true)) |
| 1679 | ep0_stall(udc); |
| 1680 | out: |
| 1681 | return; |
| 1682 | } |
| 1683 | |
| 1684 | static void handle_setup_packet(struct mv_udc *udc, u8 ep_num, |
| 1685 | struct usb_ctrlrequest *setup) |
| 1686 | { |
| 1687 | bool delegate = false; |
| 1688 | |
| 1689 | nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN); |
| 1690 | |
| 1691 | dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n", |
| 1692 | setup->bRequestType, setup->bRequest, |
| 1693 | setup->wValue, setup->wIndex, setup->wLength); |
| 1694 | /* We process some stardard setup requests here */ |
| 1695 | if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { |
| 1696 | switch (setup->bRequest) { |
| 1697 | case USB_REQ_GET_STATUS: |
| 1698 | ch9getstatus(udc, ep_num, setup); |
| 1699 | break; |
| 1700 | |
| 1701 | case USB_REQ_SET_ADDRESS: |
| 1702 | ch9setaddress(udc, setup); |
| 1703 | break; |
| 1704 | |
| 1705 | case USB_REQ_CLEAR_FEATURE: |
| 1706 | ch9clearfeature(udc, setup); |
| 1707 | break; |
| 1708 | |
| 1709 | case USB_REQ_SET_FEATURE: |
| 1710 | ch9setfeature(udc, setup); |
| 1711 | break; |
| 1712 | |
| 1713 | default: |
| 1714 | delegate = true; |
| 1715 | } |
| 1716 | } else |
| 1717 | delegate = true; |
| 1718 | |
| 1719 | /* delegate USB standard requests to the gadget driver */ |
| 1720 | if (delegate == true) { |
| 1721 | /* USB requests handled by gadget */ |
| 1722 | if (setup->wLength) { |
| 1723 | /* DATA phase from gadget, STATUS phase from udc */ |
| 1724 | udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) |
| 1725 | ? EP_DIR_IN : EP_DIR_OUT; |
| 1726 | spin_unlock(&udc->lock); |
| 1727 | if (udc->driver->setup(&udc->gadget, |
| 1728 | &udc->local_setup_buff) < 0) |
| 1729 | ep0_stall(udc); |
| 1730 | spin_lock(&udc->lock); |
| 1731 | udc->ep0_state = (setup->bRequestType & USB_DIR_IN) |
| 1732 | ? DATA_STATE_XMIT : DATA_STATE_RECV; |
| 1733 | } else { |
| 1734 | /* no DATA phase, IN STATUS phase from gadget */ |
| 1735 | udc->ep0_dir = EP_DIR_IN; |
| 1736 | spin_unlock(&udc->lock); |
| 1737 | if (udc->driver->setup(&udc->gadget, |
| 1738 | &udc->local_setup_buff) < 0) |
| 1739 | ep0_stall(udc); |
| 1740 | spin_lock(&udc->lock); |
| 1741 | udc->ep0_state = WAIT_FOR_OUT_STATUS; |
| 1742 | } |
| 1743 | } |
| 1744 | } |
| 1745 | |
| 1746 | /* complete DATA or STATUS phase of ep0 prime status phase if needed */ |
| 1747 | static void ep0_req_complete(struct mv_udc *udc, |
| 1748 | struct mv_ep *ep0, struct mv_req *req) |
| 1749 | { |
| 1750 | u32 new_addr; |
| 1751 | |
| 1752 | if (udc->usb_state == USB_STATE_ADDRESS) { |
| 1753 | /* set the new address */ |
| 1754 | new_addr = (u32)udc->dev_addr; |
| 1755 | writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT, |
| 1756 | &udc->op_regs->deviceaddr); |
| 1757 | } |
| 1758 | |
| 1759 | done(ep0, req, 0); |
| 1760 | |
| 1761 | switch (udc->ep0_state) { |
| 1762 | case DATA_STATE_XMIT: |
| 1763 | /* receive status phase */ |
| 1764 | if (udc_prime_status(udc, EP_DIR_OUT, 0, true)) |
| 1765 | ep0_stall(udc); |
| 1766 | break; |
| 1767 | case DATA_STATE_RECV: |
| 1768 | /* send status phase */ |
| 1769 | if (udc_prime_status(udc, EP_DIR_IN, 0 , true)) |
| 1770 | ep0_stall(udc); |
| 1771 | break; |
| 1772 | case WAIT_FOR_OUT_STATUS: |
| 1773 | udc->ep0_state = WAIT_FOR_SETUP; |
| 1774 | break; |
| 1775 | case WAIT_FOR_SETUP: |
| 1776 | dev_err(&udc->dev->dev, "unexpect ep0 packets\n"); |
| 1777 | break; |
| 1778 | default: |
| 1779 | ep0_stall(udc); |
| 1780 | break; |
| 1781 | } |
| 1782 | } |
| 1783 | |
| 1784 | static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr) |
| 1785 | { |
| 1786 | u32 temp; |
| 1787 | struct mv_dqh *dqh; |
| 1788 | |
| 1789 | dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT]; |
| 1790 | |
| 1791 | /* Clear bit in ENDPTSETUPSTAT */ |
Neil Zhang | 96c2bbb | 2011-10-12 16:49:30 +0800 | [diff] [blame] | 1792 | writel((1 << ep_num), &udc->op_regs->epsetupstat); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 1793 | |
| 1794 | /* while a hazard exists when setup package arrives */ |
| 1795 | do { |
| 1796 | /* Set Setup Tripwire */ |
| 1797 | temp = readl(&udc->op_regs->usbcmd); |
| 1798 | writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd); |
| 1799 | |
| 1800 | /* Copy the setup packet to local buffer */ |
| 1801 | memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8); |
| 1802 | } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET)); |
| 1803 | |
| 1804 | /* Clear Setup Tripwire */ |
| 1805 | temp = readl(&udc->op_regs->usbcmd); |
| 1806 | writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd); |
| 1807 | } |
| 1808 | |
| 1809 | static void irq_process_tr_complete(struct mv_udc *udc) |
| 1810 | { |
| 1811 | u32 tmp, bit_pos; |
| 1812 | int i, ep_num = 0, direction = 0; |
| 1813 | struct mv_ep *curr_ep; |
| 1814 | struct mv_req *curr_req, *temp_req; |
| 1815 | int status; |
| 1816 | |
| 1817 | /* |
| 1818 | * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE |
| 1819 | * because the setup packets are to be read ASAP |
| 1820 | */ |
| 1821 | |
| 1822 | /* Process all Setup packet received interrupts */ |
| 1823 | tmp = readl(&udc->op_regs->epsetupstat); |
| 1824 | |
| 1825 | if (tmp) { |
| 1826 | for (i = 0; i < udc->max_eps; i++) { |
| 1827 | if (tmp & (1 << i)) { |
| 1828 | get_setup_data(udc, i, |
| 1829 | (u8 *)(&udc->local_setup_buff)); |
| 1830 | handle_setup_packet(udc, i, |
| 1831 | &udc->local_setup_buff); |
| 1832 | } |
| 1833 | } |
| 1834 | } |
| 1835 | |
| 1836 | /* Don't clear the endpoint setup status register here. |
| 1837 | * It is cleared as a setup packet is read out of the buffer |
| 1838 | */ |
| 1839 | |
| 1840 | /* Process non-setup transaction complete interrupts */ |
| 1841 | tmp = readl(&udc->op_regs->epcomplete); |
| 1842 | |
| 1843 | if (!tmp) |
| 1844 | return; |
| 1845 | |
| 1846 | writel(tmp, &udc->op_regs->epcomplete); |
| 1847 | |
| 1848 | for (i = 0; i < udc->max_eps * 2; i++) { |
| 1849 | ep_num = i >> 1; |
| 1850 | direction = i % 2; |
| 1851 | |
| 1852 | bit_pos = 1 << (ep_num + 16 * direction); |
| 1853 | |
| 1854 | if (!(bit_pos & tmp)) |
| 1855 | continue; |
| 1856 | |
| 1857 | if (i == 1) |
| 1858 | curr_ep = &udc->eps[0]; |
| 1859 | else |
| 1860 | curr_ep = &udc->eps[i]; |
| 1861 | /* process the req queue until an uncomplete request */ |
| 1862 | list_for_each_entry_safe(curr_req, temp_req, |
| 1863 | &curr_ep->queue, queue) { |
| 1864 | status = process_ep_req(udc, i, curr_req); |
| 1865 | if (status) |
| 1866 | break; |
| 1867 | |
| 1868 | /* write back status to req */ |
| 1869 | curr_req->req.status = status; |
| 1870 | |
| 1871 | /* ep0 request completion */ |
| 1872 | if (ep_num == 0) { |
| 1873 | ep0_req_complete(udc, curr_ep, curr_req); |
| 1874 | break; |
| 1875 | } else { |
| 1876 | done(curr_ep, curr_req, status); |
| 1877 | } |
| 1878 | } |
| 1879 | } |
| 1880 | } |
| 1881 | |
| 1882 | void irq_process_reset(struct mv_udc *udc) |
| 1883 | { |
| 1884 | u32 tmp; |
| 1885 | unsigned int loops; |
| 1886 | |
| 1887 | udc->ep0_dir = EP_DIR_OUT; |
| 1888 | udc->ep0_state = WAIT_FOR_SETUP; |
| 1889 | udc->remote_wakeup = 0; /* default to 0 on reset */ |
| 1890 | |
| 1891 | /* The address bits are past bit 25-31. Set the address */ |
| 1892 | tmp = readl(&udc->op_regs->deviceaddr); |
| 1893 | tmp &= ~(USB_DEVICE_ADDRESS_MASK); |
| 1894 | writel(tmp, &udc->op_regs->deviceaddr); |
| 1895 | |
| 1896 | /* Clear all the setup token semaphores */ |
| 1897 | tmp = readl(&udc->op_regs->epsetupstat); |
| 1898 | writel(tmp, &udc->op_regs->epsetupstat); |
| 1899 | |
| 1900 | /* Clear all the endpoint complete status bits */ |
| 1901 | tmp = readl(&udc->op_regs->epcomplete); |
| 1902 | writel(tmp, &udc->op_regs->epcomplete); |
| 1903 | |
| 1904 | /* wait until all endptprime bits cleared */ |
| 1905 | loops = LOOPS(PRIME_TIMEOUT); |
| 1906 | while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) { |
| 1907 | if (loops == 0) { |
| 1908 | dev_err(&udc->dev->dev, |
| 1909 | "Timeout for ENDPTPRIME = 0x%x\n", |
| 1910 | readl(&udc->op_regs->epprime)); |
| 1911 | break; |
| 1912 | } |
| 1913 | loops--; |
| 1914 | udelay(LOOPS_USEC); |
| 1915 | } |
| 1916 | |
| 1917 | /* Write 1s to the Flush register */ |
| 1918 | writel((u32)~0, &udc->op_regs->epflush); |
| 1919 | |
| 1920 | if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) { |
| 1921 | dev_info(&udc->dev->dev, "usb bus reset\n"); |
| 1922 | udc->usb_state = USB_STATE_DEFAULT; |
| 1923 | /* reset all the queues, stop all USB activities */ |
| 1924 | stop_activity(udc, udc->driver); |
| 1925 | } else { |
| 1926 | dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n", |
| 1927 | readl(&udc->op_regs->portsc)); |
| 1928 | |
| 1929 | /* |
| 1930 | * re-initialize |
| 1931 | * controller reset |
| 1932 | */ |
| 1933 | udc_reset(udc); |
| 1934 | |
| 1935 | /* reset all the queues, stop all USB activities */ |
| 1936 | stop_activity(udc, udc->driver); |
| 1937 | |
| 1938 | /* reset ep0 dQH and endptctrl */ |
| 1939 | ep0_reset(udc); |
| 1940 | |
| 1941 | /* enable interrupt and set controller to run state */ |
| 1942 | udc_start(udc); |
| 1943 | |
| 1944 | udc->usb_state = USB_STATE_ATTACHED; |
| 1945 | } |
| 1946 | } |
| 1947 | |
| 1948 | static void handle_bus_resume(struct mv_udc *udc) |
| 1949 | { |
| 1950 | udc->usb_state = udc->resume_state; |
| 1951 | udc->resume_state = 0; |
| 1952 | |
| 1953 | /* report resume to the driver */ |
| 1954 | if (udc->driver) { |
| 1955 | if (udc->driver->resume) { |
| 1956 | spin_unlock(&udc->lock); |
| 1957 | udc->driver->resume(&udc->gadget); |
| 1958 | spin_lock(&udc->lock); |
| 1959 | } |
| 1960 | } |
| 1961 | } |
| 1962 | |
| 1963 | static void irq_process_suspend(struct mv_udc *udc) |
| 1964 | { |
| 1965 | udc->resume_state = udc->usb_state; |
| 1966 | udc->usb_state = USB_STATE_SUSPENDED; |
| 1967 | |
| 1968 | if (udc->driver->suspend) { |
| 1969 | spin_unlock(&udc->lock); |
| 1970 | udc->driver->suspend(&udc->gadget); |
| 1971 | spin_lock(&udc->lock); |
| 1972 | } |
| 1973 | } |
| 1974 | |
| 1975 | static void irq_process_port_change(struct mv_udc *udc) |
| 1976 | { |
| 1977 | u32 portsc; |
| 1978 | |
| 1979 | portsc = readl(&udc->op_regs->portsc[0]); |
| 1980 | if (!(portsc & PORTSCX_PORT_RESET)) { |
| 1981 | /* Get the speed */ |
| 1982 | u32 speed = portsc & PORTSCX_PORT_SPEED_MASK; |
| 1983 | switch (speed) { |
| 1984 | case PORTSCX_PORT_SPEED_HIGH: |
| 1985 | udc->gadget.speed = USB_SPEED_HIGH; |
| 1986 | break; |
| 1987 | case PORTSCX_PORT_SPEED_FULL: |
| 1988 | udc->gadget.speed = USB_SPEED_FULL; |
| 1989 | break; |
| 1990 | case PORTSCX_PORT_SPEED_LOW: |
| 1991 | udc->gadget.speed = USB_SPEED_LOW; |
| 1992 | break; |
| 1993 | default: |
| 1994 | udc->gadget.speed = USB_SPEED_UNKNOWN; |
| 1995 | break; |
| 1996 | } |
| 1997 | } |
| 1998 | |
| 1999 | if (portsc & PORTSCX_PORT_SUSPEND) { |
| 2000 | udc->resume_state = udc->usb_state; |
| 2001 | udc->usb_state = USB_STATE_SUSPENDED; |
| 2002 | if (udc->driver->suspend) { |
| 2003 | spin_unlock(&udc->lock); |
| 2004 | udc->driver->suspend(&udc->gadget); |
| 2005 | spin_lock(&udc->lock); |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | if (!(portsc & PORTSCX_PORT_SUSPEND) |
| 2010 | && udc->usb_state == USB_STATE_SUSPENDED) { |
| 2011 | handle_bus_resume(udc); |
| 2012 | } |
| 2013 | |
| 2014 | if (!udc->resume_state) |
| 2015 | udc->usb_state = USB_STATE_DEFAULT; |
| 2016 | } |
| 2017 | |
| 2018 | static void irq_process_error(struct mv_udc *udc) |
| 2019 | { |
| 2020 | /* Increment the error count */ |
| 2021 | udc->errors++; |
| 2022 | } |
| 2023 | |
| 2024 | static irqreturn_t mv_udc_irq(int irq, void *dev) |
| 2025 | { |
| 2026 | struct mv_udc *udc = (struct mv_udc *)dev; |
| 2027 | u32 status, intr; |
| 2028 | |
| 2029 | spin_lock(&udc->lock); |
| 2030 | |
| 2031 | status = readl(&udc->op_regs->usbsts); |
| 2032 | intr = readl(&udc->op_regs->usbintr); |
| 2033 | status &= intr; |
| 2034 | |
| 2035 | if (status == 0) { |
| 2036 | spin_unlock(&udc->lock); |
| 2037 | return IRQ_NONE; |
| 2038 | } |
| 2039 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 2040 | /* Clear all the interrupts occurred */ |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2041 | writel(status, &udc->op_regs->usbsts); |
| 2042 | |
| 2043 | if (status & USBSTS_ERR) |
| 2044 | irq_process_error(udc); |
| 2045 | |
| 2046 | if (status & USBSTS_RESET) |
| 2047 | irq_process_reset(udc); |
| 2048 | |
| 2049 | if (status & USBSTS_PORT_CHANGE) |
| 2050 | irq_process_port_change(udc); |
| 2051 | |
| 2052 | if (status & USBSTS_INT) |
| 2053 | irq_process_tr_complete(udc); |
| 2054 | |
| 2055 | if (status & USBSTS_SUSPEND) |
| 2056 | irq_process_suspend(udc); |
| 2057 | |
| 2058 | spin_unlock(&udc->lock); |
| 2059 | |
| 2060 | return IRQ_HANDLED; |
| 2061 | } |
| 2062 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 2063 | static irqreturn_t mv_udc_vbus_irq(int irq, void *dev) |
| 2064 | { |
| 2065 | struct mv_udc *udc = (struct mv_udc *)dev; |
| 2066 | |
| 2067 | /* polling VBUS and init phy may cause too much time*/ |
| 2068 | if (udc->qwork) |
| 2069 | queue_work(udc->qwork, &udc->vbus_work); |
| 2070 | |
| 2071 | return IRQ_HANDLED; |
| 2072 | } |
| 2073 | |
| 2074 | static void mv_udc_vbus_work(struct work_struct *work) |
| 2075 | { |
| 2076 | struct mv_udc *udc; |
| 2077 | unsigned int vbus; |
| 2078 | |
| 2079 | udc = container_of(work, struct mv_udc, vbus_work); |
| 2080 | if (!udc->pdata->vbus) |
| 2081 | return; |
| 2082 | |
| 2083 | vbus = udc->pdata->vbus->poll(); |
| 2084 | dev_info(&udc->dev->dev, "vbus is %d\n", vbus); |
| 2085 | |
| 2086 | if (vbus == VBUS_HIGH) |
| 2087 | mv_udc_vbus_session(&udc->gadget, 1); |
| 2088 | else if (vbus == VBUS_LOW) |
| 2089 | mv_udc_vbus_session(&udc->gadget, 0); |
| 2090 | } |
| 2091 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2092 | /* release device structure */ |
| 2093 | static void gadget_release(struct device *_dev) |
| 2094 | { |
| 2095 | struct mv_udc *udc = the_controller; |
| 2096 | |
| 2097 | complete(udc->done); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2098 | } |
| 2099 | |
Neil Zhang | 5d0b8d0 | 2011-10-12 16:49:25 +0800 | [diff] [blame] | 2100 | static int __devexit mv_udc_remove(struct platform_device *dev) |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2101 | { |
| 2102 | struct mv_udc *udc = the_controller; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2103 | int clk_i; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2104 | |
Sebastian Andrzej Siewior | 0f91349 | 2011-06-28 16:33:47 +0300 | [diff] [blame] | 2105 | usb_del_gadget_udc(&udc->gadget); |
| 2106 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 2107 | if (udc->qwork) { |
| 2108 | flush_workqueue(udc->qwork); |
| 2109 | destroy_workqueue(udc->qwork); |
| 2110 | } |
| 2111 | |
| 2112 | if (udc->pdata && udc->pdata->vbus && udc->clock_gating) |
| 2113 | free_irq(udc->pdata->vbus->irq, &dev->dev); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2114 | |
| 2115 | /* free memory allocated in probe */ |
| 2116 | if (udc->dtd_pool) |
| 2117 | dma_pool_destroy(udc->dtd_pool); |
| 2118 | |
| 2119 | if (udc->ep_dqh) |
| 2120 | dma_free_coherent(&dev->dev, udc->ep_dqh_size, |
| 2121 | udc->ep_dqh, udc->ep_dqh_dma); |
| 2122 | |
| 2123 | kfree(udc->eps); |
| 2124 | |
| 2125 | if (udc->irq) |
| 2126 | free_irq(udc->irq, &dev->dev); |
| 2127 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 2128 | mv_udc_disable(udc); |
| 2129 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2130 | if (udc->cap_regs) |
| 2131 | iounmap(udc->cap_regs); |
| 2132 | udc->cap_regs = NULL; |
| 2133 | |
| 2134 | if (udc->phy_regs) |
| 2135 | iounmap((void *)udc->phy_regs); |
| 2136 | udc->phy_regs = 0; |
| 2137 | |
| 2138 | if (udc->status_req) { |
| 2139 | kfree(udc->status_req->req.buf); |
| 2140 | kfree(udc->status_req); |
| 2141 | } |
| 2142 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2143 | for (clk_i = 0; clk_i <= udc->clknum; clk_i++) |
| 2144 | clk_put(udc->clk[clk_i]); |
| 2145 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2146 | device_unregister(&udc->gadget.dev); |
| 2147 | |
| 2148 | /* free dev, wait for the release() finished */ |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2149 | wait_for_completion(udc->done); |
| 2150 | kfree(udc); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2151 | |
| 2152 | the_controller = NULL; |
| 2153 | |
| 2154 | return 0; |
| 2155 | } |
| 2156 | |
Neil Zhang | 5d0b8d0 | 2011-10-12 16:49:25 +0800 | [diff] [blame] | 2157 | static int __devinit mv_udc_probe(struct platform_device *dev) |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2158 | { |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2159 | struct mv_usb_platform_data *pdata = dev->dev.platform_data; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2160 | struct mv_udc *udc; |
| 2161 | int retval = 0; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2162 | int clk_i = 0; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2163 | struct resource *r; |
| 2164 | size_t size; |
| 2165 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2166 | if (pdata == NULL) { |
| 2167 | dev_err(&dev->dev, "missing platform_data\n"); |
| 2168 | return -ENODEV; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2169 | } |
| 2170 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2171 | size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum; |
| 2172 | udc = kzalloc(size, GFP_KERNEL); |
| 2173 | if (udc == NULL) { |
| 2174 | dev_err(&dev->dev, "failed to allocate memory for udc\n"); |
| 2175 | return -ENOMEM; |
| 2176 | } |
| 2177 | |
| 2178 | the_controller = udc; |
| 2179 | udc->done = &release_done; |
| 2180 | udc->pdata = dev->dev.platform_data; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2181 | spin_lock_init(&udc->lock); |
| 2182 | |
| 2183 | udc->dev = dev; |
| 2184 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2185 | udc->clknum = pdata->clknum; |
| 2186 | for (clk_i = 0; clk_i < udc->clknum; clk_i++) { |
| 2187 | udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]); |
| 2188 | if (IS_ERR(udc->clk[clk_i])) { |
| 2189 | retval = PTR_ERR(udc->clk[clk_i]); |
| 2190 | goto err_put_clk; |
| 2191 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2192 | } |
| 2193 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2194 | r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs"); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2195 | if (r == NULL) { |
| 2196 | dev_err(&dev->dev, "no I/O memory resource defined\n"); |
| 2197 | retval = -ENODEV; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2198 | goto err_put_clk; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2199 | } |
| 2200 | |
| 2201 | udc->cap_regs = (struct mv_cap_regs __iomem *) |
| 2202 | ioremap(r->start, resource_size(r)); |
| 2203 | if (udc->cap_regs == NULL) { |
| 2204 | dev_err(&dev->dev, "failed to map I/O memory\n"); |
| 2205 | retval = -EBUSY; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2206 | goto err_put_clk; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2207 | } |
| 2208 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2209 | r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs"); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2210 | if (r == NULL) { |
| 2211 | dev_err(&dev->dev, "no phy I/O memory resource defined\n"); |
| 2212 | retval = -ENODEV; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2213 | goto err_iounmap_capreg; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2214 | } |
| 2215 | |
| 2216 | udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r)); |
| 2217 | if (udc->phy_regs == 0) { |
| 2218 | dev_err(&dev->dev, "failed to map phy I/O memory\n"); |
| 2219 | retval = -EBUSY; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2220 | goto err_iounmap_capreg; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2221 | } |
| 2222 | |
| 2223 | /* we will acces controller register, so enable the clk */ |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2224 | udc_clock_enable(udc); |
| 2225 | if (pdata->phy_init) { |
| 2226 | retval = pdata->phy_init(udc->phy_regs); |
| 2227 | if (retval) { |
| 2228 | dev_err(&dev->dev, "phy init error %d\n", retval); |
| 2229 | goto err_iounmap_phyreg; |
| 2230 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2231 | } |
| 2232 | |
| 2233 | udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs |
| 2234 | + (readl(&udc->cap_regs->caplength_hciversion) |
| 2235 | & CAPLENGTH_MASK)); |
| 2236 | udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK; |
| 2237 | |
Neil Zhang | 4540a9ab | 2011-10-12 16:49:26 +0800 | [diff] [blame] | 2238 | /* |
| 2239 | * some platform will use usb to download image, it may not disconnect |
| 2240 | * usb gadget before loading kernel. So first stop udc here. |
| 2241 | */ |
| 2242 | udc_stop(udc); |
| 2243 | writel(0xFFFFFFFF, &udc->op_regs->usbsts); |
| 2244 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2245 | size = udc->max_eps * sizeof(struct mv_dqh) *2; |
| 2246 | size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1); |
| 2247 | udc->ep_dqh = dma_alloc_coherent(&dev->dev, size, |
| 2248 | &udc->ep_dqh_dma, GFP_KERNEL); |
| 2249 | |
| 2250 | if (udc->ep_dqh == NULL) { |
| 2251 | dev_err(&dev->dev, "allocate dQH memory failed\n"); |
| 2252 | retval = -ENOMEM; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2253 | goto err_disable_clock; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2254 | } |
| 2255 | udc->ep_dqh_size = size; |
| 2256 | |
| 2257 | /* create dTD dma_pool resource */ |
| 2258 | udc->dtd_pool = dma_pool_create("mv_dtd", |
| 2259 | &dev->dev, |
| 2260 | sizeof(struct mv_dtd), |
| 2261 | DTD_ALIGNMENT, |
| 2262 | DMA_BOUNDARY); |
| 2263 | |
| 2264 | if (!udc->dtd_pool) { |
| 2265 | retval = -ENOMEM; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2266 | goto err_free_dma; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2267 | } |
| 2268 | |
| 2269 | size = udc->max_eps * sizeof(struct mv_ep) *2; |
| 2270 | udc->eps = kzalloc(size, GFP_KERNEL); |
| 2271 | if (udc->eps == NULL) { |
| 2272 | dev_err(&dev->dev, "allocate ep memory failed\n"); |
| 2273 | retval = -ENOMEM; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2274 | goto err_destroy_dma; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2275 | } |
| 2276 | |
| 2277 | /* initialize ep0 status request structure */ |
| 2278 | udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL); |
| 2279 | if (!udc->status_req) { |
| 2280 | dev_err(&dev->dev, "allocate status_req memory failed\n"); |
| 2281 | retval = -ENOMEM; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2282 | goto err_free_eps; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2283 | } |
| 2284 | INIT_LIST_HEAD(&udc->status_req->queue); |
| 2285 | |
| 2286 | /* allocate a small amount of memory to get valid address */ |
| 2287 | udc->status_req->req.buf = kzalloc(8, GFP_KERNEL); |
Neil Zhang | 46e172d | 2011-10-12 16:49:37 +0800 | [diff] [blame] | 2288 | udc->status_req->req.dma = DMA_ADDR_INVALID; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2289 | |
| 2290 | udc->resume_state = USB_STATE_NOTATTACHED; |
| 2291 | udc->usb_state = USB_STATE_POWERED; |
| 2292 | udc->ep0_dir = EP_DIR_OUT; |
| 2293 | udc->remote_wakeup = 0; |
| 2294 | |
| 2295 | r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0); |
| 2296 | if (r == NULL) { |
| 2297 | dev_err(&dev->dev, "no IRQ resource defined\n"); |
| 2298 | retval = -ENODEV; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2299 | goto err_free_status_req; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2300 | } |
| 2301 | udc->irq = r->start; |
| 2302 | if (request_irq(udc->irq, mv_udc_irq, |
Yong Zhang | b5dd18d | 2011-09-07 16:10:52 +0800 | [diff] [blame] | 2303 | IRQF_SHARED, driver_name, udc)) { |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2304 | dev_err(&dev->dev, "Request irq %d for UDC failed\n", |
| 2305 | udc->irq); |
| 2306 | retval = -ENODEV; |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2307 | goto err_free_status_req; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2308 | } |
| 2309 | |
| 2310 | /* initialize gadget structure */ |
| 2311 | udc->gadget.ops = &mv_ops; /* usb_gadget_ops */ |
| 2312 | udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */ |
| 2313 | INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */ |
| 2314 | udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */ |
Michal Nazarewicz | d327ab5 | 2011-11-19 18:27:37 +0100 | [diff] [blame] | 2315 | udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */ |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2316 | |
| 2317 | /* the "gadget" abstracts/virtualizes the controller */ |
| 2318 | dev_set_name(&udc->gadget.dev, "gadget"); |
| 2319 | udc->gadget.dev.parent = &dev->dev; |
| 2320 | udc->gadget.dev.dma_mask = dev->dev.dma_mask; |
| 2321 | udc->gadget.dev.release = gadget_release; |
| 2322 | udc->gadget.name = driver_name; /* gadget name */ |
| 2323 | |
| 2324 | retval = device_register(&udc->gadget.dev); |
| 2325 | if (retval) |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2326 | goto err_free_irq; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2327 | |
| 2328 | eps_init(udc); |
| 2329 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 2330 | /* VBUS detect: we can disable/enable clock on demand.*/ |
| 2331 | if (pdata->vbus) { |
| 2332 | udc->clock_gating = 1; |
| 2333 | retval = request_threaded_irq(pdata->vbus->irq, NULL, |
| 2334 | mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc); |
| 2335 | if (retval) { |
| 2336 | dev_info(&dev->dev, |
| 2337 | "Can not request irq for VBUS, " |
| 2338 | "disable clock gating\n"); |
| 2339 | udc->clock_gating = 0; |
| 2340 | } |
| 2341 | |
| 2342 | udc->qwork = create_singlethread_workqueue("mv_udc_queue"); |
| 2343 | if (!udc->qwork) { |
| 2344 | dev_err(&dev->dev, "cannot create workqueue\n"); |
| 2345 | retval = -ENOMEM; |
| 2346 | goto err_unregister; |
| 2347 | } |
| 2348 | |
| 2349 | INIT_WORK(&udc->vbus_work, mv_udc_vbus_work); |
| 2350 | } |
| 2351 | |
| 2352 | /* |
| 2353 | * When clock gating is supported, we can disable clk and phy. |
| 2354 | * If not, it means that VBUS detection is not supported, we |
| 2355 | * have to enable vbus active all the time to let controller work. |
| 2356 | */ |
| 2357 | if (udc->clock_gating) { |
| 2358 | if (udc->pdata->phy_deinit) |
| 2359 | udc->pdata->phy_deinit(udc->phy_regs); |
| 2360 | udc_clock_disable(udc); |
| 2361 | } else |
| 2362 | udc->vbus_active = 1; |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2363 | |
Sebastian Andrzej Siewior | 0f91349 | 2011-06-28 16:33:47 +0300 | [diff] [blame] | 2364 | retval = usb_add_gadget_udc(&dev->dev, &udc->gadget); |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2365 | if (retval) |
| 2366 | goto err_unregister; |
| 2367 | |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 2368 | dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n", |
| 2369 | udc->clock_gating ? "with" : "without"); |
| 2370 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2371 | return 0; |
| 2372 | |
| 2373 | err_unregister: |
Neil Zhang | 1aec033 | 2011-10-12 16:49:39 +0800 | [diff] [blame] | 2374 | if (udc->pdata && udc->pdata->vbus && udc->clock_gating) |
| 2375 | free_irq(pdata->vbus->irq, &dev->dev); |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2376 | device_unregister(&udc->gadget.dev); |
| 2377 | err_free_irq: |
| 2378 | free_irq(udc->irq, &dev->dev); |
| 2379 | err_free_status_req: |
| 2380 | kfree(udc->status_req->req.buf); |
| 2381 | kfree(udc->status_req); |
| 2382 | err_free_eps: |
| 2383 | kfree(udc->eps); |
| 2384 | err_destroy_dma: |
| 2385 | dma_pool_destroy(udc->dtd_pool); |
| 2386 | err_free_dma: |
| 2387 | dma_free_coherent(&dev->dev, udc->ep_dqh_size, |
| 2388 | udc->ep_dqh, udc->ep_dqh_dma); |
| 2389 | err_disable_clock: |
| 2390 | if (udc->pdata->phy_deinit) |
| 2391 | udc->pdata->phy_deinit(udc->phy_regs); |
| 2392 | udc_clock_disable(udc); |
| 2393 | err_iounmap_phyreg: |
| 2394 | iounmap((void *)udc->phy_regs); |
| 2395 | err_iounmap_capreg: |
| 2396 | iounmap(udc->cap_regs); |
| 2397 | err_put_clk: |
| 2398 | for (clk_i--; clk_i >= 0; clk_i--) |
| 2399 | clk_put(udc->clk[clk_i]); |
| 2400 | the_controller = NULL; |
| 2401 | kfree(udc); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2402 | return retval; |
| 2403 | } |
| 2404 | |
| 2405 | #ifdef CONFIG_PM |
Sebastian Andrzej Siewior | cb42447 | 2011-06-03 19:50:45 +0200 | [diff] [blame] | 2406 | static int mv_udc_suspend(struct device *_dev) |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2407 | { |
| 2408 | struct mv_udc *udc = the_controller; |
| 2409 | |
| 2410 | udc_stop(udc); |
| 2411 | |
| 2412 | return 0; |
| 2413 | } |
| 2414 | |
Sebastian Andrzej Siewior | cb42447 | 2011-06-03 19:50:45 +0200 | [diff] [blame] | 2415 | static int mv_udc_resume(struct device *_dev) |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2416 | { |
| 2417 | struct mv_udc *udc = the_controller; |
| 2418 | int retval; |
| 2419 | |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2420 | if (udc->pdata->phy_init) { |
| 2421 | retval = udc->pdata->phy_init(udc->phy_regs); |
| 2422 | if (retval) { |
| 2423 | dev_err(&udc->dev->dev, |
| 2424 | "init phy error %d when resume back\n", |
| 2425 | retval); |
| 2426 | return retval; |
| 2427 | } |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2428 | } |
Neil Zhang | dde34cc | 2011-10-12 16:49:24 +0800 | [diff] [blame] | 2429 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2430 | udc_reset(udc); |
| 2431 | ep0_reset(udc); |
| 2432 | udc_start(udc); |
| 2433 | |
| 2434 | return 0; |
| 2435 | } |
| 2436 | |
| 2437 | static const struct dev_pm_ops mv_udc_pm_ops = { |
| 2438 | .suspend = mv_udc_suspend, |
| 2439 | .resume = mv_udc_resume, |
| 2440 | }; |
| 2441 | #endif |
| 2442 | |
Neil Zhang | 046b07a | 2011-10-12 16:49:35 +0800 | [diff] [blame] | 2443 | static void mv_udc_shutdown(struct platform_device *dev) |
| 2444 | { |
| 2445 | struct mv_udc *udc = the_controller; |
| 2446 | u32 mode; |
| 2447 | |
| 2448 | /* reset controller mode to IDLE */ |
| 2449 | mode = readl(&udc->op_regs->usbmode); |
| 2450 | mode &= ~3; |
| 2451 | writel(mode, &udc->op_regs->usbmode); |
| 2452 | } |
| 2453 | |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2454 | static struct platform_driver udc_driver = { |
| 2455 | .probe = mv_udc_probe, |
| 2456 | .remove = __exit_p(mv_udc_remove), |
Neil Zhang | 046b07a | 2011-10-12 16:49:35 +0800 | [diff] [blame] | 2457 | .shutdown = mv_udc_shutdown, |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2458 | .driver = { |
| 2459 | .owner = THIS_MODULE, |
| 2460 | .name = "pxa-u2o", |
| 2461 | #ifdef CONFIG_PM |
Sebastian Andrzej Siewior | cb42447 | 2011-06-03 19:50:45 +0200 | [diff] [blame] | 2462 | .pm = &mv_udc_pm_ops, |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2463 | #endif |
| 2464 | }, |
| 2465 | }; |
Sebastian Andrzej Siewior | 86081d7 | 2011-06-29 16:41:55 +0300 | [diff] [blame] | 2466 | MODULE_ALIAS("platform:pxa-u2o"); |
cxie4 | e7cddda | 2010-11-30 13:35:15 +0800 | [diff] [blame] | 2467 | |
| 2468 | MODULE_DESCRIPTION(DRIVER_DESC); |
| 2469 | MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>"); |
| 2470 | MODULE_VERSION(DRIVER_VERSION); |
| 2471 | MODULE_LICENSE("GPL"); |
| 2472 | |
| 2473 | |
| 2474 | static int __init init(void) |
| 2475 | { |
| 2476 | return platform_driver_register(&udc_driver); |
| 2477 | } |
| 2478 | module_init(init); |
| 2479 | |
| 2480 | |
| 2481 | static void __exit cleanup(void) |
| 2482 | { |
| 2483 | platform_driver_unregister(&udc_driver); |
| 2484 | } |
| 2485 | module_exit(cleanup); |
| 2486 | |