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Sekhar Noria6c0f6e2009-11-03 15:14:13 +05301/*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/cpuidle.h>
18#include <linux/io.h>
Paul Gortmakerdc280942011-07-31 16:17:29 -040019#include <linux/export.h>
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053020#include <asm/proc-fns.h>
Robert Lee19976c22012-03-20 15:22:45 -050021#include <asm/cpuidle.h>
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053022
23#include <mach/cpuidle.h>
Nicolas Pitre0020afb2011-07-05 22:52:57 -040024#include <mach/ddr2.h>
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053025
26#define DAVINCI_CPUIDLE_MAX_STATES 2
27
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053028static void __iomem *ddr2_reg_base;
Daniel Lezcano5af4a212013-02-04 12:01:41 +000029static bool ddr2_pdown;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053030
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053031static void davinci_save_ddr_power(int enter, bool pdown)
32{
33 u32 val;
34
35 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
36
37 if (enter) {
38 if (pdown)
39 val |= DDR2_SRPD_BIT;
40 else
41 val &= ~DDR2_SRPD_BIT;
42 val |= DDR2_LPMODEN_BIT;
43 } else {
44 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
45 }
46
47 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
48}
49
Daniel Lezcano8d601432013-02-04 12:01:42 +000050/* Actual code that puts the SoC in different idle states */
51static int davinci_enter_idle(struct cpuidle_device *dev,
Daniel Lezcanoc062d442013-04-03 12:15:19 +000052 struct cpuidle_driver *drv, int index)
Daniel Lezcano8d601432013-02-04 12:01:42 +000053{
Daniel Lezcano36ce8d42013-02-04 12:01:43 +000054 davinci_save_ddr_power(1, ddr2_pdown);
Daniel Lezcanoc062d442013-04-03 12:15:19 +000055 cpu_do_idle();
Daniel Lezcano36ce8d42013-02-04 12:01:43 +000056 davinci_save_ddr_power(0, ddr2_pdown);
Daniel Lezcano8d601432013-02-04 12:01:42 +000057
58 return index;
59}
60
61static struct cpuidle_driver davinci_idle_driver = {
62 .name = "cpuidle-davinci",
63 .owner = THIS_MODULE,
Daniel Lezcano8d601432013-02-04 12:01:42 +000064 .states[0] = ARM_CPUIDLE_WFI_STATE,
65 .states[1] = {
66 .enter = davinci_enter_idle,
67 .exit_latency = 10,
Daniel Lezcano7006b8a2013-06-28 12:09:09 +020068 .target_residency = 10000,
Daniel Lezcano8d601432013-02-04 12:01:42 +000069 .flags = CPUIDLE_FLAG_TIME_VALID,
70 .name = "DDR SR",
71 .desc = "WFI and DDR Self Refresh",
72 },
73 .state_count = DAVINCI_CPUIDLE_MAX_STATES,
74};
75
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053076static int __init davinci_cpuidle_probe(struct platform_device *pdev)
77{
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053078 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053079
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053080 if (!pdata) {
81 dev_err(&pdev->dev, "cannot get platform data\n");
82 return -ENOENT;
83 }
84
Sekhar Nori948c66d2009-11-16 17:21:37 +053085 ddr2_reg_base = pdata->ddr2_ctlr_base;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053086
Daniel Lezcano5af4a212013-02-04 12:01:41 +000087 ddr2_pdown = pdata->ddr2_pdown;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053088
Daniel Lezcano3aec0342013-04-23 08:54:44 +000089 return cpuidle_register(&davinci_idle_driver, NULL);
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053090}
91
92static struct platform_driver davinci_cpuidle_driver = {
93 .driver = {
94 .name = "cpuidle-davinci",
95 .owner = THIS_MODULE,
96 },
97};
98
99static int __init davinci_cpuidle_init(void)
100{
101 return platform_driver_probe(&davinci_cpuidle_driver,
102 davinci_cpuidle_probe);
103}
104device_initcall(davinci_cpuidle_init);
105