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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
4 */
5
6#ifndef MSI_H
7#define MSI_H
8
Hidetoshi Seto2c21fd42009-06-23 17:40:04 +09009#define PCI_MSIX_ENTRY_SIZE 16
10#define PCI_MSIX_ENTRY_LOWER_ADDR 0
11#define PCI_MSIX_ENTRY_UPPER_ADDR 4
12#define PCI_MSIX_ENTRY_DATA 8
13#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
16#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
17#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
18#define msi_data_reg(base, is64bit) \
Hidetoshi Seto67b5db62009-04-20 10:54:59 +090019 (base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32))
20#define msi_mask_reg(base, is64bit) \
21 (base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32))
Eric W. Biedermandd159ee2006-10-04 02:16:32 -070022#define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
23#define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#define msix_table_offset_reg(base) (base + 0x04)
26#define msix_pba_offset_reg(base) (base + 0x08)
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
Hidetoshi Seto04846b52009-04-20 10:54:52 +090028#define multi_msix_capable(control) msix_table_size((control))
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#endif /* MSI_H */