Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 1 | /* 10G controller driver for Samsung SoCs |
| 2 | * |
| 3 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * Author: Siva Reddy Kallam <siva.kallam@samsung.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | #ifndef __SXGBE_DESC_H__ |
| 13 | #define __SXGBE_DESC_H__ |
| 14 | |
| 15 | #define SXGBE_DESC_SIZE_BYTES 16 |
| 16 | |
| 17 | /* forward declaration */ |
| 18 | struct sxgbe_extra_stats; |
| 19 | |
| 20 | /* Transmit checksum insertion control */ |
| 21 | enum tdes_csum_insertion { |
| 22 | cic_disabled = 0, /* Checksum Insertion Control */ |
| 23 | cic_only_ip = 1, /* Only IP header */ |
| 24 | /* IP header but pseudoheader is not calculated */ |
| 25 | cic_no_pseudoheader = 2, |
| 26 | cic_full = 3, /* IP header and pseudoheader */ |
| 27 | }; |
| 28 | |
| 29 | struct sxgbe_tx_norm_desc { |
| 30 | u64 tdes01; /* buf1 address */ |
| 31 | union { |
| 32 | /* TX Read-Format Desc 2,3 */ |
| 33 | struct { |
| 34 | /* TDES2 */ |
| 35 | u32 buf1_size:14; |
| 36 | u32 vlan_tag_ctl:2; |
| 37 | u32 buf2_size:14; |
| 38 | u32 timestmp_enable:1; |
| 39 | u32 int_on_com:1; |
| 40 | /* TDES3 */ |
| 41 | union { |
Byungho An | 3ee2b7c | 2014-04-18 20:59:36 +0900 | [diff] [blame] | 42 | u16 tcp_payload_len; |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 43 | struct { |
| 44 | u32 total_pkt_len:15; |
| 45 | u32 reserved1:1; |
Byungho An | 3ee2b7c | 2014-04-18 20:59:36 +0900 | [diff] [blame] | 46 | } pkt_len; |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 47 | } tx_pkt_len; |
| 48 | |
Byungho An | 3ee2b7c | 2014-04-18 20:59:36 +0900 | [diff] [blame] | 49 | u16 cksum_ctl:2; |
| 50 | u16 tse_bit:1; |
| 51 | u16 tcp_hdr_len:4; |
| 52 | u16 sa_insert_ctl:3; |
| 53 | u16 crc_pad_ctl:2; |
| 54 | u16 last_desc:1; |
| 55 | u16 first_desc:1; |
| 56 | u16 ctxt_bit:1; |
| 57 | u16 own_bit:1; |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 58 | } tx_rd_des23; |
| 59 | |
| 60 | /* tx write back Desc 2,3 */ |
| 61 | struct { |
| 62 | /* WB TES2 */ |
| 63 | u32 reserved1; |
| 64 | /* WB TES3 */ |
| 65 | u32 reserved2:31; |
| 66 | u32 own_bit:1; |
| 67 | } tx_wb_des23; |
| 68 | } tdes23; |
| 69 | }; |
| 70 | |
| 71 | struct sxgbe_rx_norm_desc { |
| 72 | union { |
Byungho An | 3ee2b7c | 2014-04-18 20:59:36 +0900 | [diff] [blame] | 73 | u64 rdes01; /* buf1 address */ |
| 74 | union { |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 75 | u32 out_vlan_tag:16; |
| 76 | u32 in_vlan_tag:16; |
Byungho An | 3ee2b7c | 2014-04-18 20:59:36 +0900 | [diff] [blame] | 77 | u32 rss_hash; |
| 78 | } rx_wb_des01; |
| 79 | } rdes01; |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 80 | |
| 81 | union { |
| 82 | /* RX Read format Desc 2,3 */ |
| 83 | struct{ |
| 84 | /* RDES2 */ |
Byungho An | 3ee2b7c | 2014-04-18 20:59:36 +0900 | [diff] [blame] | 85 | u64 buf2_addr:62; |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 86 | /* RDES3 */ |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 87 | u32 int_on_com:1; |
| 88 | u32 own_bit:1; |
| 89 | } rx_rd_des23; |
| 90 | |
| 91 | /* RX write back */ |
| 92 | struct{ |
| 93 | /* WB RDES2 */ |
| 94 | u32 hdr_len:10; |
| 95 | u32 rdes2_reserved:2; |
| 96 | u32 elrd_val:1; |
| 97 | u32 iovt_sel:1; |
| 98 | u32 res_pkt:1; |
| 99 | u32 vlan_filter_match:1; |
| 100 | u32 sa_filter_fail:1; |
| 101 | u32 da_filter_fail:1; |
| 102 | u32 hash_filter_pass:1; |
| 103 | u32 macaddr_filter_match:8; |
| 104 | u32 l3_filter_match:1; |
| 105 | u32 l4_filter_match:1; |
| 106 | u32 l34_filter_num:3; |
| 107 | |
| 108 | /* WB RDES3 */ |
| 109 | u32 pkt_len:14; |
| 110 | u32 rdes3_reserved:1; |
Vipul Pandya | 8f7807a | 2014-03-25 12:11:02 -0700 | [diff] [blame] | 111 | u32 err_summary:1; |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 112 | u32 err_l2_type:4; |
| 113 | u32 layer34_pkt_type:4; |
| 114 | u32 no_coagulation_pkt:1; |
| 115 | u32 in_seq_pkt:1; |
| 116 | u32 rss_valid:1; |
| 117 | u32 context_des_avail:1; |
| 118 | u32 last_desc:1; |
| 119 | u32 first_desc:1; |
| 120 | u32 recv_context_desc:1; |
| 121 | u32 own_bit:1; |
| 122 | } rx_wb_des23; |
| 123 | } rdes23; |
| 124 | }; |
| 125 | |
| 126 | /* Context descriptor structure */ |
| 127 | struct sxgbe_tx_ctxt_desc { |
| 128 | u32 tstamp_lo; |
| 129 | u32 tstamp_hi; |
| 130 | u32 maxseg_size:15; |
| 131 | u32 reserved1:1; |
| 132 | u32 ivlan_tag:16; |
| 133 | u32 vlan_tag:16; |
| 134 | u32 vltag_valid:1; |
| 135 | u32 ivlan_tag_valid:1; |
| 136 | u32 ivlan_tag_ctl:2; |
| 137 | u32 reserved2:3; |
| 138 | u32 ctxt_desc_err:1; |
| 139 | u32 reserved3:2; |
| 140 | u32 ostc:1; |
| 141 | u32 tcmssv:1; |
| 142 | u32 reserved4:2; |
| 143 | u32 ctxt_bit:1; |
| 144 | u32 own_bit:1; |
| 145 | }; |
| 146 | |
| 147 | struct sxgbe_rx_ctxt_desc { |
| 148 | u32 tstamp_lo; |
| 149 | u32 tstamp_hi; |
| 150 | u32 reserved1; |
| 151 | u32 ptp_msgtype:4; |
| 152 | u32 tstamp_available:1; |
| 153 | u32 ptp_rsp_err:1; |
| 154 | u32 tstamp_dropped:1; |
| 155 | u32 reserved2:23; |
| 156 | u32 rx_ctxt_desc:1; |
| 157 | u32 own_bit:1; |
| 158 | }; |
| 159 | |
| 160 | struct sxgbe_desc_ops { |
| 161 | /* DMA TX descriptor ring initialization */ |
| 162 | void (*init_tx_desc)(struct sxgbe_tx_norm_desc *p); |
| 163 | |
| 164 | /* Invoked by the xmit function to prepare the tx descriptor */ |
| 165 | void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse, |
Vipul Pandya | 1051125 | 2014-03-25 12:10:57 -0700 | [diff] [blame] | 166 | u32 total_hdr_len, u32 tcp_hdr_len, |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 167 | u32 tcp_payload_len); |
| 168 | |
| 169 | /* Assign buffer lengths for descriptor */ |
| 170 | void (*prepare_tx_desc)(struct sxgbe_tx_norm_desc *p, u8 is_fd, |
| 171 | int buf1_len, int pkt_len, int cksum); |
| 172 | |
| 173 | /* Set VLAN control information */ |
| 174 | void (*tx_vlanctl_desc)(struct sxgbe_tx_norm_desc *p, int vlan_ctl); |
| 175 | |
| 176 | /* Set the owner of the descriptor */ |
| 177 | void (*set_tx_owner)(struct sxgbe_tx_norm_desc *p); |
| 178 | |
| 179 | /* Get the owner of the descriptor */ |
| 180 | int (*get_tx_owner)(struct sxgbe_tx_norm_desc *p); |
| 181 | |
| 182 | /* Invoked by the xmit function to close the tx descriptor */ |
| 183 | void (*close_tx_desc)(struct sxgbe_tx_norm_desc *p); |
| 184 | |
| 185 | /* Clean the tx descriptor as soon as the tx irq is received */ |
| 186 | void (*release_tx_desc)(struct sxgbe_tx_norm_desc *p); |
| 187 | |
| 188 | /* Clear interrupt on tx frame completion. When this bit is |
| 189 | * set an interrupt happens as soon as the frame is transmitted |
| 190 | */ |
| 191 | void (*clear_tx_ic)(struct sxgbe_tx_norm_desc *p); |
| 192 | |
| 193 | /* Last tx segment reports the transmit status */ |
| 194 | int (*get_tx_ls)(struct sxgbe_tx_norm_desc *p); |
| 195 | |
| 196 | /* Get the buffer size from the descriptor */ |
| 197 | int (*get_tx_len)(struct sxgbe_tx_norm_desc *p); |
| 198 | |
| 199 | /* Set tx timestamp enable bit */ |
| 200 | void (*tx_enable_tstamp)(struct sxgbe_tx_norm_desc *p); |
| 201 | |
| 202 | /* get tx timestamp status */ |
| 203 | int (*get_tx_timestamp_status)(struct sxgbe_tx_norm_desc *p); |
| 204 | |
| 205 | /* TX Context Descripto Specific */ |
| 206 | void (*tx_ctxt_desc_set_ctxt)(struct sxgbe_tx_ctxt_desc *p); |
| 207 | |
| 208 | /* Set the owner of the TX context descriptor */ |
| 209 | void (*tx_ctxt_desc_set_owner)(struct sxgbe_tx_ctxt_desc *p); |
| 210 | |
| 211 | /* Get the owner of the TX context descriptor */ |
| 212 | int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p); |
| 213 | |
| 214 | /* Set TX mss */ |
Vipul Pandya | 1051125 | 2014-03-25 12:10:57 -0700 | [diff] [blame] | 215 | void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss); |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 216 | |
| 217 | /* Set TX mss */ |
| 218 | int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p); |
| 219 | |
| 220 | /* Set TX tcmssv */ |
| 221 | void (*tx_ctxt_desc_set_tcmssv)(struct sxgbe_tx_ctxt_desc *p); |
| 222 | |
| 223 | /* Reset TX ostc */ |
| 224 | void (*tx_ctxt_desc_reset_ostc)(struct sxgbe_tx_ctxt_desc *p); |
| 225 | |
| 226 | /* Set IVLAN information */ |
| 227 | void (*tx_ctxt_desc_set_ivlantag)(struct sxgbe_tx_ctxt_desc *p, |
| 228 | int is_ivlanvalid, int ivlan_tag, |
| 229 | int ivlan_ctl); |
| 230 | |
| 231 | /* Return IVLAN Tag */ |
| 232 | int (*tx_ctxt_desc_get_ivlantag)(struct sxgbe_tx_ctxt_desc *p); |
| 233 | |
| 234 | /* Set VLAN Tag */ |
| 235 | void (*tx_ctxt_desc_set_vlantag)(struct sxgbe_tx_ctxt_desc *p, |
| 236 | int is_vlanvalid, int vlan_tag); |
| 237 | |
| 238 | /* Return VLAN Tag */ |
| 239 | int (*tx_ctxt_desc_get_vlantag)(struct sxgbe_tx_ctxt_desc *p); |
| 240 | |
| 241 | /* Set Time stamp */ |
| 242 | void (*tx_ctxt_set_tstamp)(struct sxgbe_tx_ctxt_desc *p, |
| 243 | u8 ostc_enable, u64 tstamp); |
| 244 | |
| 245 | /* Close TX context descriptor */ |
| 246 | void (*close_tx_ctxt_desc)(struct sxgbe_tx_ctxt_desc *p); |
| 247 | |
| 248 | /* WB status of context descriptor */ |
| 249 | int (*get_tx_ctxt_cde)(struct sxgbe_tx_ctxt_desc *p); |
| 250 | |
| 251 | /* DMA RX descriptor ring initialization */ |
| 252 | void (*init_rx_desc)(struct sxgbe_rx_norm_desc *p, int disable_rx_ic, |
| 253 | int mode, int end); |
| 254 | |
| 255 | /* Get own bit */ |
| 256 | int (*get_rx_owner)(struct sxgbe_rx_norm_desc *p); |
| 257 | |
| 258 | /* Set own bit */ |
| 259 | void (*set_rx_owner)(struct sxgbe_rx_norm_desc *p); |
| 260 | |
Byungho An | 3dc638d | 2014-04-29 13:15:27 +0900 | [diff] [blame] | 261 | /* Set Interrupt on completion bit */ |
| 262 | void (*set_rx_int_on_com)(struct sxgbe_rx_norm_desc *p); |
| 263 | |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 264 | /* Get the receive frame size */ |
| 265 | int (*get_rx_frame_len)(struct sxgbe_rx_norm_desc *p); |
| 266 | |
| 267 | /* Return first Descriptor status */ |
| 268 | int (*get_rx_fd_status)(struct sxgbe_rx_norm_desc *p); |
| 269 | |
| 270 | /* Return first Descriptor status */ |
| 271 | int (*get_rx_ld_status)(struct sxgbe_rx_norm_desc *p); |
| 272 | |
| 273 | /* Return the reception status looking at the RDES1 */ |
| 274 | int (*rx_wbstatus)(struct sxgbe_rx_norm_desc *p, |
| 275 | struct sxgbe_extra_stats *x, int *checksum); |
| 276 | |
| 277 | /* Get own bit */ |
| 278 | int (*get_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p); |
| 279 | |
| 280 | /* Set own bit */ |
| 281 | void (*set_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p); |
| 282 | |
| 283 | /* Return the reception status looking at Context control information */ |
| 284 | void (*rx_ctxt_wbstatus)(struct sxgbe_rx_ctxt_desc *p, |
| 285 | struct sxgbe_extra_stats *x); |
| 286 | |
| 287 | /* Get rx timestamp status */ |
| 288 | int (*get_rx_ctxt_tstamp_status)(struct sxgbe_rx_ctxt_desc *p); |
| 289 | |
| 290 | /* Get timestamp value for rx, need to check this */ |
| 291 | u64 (*get_timestamp)(struct sxgbe_rx_ctxt_desc *p); |
| 292 | }; |
| 293 | |
| 294 | const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void); |
| 295 | |
| 296 | #endif /* __SXGBE_DESC_H__ */ |