Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 1 | /* 10G controller driver for Samsung SoCs |
| 2 | * |
| 3 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * Author: Siva Reddy Kallam <siva.kallam@samsung.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | #ifndef __SXGBE_REGMAP_H__ |
| 13 | #define __SXGBE_REGMAP_H__ |
| 14 | |
| 15 | /* SXGBE MAC Registers */ |
| 16 | #define SXGBE_CORE_TX_CONFIG_REG 0x0000 |
| 17 | #define SXGBE_CORE_RX_CONFIG_REG 0x0004 |
| 18 | #define SXGBE_CORE_PKT_FILTER_REG 0x0008 |
| 19 | #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C |
| 20 | #define SXGBE_CORE_HASH_TABLE_REG0 0x0010 |
| 21 | #define SXGBE_CORE_HASH_TABLE_REG1 0x0014 |
| 22 | #define SXGBE_CORE_HASH_TABLE_REG2 0x0018 |
| 23 | #define SXGBE_CORE_HASH_TABLE_REG3 0x001C |
| 24 | #define SXGBE_CORE_HASH_TABLE_REG4 0x0020 |
| 25 | #define SXGBE_CORE_HASH_TABLE_REG5 0x0024 |
| 26 | #define SXGBE_CORE_HASH_TABLE_REG6 0x0028 |
| 27 | #define SXGBE_CORE_HASH_TABLE_REG7 0x002C |
Girish K S | acc18c1 | 2014-03-25 12:10:57 -0700 | [diff] [blame] | 28 | |
| 29 | /* EEE-LPI Registers */ |
| 30 | #define SXGBE_CORE_LPI_CTRL_STATUS 0x00D0 |
| 31 | #define SXGBE_CORE_LPI_TIMER_CTRL 0x00D4 |
| 32 | |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 33 | /* VLAN Specific Registers */ |
| 34 | #define SXGBE_CORE_VLAN_TAG_REG 0x0050 |
| 35 | #define SXGBE_CORE_VLAN_HASHTAB_REG 0x0058 |
| 36 | #define SXGBE_CORE_VLAN_INSCTL_REG 0x0060 |
| 37 | #define SXGBE_CORE_VLAN_INNERCTL_REG 0x0064 |
| 38 | #define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C |
| 39 | |
| 40 | /* Flow Contol Registers */ |
| 41 | #define SXGBE_CORE_TX_Q0_FLOWCTL_REG 0x0070 |
| 42 | #define SXGBE_CORE_TX_Q1_FLOWCTL_REG 0x0074 |
| 43 | #define SXGBE_CORE_TX_Q2_FLOWCTL_REG 0x0078 |
| 44 | #define SXGBE_CORE_TX_Q3_FLOWCTL_REG 0x007C |
| 45 | #define SXGBE_CORE_TX_Q4_FLOWCTL_REG 0x0080 |
| 46 | #define SXGBE_CORE_TX_Q5_FLOWCTL_REG 0x0084 |
| 47 | #define SXGBE_CORE_TX_Q6_FLOWCTL_REG 0x0088 |
| 48 | #define SXGBE_CORE_TX_Q7_FLOWCTL_REG 0x008C |
| 49 | #define SXGBE_CORE_RX_FLOWCTL_REG 0x0090 |
| 50 | #define SXGBE_CORE_RX_CTL0_REG 0x00A0 |
| 51 | #define SXGBE_CORE_RX_CTL1_REG 0x00A4 |
| 52 | #define SXGBE_CORE_RX_CTL2_REG 0x00A8 |
| 53 | #define SXGBE_CORE_RX_CTL3_REG 0x00AC |
| 54 | |
Byungho An | 325b94f | 2014-04-29 13:15:17 +0900 | [diff] [blame] | 55 | #define SXGBE_CORE_RXQ_ENABLE_MASK 0x0003 |
| 56 | #define SXGBE_CORE_RXQ_ENABLE 0x0002 |
| 57 | #define SXGBE_CORE_RXQ_DISABLE 0x0000 |
| 58 | |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 59 | /* Interrupt Registers */ |
| 60 | #define SXGBE_CORE_INT_STATUS_REG 0x00B0 |
| 61 | #define SXGBE_CORE_INT_ENABLE_REG 0x00B4 |
| 62 | #define SXGBE_CORE_RXTX_ERR_STATUS_REG 0x00B8 |
| 63 | #define SXGBE_CORE_PMT_CTL_STATUS_REG 0x00C0 |
| 64 | #define SXGBE_CORE_RWK_PKT_FILTER_REG 0x00C4 |
| 65 | #define SXGBE_CORE_VERSION_REG 0x0110 |
| 66 | #define SXGBE_CORE_DEBUG_REG 0x0114 |
| 67 | #define SXGBE_CORE_HW_FEA_REG(index) (0x011C + index * 4) |
| 68 | |
| 69 | /* SMA(MDIO) module registers */ |
| 70 | #define SXGBE_MDIO_SCMD_ADD_REG 0x0200 |
| 71 | #define SXGBE_MDIO_SCMD_DATA_REG 0x0204 |
| 72 | #define SXGBE_MDIO_CCMD_WADD_REG 0x0208 |
| 73 | #define SXGBE_MDIO_CCMD_WDATA_REG 0x020C |
| 74 | #define SXGBE_MDIO_CSCAN_PORT_REG 0x0210 |
| 75 | #define SXGBE_MDIO_INT_STATUS_REG 0x0214 |
| 76 | #define SXGBE_MDIO_INT_ENABLE_REG 0x0218 |
| 77 | #define SXGBE_MDIO_PORT_CONDCON_REG 0x021C |
| 78 | #define SXGBE_MDIO_CLAUSE22_PORT_REG 0x0220 |
| 79 | |
| 80 | /* port specific, addr = 0-3 */ |
| 81 | #define SXGBE_MDIO_DEV_BASE_REG 0x0230 |
| 82 | #define SXGBE_MDIO_PORT_DEV_REG(addr) \ |
| 83 | (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0) |
| 84 | #define SXGBE_MDIO_PORT_LSTATUS_REG(addr) \ |
| 85 | (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4) |
| 86 | #define SXGBE_MDIO_PORT_ALIVE_REG(addr) \ |
| 87 | (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8) |
| 88 | |
| 89 | #define SXGBE_CORE_GPIO_CTL_REG 0x0278 |
| 90 | #define SXGBE_CORE_GPIO_STATUS_REG 0x027C |
| 91 | |
| 92 | /* Address registers for filtering */ |
| 93 | #define SXGBE_CORE_ADD_BASE_REG 0x0300 |
| 94 | |
| 95 | /* addr = 0-31 */ |
| 96 | #define SXGBE_CORE_ADD_HIGHOFFSET(addr) \ |
| 97 | (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0) |
| 98 | #define SXGBE_CORE_ADD_LOWOFFSET(addr) \ |
| 99 | (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4) |
| 100 | |
| 101 | /* SXGBE MMC registers */ |
| 102 | #define SXGBE_MMC_CTL_REG 0x0800 |
| 103 | #define SXGBE_MMC_RXINT_STATUS_REG 0x0804 |
| 104 | #define SXGBE_MMC_TXINT_STATUS_REG 0x0808 |
| 105 | #define SXGBE_MMC_RXINT_ENABLE_REG 0x080C |
| 106 | #define SXGBE_MMC_TXINT_ENABLE_REG 0x0810 |
| 107 | |
| 108 | /* TX specific counters */ |
| 109 | #define SXGBE_MMC_TXOCTETHI_GBCNT_REG 0x0814 |
| 110 | #define SXGBE_MMC_TXOCTETLO_GBCNT_REG 0x0818 |
| 111 | #define SXGBE_MMC_TXFRAMELO_GBCNT_REG 0x081C |
| 112 | #define SXGBE_MMC_TXFRAMEHI_GBCNT_REG 0x0820 |
| 113 | #define SXGBE_MMC_TXBROADLO_GCNT_REG 0x0824 |
| 114 | #define SXGBE_MMC_TXBROADHI_GCNT_REG 0x0828 |
| 115 | #define SXGBE_MMC_TXMULTILO_GCNT_REG 0x082C |
| 116 | #define SXGBE_MMC_TXMULTIHI_GCNT_REG 0x0830 |
| 117 | #define SXGBE_MMC_TX64LO_GBCNT_REG 0x0834 |
| 118 | #define SXGBE_MMC_TX64HI_GBCNT_REG 0x0838 |
| 119 | #define SXGBE_MMC_TX65TO127LO_GBCNT_REG 0x083C |
| 120 | #define SXGBE_MMC_TX65TO127HI_GBCNT_REG 0x0840 |
| 121 | #define SXGBE_MMC_TX128TO255LO_GBCNT_REG 0x0844 |
| 122 | #define SXGBE_MMC_TX128TO255HI_GBCNT_REG 0x0848 |
| 123 | #define SXGBE_MMC_TX256TO511LO_GBCNT_REG 0x084C |
| 124 | #define SXGBE_MMC_TX256TO511HI_GBCNT_REG 0x0850 |
| 125 | #define SXGBE_MMC_TX512TO1023LO_GBCNT_REG 0x0854 |
| 126 | #define SXGBE_MMC_TX512TO1023HI_GBCNT_REG 0x0858 |
| 127 | #define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG 0x085C |
| 128 | #define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG 0x0860 |
| 129 | #define SXGBE_MMC_TXUNICASTLO_GBCNT_REG 0x0864 |
| 130 | #define SXGBE_MMC_TXUNICASTHI_GBCNT_REG 0x0868 |
| 131 | #define SXGBE_MMC_TXMULTILO_GBCNT_REG 0x086C |
| 132 | #define SXGBE_MMC_TXMULTIHI_GBCNT_REG 0x0870 |
| 133 | #define SXGBE_MMC_TXBROADLO_GBCNT_REG 0x0874 |
| 134 | #define SXGBE_MMC_TXBROADHI_GBCNT_REG 0x0878 |
| 135 | #define SXGBE_MMC_TXUFLWLO_GBCNT_REG 0x087C |
| 136 | #define SXGBE_MMC_TXUFLWHI_GBCNT_REG 0x0880 |
| 137 | #define SXGBE_MMC_TXOCTETLO_GCNT_REG 0x0884 |
| 138 | #define SXGBE_MMC_TXOCTETHI_GCNT_REG 0x0888 |
| 139 | #define SXGBE_MMC_TXFRAMELO_GCNT_REG 0x088C |
| 140 | #define SXGBE_MMC_TXFRAMEHI_GCNT_REG 0x0890 |
| 141 | #define SXGBE_MMC_TXPAUSELO_CNT_REG 0x0894 |
| 142 | #define SXGBE_MMC_TXPAUSEHI_CNT_REG 0x0898 |
| 143 | #define SXGBE_MMC_TXVLANLO_GCNT_REG 0x089C |
| 144 | #define SXGBE_MMC_TXVLANHI_GCNT_REG 0x08A0 |
| 145 | |
| 146 | /* RX specific counters */ |
| 147 | #define SXGBE_MMC_RXFRAMELO_GBCNT_REG 0x0900 |
| 148 | #define SXGBE_MMC_RXFRAMEHI_GBCNT_REG 0x0904 |
| 149 | #define SXGBE_MMC_RXOCTETLO_GBCNT_REG 0x0908 |
| 150 | #define SXGBE_MMC_RXOCTETHI_GBCNT_REG 0x090C |
| 151 | #define SXGBE_MMC_RXOCTETLO_GCNT_REG 0x0910 |
| 152 | #define SXGBE_MMC_RXOCTETHI_GCNT_REG 0x0914 |
| 153 | #define SXGBE_MMC_RXBROADLO_GCNT_REG 0x0918 |
| 154 | #define SXGBE_MMC_RXBROADHI_GCNT_REG 0x091C |
| 155 | #define SXGBE_MMC_RXMULTILO_GCNT_REG 0x0920 |
| 156 | #define SXGBE_MMC_RXMULTIHI_GCNT_REG 0x0924 |
| 157 | #define SXGBE_MMC_RXCRCERRLO_REG 0x0928 |
| 158 | #define SXGBE_MMC_RXCRCERRHI_REG 0x092C |
| 159 | #define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG 0x0930 |
| 160 | #define SXGBE_MMC_RXJABBERERR_REG 0x0934 |
| 161 | #define SXGBE_MMC_RXSHORT64BFRAME_COR_REG 0x0938 |
| 162 | #define SXGBE_MMC_RXOVERMAXFRAME_COR_REG 0x093C |
| 163 | #define SXGBE_MMC_RX64LO_GBCNT_REG 0x0940 |
| 164 | #define SXGBE_MMC_RX64HI_GBCNT_REG 0x0944 |
| 165 | #define SXGBE_MMC_RX65TO127LO_GBCNT_REG 0x0948 |
| 166 | #define SXGBE_MMC_RX65TO127HI_GBCNT_REG 0x094C |
| 167 | #define SXGBE_MMC_RX128TO255LO_GBCNT_REG 0x0950 |
| 168 | #define SXGBE_MMC_RX128TO255HI_GBCNT_REG 0x0954 |
| 169 | #define SXGBE_MMC_RX256TO511LO_GBCNT_REG 0x0958 |
| 170 | #define SXGBE_MMC_RX256TO511HI_GBCNT_REG 0x095C |
| 171 | #define SXGBE_MMC_RX512TO1023LO_GBCNT_REG 0x0960 |
| 172 | #define SXGBE_MMC_RX512TO1023HI_GBCNT_REG 0x0964 |
| 173 | #define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG 0x0968 |
| 174 | #define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG 0x096C |
| 175 | #define SXGBE_MMC_RXUNICASTLO_GCNT_REG 0x0970 |
| 176 | #define SXGBE_MMC_RXUNICASTHI_GCNT_REG 0x0974 |
| 177 | #define SXGBE_MMC_RXLENERRLO_REG 0x0978 |
| 178 | #define SXGBE_MMC_RXLENERRHI_REG 0x097C |
| 179 | #define SXGBE_MMC_RXOUTOFRANGETYPELO_REG 0x0980 |
| 180 | #define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG 0x0984 |
| 181 | #define SXGBE_MMC_RXPAUSELO_CNT_REG 0x0988 |
| 182 | #define SXGBE_MMC_RXPAUSEHI_CNT_REG 0x098C |
| 183 | #define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG 0x0990 |
| 184 | #define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG 0x0994 |
| 185 | #define SXGBE_MMC_RXVLANLO_GBCNT_REG 0x0998 |
| 186 | #define SXGBE_MMC_RXVLANHI_GBCNT_REG 0x099C |
| 187 | #define SXGBE_MMC_RXWATCHDOG_ERR_REG 0x09A0 |
| 188 | |
| 189 | /* L3/L4 function registers */ |
| 190 | #define SXGBE_CORE_L34_ADDCTL_REG 0x0C00 |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 191 | #define SXGBE_CORE_L34_DATA_REG 0x0C04 |
| 192 | |
| 193 | /* ARP registers */ |
| 194 | #define SXGBE_CORE_ARP_ADD_REG 0x0C10 |
| 195 | |
| 196 | /* RSS registers */ |
| 197 | #define SXGBE_CORE_RSS_CTL_REG 0x0C80 |
| 198 | #define SXGBE_CORE_RSS_ADD_REG 0x0C88 |
| 199 | #define SXGBE_CORE_RSS_DATA_REG 0x0C8C |
| 200 | |
Vipul Pandya | 25f72a7 | 2014-03-25 12:11:02 -0700 | [diff] [blame] | 201 | /* RSS control register bits */ |
| 202 | #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3) |
| 203 | #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2) |
| 204 | #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1) |
| 205 | #define SXGBE_CORE_RSS_CTL_RSSE BIT(0) |
| 206 | |
Siva Reddy | 1edb9ca | 2014-03-25 12:10:54 -0700 | [diff] [blame] | 207 | /* IEEE 1588 registers */ |
| 208 | #define SXGBE_CORE_TSTAMP_CTL_REG 0x0D00 |
| 209 | #define SXGBE_CORE_SUBSEC_INC_REG 0x0D04 |
| 210 | #define SXGBE_CORE_SYSTIME_SEC_REG 0x0D0C |
| 211 | #define SXGBE_CORE_SYSTIME_NSEC_REG 0x0D10 |
| 212 | #define SXGBE_CORE_SYSTIME_SECUP_REG 0x0D14 |
| 213 | #define SXGBE_CORE_TSTAMP_ADD_REG 0x0D18 |
| 214 | #define SXGBE_CORE_SYSTIME_HWORD_REG 0x0D1C |
| 215 | #define SXGBE_CORE_TSTAMP_STATUS_REG 0x0D20 |
| 216 | #define SXGBE_CORE_TXTIME_STATUSNSEC_REG 0x0D30 |
| 217 | #define SXGBE_CORE_TXTIME_STATUSSEC_REG 0x0D34 |
| 218 | |
| 219 | /* Auxiliary registers */ |
| 220 | #define SXGBE_CORE_AUX_CTL_REG 0x0D40 |
| 221 | #define SXGBE_CORE_AUX_TSTAMP_NSEC_REG 0x0D48 |
| 222 | #define SXGBE_CORE_AUX_TSTAMP_SEC_REG 0x0D4C |
| 223 | #define SXGBE_CORE_AUX_TSTAMP_INGCOR_REG 0x0D50 |
| 224 | #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_REG 0x0D54 |
| 225 | #define SXGBE_CORE_AUX_TSTAMP_INGCOR_NSEC_REG 0x0D58 |
| 226 | #define SXGBE_CORE_AUX_TSTAMP_INGCOR_SUBNSEC_REG 0x0D5C |
| 227 | #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_NSEC_REG 0x0D60 |
| 228 | #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_SUBNSEC_REG 0x0D64 |
| 229 | |
| 230 | /* PPS registers */ |
| 231 | #define SXGBE_CORE_PPS_CTL_REG 0x0D70 |
| 232 | #define SXGBE_CORE_PPS_BASE 0x0D80 |
| 233 | |
| 234 | /* addr = 0 - 3 */ |
| 235 | #define SXGBE_CORE_PPS_TTIME_SEC_REG(addr) \ |
| 236 | (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x0) |
| 237 | #define SXGBE_CORE_PPS_TTIME_NSEC_REG(addr) \ |
| 238 | (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x4) |
| 239 | #define SXGBE_CORE_PPS_INTERVAL_REG(addr) \ |
| 240 | (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x8) |
| 241 | #define SXGBE_CORE_PPS_WIDTH_REG(addr) \ |
| 242 | (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0xC) |
| 243 | #define SXGBE_CORE_PTO_CTL_REG 0x0DC0 |
| 244 | #define SXGBE_CORE_SRCPORT_ITY0_REG 0x0DC4 |
| 245 | #define SXGBE_CORE_SRCPORT_ITY1_REG 0x0DC8 |
| 246 | #define SXGBE_CORE_SRCPORT_ITY2_REG 0x0DCC |
| 247 | #define SXGBE_CORE_LOGMSG_LEVEL_REG 0x0DD0 |
| 248 | |
| 249 | /* SXGBE MTL Registers */ |
| 250 | #define SXGBE_MTL_BASE_REG 0x1000 |
| 251 | #define SXGBE_MTL_OP_MODE_REG (SXGBE_MTL_BASE_REG + 0x0000) |
| 252 | #define SXGBE_MTL_DEBUG_CTL_REG (SXGBE_MTL_BASE_REG + 0x0008) |
| 253 | #define SXGBE_MTL_DEBUG_STATUS_REG (SXGBE_MTL_BASE_REG + 0x000C) |
| 254 | #define SXGBE_MTL_FIFO_DEBUGDATA_REG (SXGBE_MTL_BASE_REG + 0x0010) |
| 255 | #define SXGBE_MTL_INT_STATUS_REG (SXGBE_MTL_BASE_REG + 0x0020) |
| 256 | #define SXGBE_MTL_RXQ_DMAMAP0_REG (SXGBE_MTL_BASE_REG + 0x0030) |
| 257 | #define SXGBE_MTL_RXQ_DMAMAP1_REG (SXGBE_MTL_BASE_REG + 0x0034) |
| 258 | #define SXGBE_MTL_RXQ_DMAMAP2_REG (SXGBE_MTL_BASE_REG + 0x0038) |
| 259 | #define SXGBE_MTL_TX_PRTYMAP0_REG (SXGBE_MTL_BASE_REG + 0x0040) |
| 260 | #define SXGBE_MTL_TX_PRTYMAP1_REG (SXGBE_MTL_BASE_REG + 0x0044) |
| 261 | |
| 262 | /* TC/Queue registers, qnum=0-15 */ |
| 263 | #define SXGBE_MTL_TC_TXBASE_REG (SXGBE_MTL_BASE_REG + 0x0100) |
| 264 | #define SXGBE_MTL_TXQ_OPMODE_REG(qnum) \ |
| 265 | (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x00) |
| 266 | #define SXGBE_MTL_SFMODE BIT(1) |
| 267 | #define SXGBE_MTL_FIFO_LSHIFT 16 |
| 268 | #define SXGBE_MTL_ENABLE_QUEUE 0x00000008 |
| 269 | #define SXGBE_MTL_TXQ_UNDERFLOW_REG(qnum) \ |
| 270 | (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x04) |
| 271 | #define SXGBE_MTL_TXQ_DEBUG_REG(qnum) \ |
| 272 | (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x08) |
| 273 | #define SXGBE_MTL_TXQ_ETSCTL_REG(qnum) \ |
| 274 | (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x10) |
| 275 | #define SXGBE_MTL_TXQ_ETSSTATUS_REG(qnum) \ |
| 276 | (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x14) |
| 277 | #define SXGBE_MTL_TXQ_QUANTWEIGHT_REG(qnum) \ |
| 278 | (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x18) |
| 279 | |
| 280 | #define SXGBE_MTL_TC_RXBASE_REG 0x1140 |
| 281 | #define SXGBE_RX_MTL_SFMODE BIT(5) |
| 282 | #define SXGBE_MTL_RXQ_OPMODE_REG(qnum) \ |
| 283 | (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x00) |
| 284 | #define SXGBE_MTL_RXQ_MISPKTOVERFLOW_REG(qnum) \ |
| 285 | (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x04) |
| 286 | #define SXGBE_MTL_RXQ_DEBUG_REG(qnum) \ |
| 287 | (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x08) |
| 288 | #define SXGBE_MTL_RXQ_CTL_REG(qnum) \ |
| 289 | (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x0C) |
| 290 | #define SXGBE_MTL_RXQ_INTENABLE_REG(qnum) \ |
| 291 | (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x30) |
| 292 | #define SXGBE_MTL_RXQ_INTSTATUS_REG(qnum) \ |
| 293 | (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x34) |
| 294 | |
| 295 | /* SXGBE DMA Registers */ |
| 296 | #define SXGBE_DMA_BASE_REG 0x3000 |
| 297 | #define SXGBE_DMA_MODE_REG (SXGBE_DMA_BASE_REG + 0x0000) |
| 298 | #define SXGBE_DMA_SOFT_RESET BIT(0) |
| 299 | #define SXGBE_DMA_SYSBUS_MODE_REG (SXGBE_DMA_BASE_REG + 0x0004) |
| 300 | #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0) |
| 301 | #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11) |
| 302 | #define SXGBE_DMA_INT_STATUS_REG (SXGBE_DMA_BASE_REG + 0x0008) |
| 303 | #define SXGBE_DMA_AXI_ARCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0010) |
| 304 | #define SXGBE_DMA_AXI_AWCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0018) |
| 305 | #define SXGBE_DMA_DEBUG_STATUS0_REG (SXGBE_DMA_BASE_REG + 0x0020) |
| 306 | #define SXGBE_DMA_DEBUG_STATUS1_REG (SXGBE_DMA_BASE_REG + 0x0024) |
| 307 | #define SXGBE_DMA_DEBUG_STATUS2_REG (SXGBE_DMA_BASE_REG + 0x0028) |
| 308 | #define SXGBE_DMA_DEBUG_STATUS3_REG (SXGBE_DMA_BASE_REG + 0x002C) |
| 309 | #define SXGBE_DMA_DEBUG_STATUS4_REG (SXGBE_DMA_BASE_REG + 0x0030) |
| 310 | #define SXGBE_DMA_DEBUG_STATUS5_REG (SXGBE_DMA_BASE_REG + 0x0034) |
| 311 | |
| 312 | /* Channel Registers, cha_num = 0-15 */ |
| 313 | #define SXGBE_DMA_CHA_BASE_REG \ |
| 314 | (SXGBE_DMA_BASE_REG + 0x0100) |
| 315 | #define SXGBE_DMA_CHA_CTL_REG(cha_num) \ |
| 316 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x00) |
| 317 | #define SXGBE_DMA_PBL_X8MODE BIT(16) |
| 318 | #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE BIT(12) |
| 319 | #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) \ |
| 320 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x04) |
| 321 | #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) \ |
| 322 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x08) |
| 323 | #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) \ |
| 324 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x10) |
| 325 | #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) \ |
| 326 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x14) |
| 327 | #define SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num) \ |
| 328 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x18) |
| 329 | #define SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num) \ |
| 330 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x1C) |
| 331 | #define SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num) \ |
| 332 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x24) |
| 333 | #define SXGBE_DMA_CHA_RXDESC_TAILPTR_REG(cha_num) \ |
| 334 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x2C) |
| 335 | #define SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num) \ |
| 336 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x30) |
| 337 | #define SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num) \ |
| 338 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x34) |
| 339 | #define SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num) \ |
| 340 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x38) |
| 341 | #define SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(cha_num) \ |
| 342 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x3C) |
| 343 | #define SXGBE_DMA_CHA_TXDESC_CURADDLO_REG(cha_num) \ |
| 344 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x44) |
| 345 | #define SXGBE_DMA_CHA_RXDESC_CURADDLO_REG(cha_num) \ |
| 346 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x4C) |
| 347 | #define SXGBE_DMA_CHA_CURTXBUF_ADDHI_REG(cha_num) \ |
| 348 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x50) |
| 349 | #define SXGBE_DMA_CHA_CURTXBUF_ADDLO_REG(cha_num) \ |
| 350 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x54) |
| 351 | #define SXGBE_DMA_CHA_CURRXBUF_ADDHI_REG(cha_num) \ |
| 352 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x58) |
| 353 | #define SXGBE_DMA_CHA_CURRXBUF_ADDLO_REG(cha_num) \ |
| 354 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x5C) |
| 355 | #define SXGBE_DMA_CHA_STATUS_REG(cha_num) \ |
| 356 | (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x60) |
| 357 | |
| 358 | /* TX DMA control register specific */ |
| 359 | #define SXGBE_TX_START_DMA BIT(0) |
| 360 | |
| 361 | /* sxgbe tx configuration register bitfields */ |
| 362 | #define SXGBE_SPEED_10G 0x0 |
| 363 | #define SXGBE_SPEED_2_5G 0x1 |
| 364 | #define SXGBE_SPEED_1G 0x2 |
| 365 | #define SXGBE_SPEED_LSHIFT 29 |
| 366 | |
| 367 | #define SXGBE_TX_ENABLE BIT(0) |
| 368 | #define SXGBE_TX_DISDIC_ALGO BIT(1) |
| 369 | #define SXGBE_TX_JABBER_DISABLE BIT(16) |
| 370 | |
| 371 | /* sxgbe rx configuration register bitfields */ |
| 372 | #define SXGBE_RX_ENABLE BIT(0) |
| 373 | #define SXGBE_RX_ACS_ENABLE BIT(1) |
| 374 | #define SXGBE_RX_WATCHDOG_DISABLE BIT(7) |
| 375 | #define SXGBE_RX_JUMBPKT_ENABLE BIT(8) |
| 376 | #define SXGBE_RX_CSUMOFFLOAD_ENABLE BIT(9) |
| 377 | #define SXGBE_RX_LOOPBACK_ENABLE BIT(10) |
| 378 | #define SXGBE_RX_ARPOFFLOAD_ENABLE BIT(31) |
| 379 | |
| 380 | /* sxgbe vlan Tag Register bitfields */ |
| 381 | #define SXGBE_VLAN_SVLAN_ENABLE BIT(18) |
| 382 | #define SXGBE_VLAN_DOUBLEVLAN_ENABLE BIT(26) |
| 383 | #define SXGBE_VLAN_INNERVLAN_ENABLE BIT(27) |
| 384 | |
| 385 | /* XMAC VLAN Tag Inclusion Register(0x0060) bitfields |
| 386 | * Below fields same for Inner VLAN Tag Inclusion |
| 387 | * Register(0x0064) register |
| 388 | */ |
| 389 | enum vlan_tag_ctl_tx { |
| 390 | VLAN_TAG_TX_NOP, |
| 391 | VLAN_TAG_TX_DEL, |
| 392 | VLAN_TAG_TX_INSERT, |
| 393 | VLAN_TAG_TX_REPLACE |
| 394 | }; |
| 395 | #define SXGBE_VLAN_PRTY_CTL BIT(18) |
| 396 | #define SXGBE_VLAN_CSVL_CTL BIT(19) |
| 397 | |
| 398 | /* SXGBE TX Q Flow Control Register bitfields */ |
| 399 | #define SXGBE_TX_FLOW_CTL_FCB BIT(0) |
| 400 | #define SXGBE_TX_FLOW_CTL_TFB BIT(1) |
| 401 | |
| 402 | /* SXGBE RX Q Flow Control Register bitfields */ |
| 403 | #define SXGBE_RX_FLOW_CTL_ENABLE BIT(0) |
| 404 | #define SXGBE_RX_UNICAST_DETECT BIT(1) |
| 405 | #define SXGBE_RX_PRTYFLOW_CTL_ENABLE BIT(8) |
| 406 | |
| 407 | /* sxgbe rx Q control0 register bitfields */ |
| 408 | #define SXGBE_RX_Q_ENABLE 0x2 |
| 409 | |
| 410 | /* SXGBE hardware features bitfield specific */ |
| 411 | /* Capability Register 0 */ |
| 412 | #define SXGBE_HW_FEAT_GMII(cap) ((cap & 0x00000002) >> 1) |
| 413 | #define SXGBE_HW_FEAT_VLAN_HASH_FILTER(cap) ((cap & 0x00000010) >> 4) |
| 414 | #define SXGBE_HW_FEAT_SMA(cap) ((cap & 0x00000020) >> 5) |
| 415 | #define SXGBE_HW_FEAT_PMT_TEMOTE_WOP(cap) ((cap & 0x00000040) >> 6) |
| 416 | #define SXGBE_HW_FEAT_PMT_MAGIC_PKT(cap) ((cap & 0x00000080) >> 7) |
| 417 | #define SXGBE_HW_FEAT_RMON(cap) ((cap & 0x00000100) >> 8) |
| 418 | #define SXGBE_HW_FEAT_ARP_OFFLOAD(cap) ((cap & 0x00000200) >> 9) |
| 419 | #define SXGBE_HW_FEAT_IEEE1500_2008(cap) ((cap & 0x00001000) >> 12) |
| 420 | #define SXGBE_HW_FEAT_EEE(cap) ((cap & 0x00002000) >> 13) |
| 421 | #define SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(cap) ((cap & 0x00004000) >> 14) |
| 422 | #define SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(cap) ((cap & 0x00010000) >> 16) |
| 423 | #define SXGBE_HW_FEAT_MACADDR_COUNT(cap) ((cap & 0x007C0000) >> 18) |
| 424 | #define SXGBE_HW_FEAT_TSTMAP_SRC(cap) ((cap & 0x06000000) >> 25) |
| 425 | #define SXGBE_HW_FEAT_SRCADDR_VLAN(cap) ((cap & 0x08000000) >> 27) |
| 426 | |
| 427 | /* Capability Register 1 */ |
| 428 | #define SXGBE_HW_FEAT_RX_FIFO_SIZE(cap) ((cap & 0x0000001F)) |
| 429 | #define SXGBE_HW_FEAT_TX_FIFO_SIZE(cap) ((cap & 0x000007C0) >> 6) |
| 430 | #define SXGBE_HW_FEAT_IEEE1588_HWORD(cap) ((cap & 0x00002000) >> 13) |
| 431 | #define SXGBE_HW_FEAT_DCB(cap) ((cap & 0x00010000) >> 16) |
| 432 | #define SXGBE_HW_FEAT_SPLIT_HDR(cap) ((cap & 0x00020000) >> 17) |
| 433 | #define SXGBE_HW_FEAT_TSO(cap) ((cap & 0x00040000) >> 18) |
| 434 | #define SXGBE_HW_FEAT_DEBUG_MEM_IFACE(cap) ((cap & 0x00080000) >> 19) |
| 435 | #define SXGBE_HW_FEAT_RSS(cap) ((cap & 0x00100000) >> 20) |
| 436 | #define SXGBE_HW_FEAT_HASH_TABLE_SIZE(cap) ((cap & 0x03000000) >> 24) |
| 437 | #define SXGBE_HW_FEAT_L3L4_FILTER_NUM(cap) ((cap & 0x78000000) >> 27) |
| 438 | |
| 439 | /* Capability Register 2 */ |
| 440 | #define SXGBE_HW_FEAT_RX_MTL_QUEUES(cap) ((cap & 0x0000000F)) |
| 441 | #define SXGBE_HW_FEAT_TX_MTL_QUEUES(cap) ((cap & 0x000003C0) >> 6) |
| 442 | #define SXGBE_HW_FEAT_RX_DMA_CHANNELS(cap) ((cap & 0x0000F000) >> 12) |
| 443 | #define SXGBE_HW_FEAT_TX_DMA_CHANNELS(cap) ((cap & 0x003C0000) >> 18) |
| 444 | #define SXGBE_HW_FEAT_PPS_OUTPUTS(cap) ((cap & 0x07000000) >> 24) |
| 445 | #define SXGBE_HW_FEAT_AUX_SNAPSHOTS(cap) ((cap & 0x70000000) >> 28) |
| 446 | |
| 447 | /* DMAchannel interrupt enable specific */ |
| 448 | /* DMA Normal interrupt */ |
| 449 | #define SXGBE_DMA_INT_ENA_NIE BIT(16) /* Normal Summary */ |
| 450 | #define SXGBE_DMA_INT_ENA_TIE BIT(0) /* Transmit Interrupt */ |
| 451 | #define SXGBE_DMA_INT_ENA_TUE BIT(2) /* Transmit Buffer Unavailable */ |
| 452 | #define SXGBE_DMA_INT_ENA_RIE BIT(6) /* Receive Interrupt */ |
| 453 | |
| 454 | #define SXGBE_DMA_INT_NORMAL \ |
| 455 | (SXGBE_DMA_INT_ENA_NIE | SXGBE_DMA_INT_ENA_RIE | \ |
| 456 | SXGBE_DMA_INT_ENA_TIE | SXGBE_DMA_INT_ENA_TUE) |
| 457 | |
| 458 | /* DMA Abnormal interrupt */ |
| 459 | #define SXGBE_DMA_INT_ENA_AIE BIT(15) /* Abnormal Summary */ |
| 460 | #define SXGBE_DMA_INT_ENA_TSE BIT(1) /* Transmit Stopped */ |
| 461 | #define SXGBE_DMA_INT_ENA_RUE BIT(7) /* Receive Buffer Unavailable */ |
| 462 | #define SXGBE_DMA_INT_ENA_RSE BIT(8) /* Receive Stopped */ |
| 463 | #define SXGBE_DMA_INT_ENA_FBE BIT(12) /* Fatal Bus Error */ |
| 464 | #define SXGBE_DMA_INT_ENA_CDEE BIT(13) /* Context Descriptor Error */ |
| 465 | |
| 466 | #define SXGBE_DMA_INT_ABNORMAL \ |
| 467 | (SXGBE_DMA_INT_ENA_AIE | SXGBE_DMA_INT_ENA_TSE | \ |
| 468 | SXGBE_DMA_INT_ENA_RUE | SXGBE_DMA_INT_ENA_RSE | \ |
| 469 | SXGBE_DMA_INT_ENA_FBE | SXGBE_DMA_INT_ENA_CDEE) |
| 470 | |
| 471 | #define SXGBE_DMA_ENA_INT (SXGBE_DMA_INT_NORMAL | SXGBE_DMA_INT_ABNORMAL) |
| 472 | |
| 473 | /* DMA channel interrupt status specific */ |
| 474 | #define SXGBE_DMA_INT_STATUS_REB2 BIT(21) |
| 475 | #define SXGBE_DMA_INT_STATUS_REB1 BIT(20) |
| 476 | #define SXGBE_DMA_INT_STATUS_REB0 BIT(19) |
| 477 | #define SXGBE_DMA_INT_STATUS_TEB2 BIT(18) |
| 478 | #define SXGBE_DMA_INT_STATUS_TEB1 BIT(17) |
| 479 | #define SXGBE_DMA_INT_STATUS_TEB0 BIT(16) |
| 480 | #define SXGBE_DMA_INT_STATUS_NIS BIT(15) |
| 481 | #define SXGBE_DMA_INT_STATUS_AIS BIT(14) |
| 482 | #define SXGBE_DMA_INT_STATUS_CTXTERR BIT(13) |
| 483 | #define SXGBE_DMA_INT_STATUS_FBE BIT(12) |
| 484 | #define SXGBE_DMA_INT_STATUS_RPS BIT(8) |
| 485 | #define SXGBE_DMA_INT_STATUS_RBU BIT(7) |
| 486 | #define SXGBE_DMA_INT_STATUS_RI BIT(6) |
| 487 | #define SXGBE_DMA_INT_STATUS_TBU BIT(2) |
| 488 | #define SXGBE_DMA_INT_STATUS_TPS BIT(1) |
| 489 | #define SXGBE_DMA_INT_STATUS_TI BIT(0) |
| 490 | |
| 491 | #endif /* __SXGBE_REGMAP_H__ */ |