Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/cris/arch-v32/drivers/nandflash.c |
| 3 | * |
| 4 | * Copyright (c) 2004 |
| 5 | * |
| 6 | * Derived from drivers/mtd/nand/spia.c |
| 7 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
| 8 | * |
| 9 | * $Id: nandflash.c,v 1.3 2005/06/01 10:57:12 starvik Exp $ |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <linux/version.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/mtd/mtd.h> |
| 22 | #include <linux/mtd/nand.h> |
| 23 | #include <linux/mtd/partitions.h> |
| 24 | #include <asm/arch/memmap.h> |
| 25 | #include <asm/arch/hwregs/reg_map.h> |
| 26 | #include <asm/arch/hwregs/reg_rdwr.h> |
| 27 | #include <asm/arch/hwregs/gio_defs.h> |
| 28 | #include <asm/arch/hwregs/bif_core_defs.h> |
| 29 | #include <asm/io.h> |
| 30 | |
| 31 | #define CE_BIT 4 |
| 32 | #define CLE_BIT 5 |
| 33 | #define ALE_BIT 6 |
| 34 | #define BY_BIT 7 |
| 35 | |
| 36 | static struct mtd_info *crisv32_mtd = NULL; |
| 37 | /* |
| 38 | * hardware specific access to control-lines |
| 39 | */ |
| 40 | static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd) |
| 41 | { |
| 42 | unsigned long flags; |
| 43 | reg_gio_rw_pa_dout dout = REG_RD(gio, regi_gio, rw_pa_dout); |
| 44 | |
| 45 | local_irq_save(flags); |
| 46 | switch(cmd){ |
| 47 | case NAND_CTL_SETCLE: |
| 48 | dout.data |= (1<<CLE_BIT); |
| 49 | break; |
| 50 | case NAND_CTL_CLRCLE: |
| 51 | dout.data &= ~(1<<CLE_BIT); |
| 52 | break; |
| 53 | case NAND_CTL_SETALE: |
| 54 | dout.data |= (1<<ALE_BIT); |
| 55 | break; |
| 56 | case NAND_CTL_CLRALE: |
| 57 | dout.data &= ~(1<<ALE_BIT); |
| 58 | break; |
| 59 | case NAND_CTL_SETNCE: |
| 60 | dout.data |= (1<<CE_BIT); |
| 61 | break; |
| 62 | case NAND_CTL_CLRNCE: |
| 63 | dout.data &= ~(1<<CE_BIT); |
| 64 | break; |
| 65 | } |
| 66 | REG_WR(gio, regi_gio, rw_pa_dout, dout); |
| 67 | local_irq_restore(flags); |
| 68 | } |
| 69 | |
| 70 | /* |
| 71 | * read device ready pin |
| 72 | */ |
| 73 | int crisv32_device_ready(struct mtd_info *mtd) |
| 74 | { |
| 75 | reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); |
| 76 | return ((din.data & (1 << BY_BIT)) >> BY_BIT); |
| 77 | } |
| 78 | |
| 79 | /* |
| 80 | * Main initialization routine |
| 81 | */ |
| 82 | struct mtd_info* __init crisv32_nand_flash_probe (void) |
| 83 | { |
| 84 | void __iomem *read_cs; |
| 85 | void __iomem *write_cs; |
| 86 | |
| 87 | reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg); |
| 88 | reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); |
| 89 | struct nand_chip *this; |
| 90 | int err = 0; |
| 91 | |
| 92 | /* Allocate memory for MTD device structure and private data */ |
| 93 | crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), |
| 94 | GFP_KERNEL); |
| 95 | if (!crisv32_mtd) { |
| 96 | printk ("Unable to allocate CRISv32 NAND MTD device structure.\n"); |
| 97 | err = -ENOMEM; |
| 98 | return NULL; |
| 99 | } |
| 100 | |
| 101 | read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192); |
| 102 | write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192); |
| 103 | |
| 104 | if (!read_cs || !write_cs) { |
| 105 | printk("CRISv32 NAND ioremap failed\n"); |
| 106 | err = -EIO; |
| 107 | goto out_mtd; |
| 108 | } |
| 109 | |
| 110 | /* Get pointer to private data */ |
| 111 | this = (struct nand_chip *) (&crisv32_mtd[1]); |
| 112 | |
| 113 | pa_oe.oe |= 1 << CE_BIT; |
| 114 | pa_oe.oe |= 1 << ALE_BIT; |
| 115 | pa_oe.oe |= 1 << CLE_BIT; |
| 116 | pa_oe.oe &= ~ (1 << BY_BIT); |
| 117 | REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); |
| 118 | |
| 119 | bif_cfg.gated_csp0 = regk_bif_core_rd; |
| 120 | bif_cfg.gated_csp1 = regk_bif_core_wr; |
| 121 | REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); |
| 122 | |
| 123 | /* Initialize structures */ |
| 124 | memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info)); |
| 125 | memset((char *) this, 0, sizeof(struct nand_chip)); |
| 126 | |
| 127 | /* Link the private data with the MTD structure */ |
| 128 | crisv32_mtd->priv = this; |
| 129 | |
| 130 | /* Set address of NAND IO lines */ |
| 131 | this->IO_ADDR_R = read_cs; |
| 132 | this->IO_ADDR_W = write_cs; |
| 133 | this->hwcontrol = crisv32_hwcontrol; |
| 134 | this->dev_ready = crisv32_device_ready; |
| 135 | /* 20 us command delay time */ |
| 136 | this->chip_delay = 20; |
| 137 | this->eccmode = NAND_ECC_SOFT; |
| 138 | |
| 139 | /* Enable the following for a flash based bad block table */ |
| 140 | this->options = NAND_USE_FLASH_BBT; |
| 141 | |
| 142 | /* Scan to find existance of the device */ |
| 143 | if (nand_scan (crisv32_mtd, 1)) { |
| 144 | err = -ENXIO; |
| 145 | goto out_ior; |
| 146 | } |
| 147 | |
| 148 | return crisv32_mtd; |
| 149 | |
| 150 | out_ior: |
| 151 | iounmap((void *)read_cs); |
| 152 | iounmap((void *)write_cs); |
| 153 | out_mtd: |
| 154 | kfree (crisv32_mtd); |
| 155 | return NULL; |
| 156 | } |
| 157 | |