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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
eric miaoe3630db2008-03-04 11:42:26 +08004 * Generic PXA IRQ handling
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020017#include <linux/syscore_ops.h>
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080018#include <linux/io.h>
19#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Jamie Iles5a567d72011-10-08 11:20:42 +010021#include <asm/exception.h>
22
Russell Kinga09e64f2008-08-05 16:14:15 +010023#include <mach/hardware.h>
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080024#include <mach/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include "generic.h"
27
Arnd Bergmann97b09da2011-10-01 22:03:45 +020028#define IRQ_BASE io_p2v(0x40d00000)
Haojian Zhuangc482ae42009-11-02 14:02:21 -050029
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080030#define ICIP (0x000)
31#define ICMR (0x004)
32#define ICLR (0x008)
33#define ICFR (0x00c)
34#define ICPR (0x010)
35#define ICCR (0x014)
36#define ICHP (0x018)
37#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
38 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
39 (0x144 + (((i) - 64) << 2)))
Eric Miaoa551e4f2011-04-27 22:48:05 +080040#define ICHP_VAL_IRQ (1 << 31)
41#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080042#define IPR_VALID (1 << 31)
43#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
44
45#define MAX_INTERNAL_IRQS 128
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47/*
48 * This is for peripheral IRQs internal to the PXA chip.
49 */
50
eric miaof6fb7af2008-03-04 13:53:05 +080051static int pxa_internal_irq_nr;
52
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +080053static inline int cpu_has_ipr(void)
54{
55 return !cpu_is_pxa25x();
56}
57
Eric Miaoa1015a12011-01-12 16:42:24 -060058static inline void __iomem *irq_base(int i)
59{
60 static unsigned long phys_base[] = {
61 0x40d00000,
62 0x40d0009c,
63 0x40d00130,
64 };
65
Arnd Bergmann97b09da2011-10-01 22:03:45 +020066 return io_p2v(phys_base[i]);
Eric Miaoa1015a12011-01-12 16:42:24 -060067}
68
Eric Miao5d284e32011-04-27 22:48:04 +080069void pxa_mask_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070070{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010071 void __iomem *base = irq_data_get_irq_chip_data(d);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080072 uint32_t icmr = __raw_readl(base + ICMR);
73
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010074 icmr &= ~(1 << IRQ_BIT(d->irq));
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080075 __raw_writel(icmr, base + ICMR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070076}
77
Eric Miao5d284e32011-04-27 22:48:04 +080078void pxa_unmask_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070079{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010080 void __iomem *base = irq_data_get_irq_chip_data(d);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080081 uint32_t icmr = __raw_readl(base + ICMR);
82
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010083 icmr |= 1 << IRQ_BIT(d->irq);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080084 __raw_writel(icmr, base + ICMR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070085}
86
eric miaof6fb7af2008-03-04 13:53:05 +080087static struct irq_chip pxa_internal_irq_chip = {
David Brownell38c677c2006-08-01 22:26:25 +010088 .name = "SC",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010089 .irq_ack = pxa_mask_irq,
90 .irq_mask = pxa_mask_irq,
91 .irq_unmask = pxa_unmask_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070092};
93
Eric Miaoa551e4f2011-04-27 22:48:05 +080094asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
95{
96 uint32_t icip, icmr, mask;
97
98 do {
99 icip = __raw_readl(IRQ_BASE + ICIP);
100 icmr = __raw_readl(IRQ_BASE + ICMR);
101 mask = icip & icmr;
102
103 if (mask == 0)
104 break;
105
106 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
107 } while (1);
108}
109
110asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
111{
112 uint32_t ichp;
113
114 do {
115 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
116
117 if ((ichp & ICHP_VAL_IRQ) == 0)
118 break;
119
120 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
121 } while (1);
122}
123
Haojian Zhuang157d2642011-10-17 20:37:52 +0800124void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
Eric Miao53665a52007-06-06 06:36:04 +0100125{
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800126 int irq, i, n;
Eric Miao53665a52007-06-06 06:36:04 +0100127
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500128 BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
129
eric miaof6fb7af2008-03-04 13:53:05 +0800130 pxa_internal_irq_nr = irq_nr;
Eric Miao53665a52007-06-06 06:36:04 +0100131
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800132 for (n = 0; n < irq_nr; n += 32) {
Marek Vasut1b624fb2011-01-10 23:53:12 +0100133 void __iomem *base = irq_base(n >> 5);
Eric Miao53665a52007-06-06 06:36:04 +0100134
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800135 __raw_writel(0, base + ICMR); /* disable all IRQs */
136 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
137 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
138 /* initialize interrupt priority */
139 if (cpu_has_ipr())
140 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
141
142 irq = PXA_IRQ(i);
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100143 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
144 handle_level_irq);
Thomas Gleixner9323f2612011-03-24 13:29:39 +0100145 irq_set_chip_data(irq, base);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800146 set_irq_flags(irq, IRQF_VALID);
147 }
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800148 }
149
Eric Miao53665a52007-06-06 06:36:04 +0100150 /* only unmasked interrupts kick us out of idle */
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800151 __raw_writel(1, irq_base(0) + ICCR);
Eric Miao53665a52007-06-06 06:36:04 +0100152
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100153 pxa_internal_irq_chip.irq_set_wake = fn;
eric miaoc95530c2007-08-29 10:22:17 +0100154}
eric miaoc01655042008-01-28 23:00:02 +0000155
156#ifdef CONFIG_PM
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500157static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
158static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
eric miaoc01655042008-01-28 23:00:02 +0000159
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200160static int pxa_irq_suspend(void)
eric miaoc01655042008-01-28 23:00:02 +0000161{
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800162 int i;
eric miaof6fb7af2008-03-04 13:53:05 +0800163
Marek Vasut1b624fb2011-01-10 23:53:12 +0100164 for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800165 void __iomem *base = irq_base(i);
166
167 saved_icmr[i] = __raw_readl(base + ICMR);
168 __raw_writel(0, base + ICMR);
eric miaoc01655042008-01-28 23:00:02 +0000169 }
Eric Miaoc70f5a62010-01-11 20:39:37 +0800170
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +0800171 if (cpu_has_ipr()) {
Eric Miaoc70f5a62010-01-11 20:39:37 +0800172 for (i = 0; i < pxa_internal_irq_nr; i++)
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800173 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
Eric Miaoc70f5a62010-01-11 20:39:37 +0800174 }
eric miaoc01655042008-01-28 23:00:02 +0000175
176 return 0;
177}
178
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200179static void pxa_irq_resume(void)
eric miaoc01655042008-01-28 23:00:02 +0000180{
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800181 int i;
eric miaof6fb7af2008-03-04 13:53:05 +0800182
Marek Vasut1b624fb2011-01-10 23:53:12 +0100183 for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800184 void __iomem *base = irq_base(i);
185
186 __raw_writel(saved_icmr[i], base + ICMR);
187 __raw_writel(0, base + ICLR);
188 }
189
Marek Vasut57879b82011-01-10 00:29:04 +0100190 if (cpu_has_ipr())
Eric Miaoc70f5a62010-01-11 20:39:37 +0800191 for (i = 0; i < pxa_internal_irq_nr; i++)
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800192 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
Eric Miaoc70f5a62010-01-11 20:39:37 +0800193
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800194 __raw_writel(1, IRQ_BASE + ICCR);
eric miaoc01655042008-01-28 23:00:02 +0000195}
196#else
197#define pxa_irq_suspend NULL
198#define pxa_irq_resume NULL
199#endif
200
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200201struct syscore_ops pxa_irq_syscore_ops = {
eric miaoc01655042008-01-28 23:00:02 +0000202 .suspend = pxa_irq_suspend,
203 .resume = pxa_irq_resume,
204};