Lennert Buytenhek | 573a652 | 2009-11-24 19:33:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support |
| 3 | * |
| 4 | * Copyright (C) 2008 Marvell Semiconductor |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | * |
| 10 | * References: |
| 11 | * - PJ1 CPU Core Datasheet, |
| 12 | * Document ID MV-S104837-01, Rev 0.7, January 24 2008. |
| 13 | * - PJ4 CPU Core Datasheet, |
| 14 | * Document ID MV-S105190-00, Rev 0.7, March 14 2008. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/init.h> |
| 18 | #include <asm/cacheflush.h> |
Russell King | 15d07dc | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 19 | #include <asm/cp15.h> |
Lennert Buytenhek | 573a652 | 2009-11-24 19:33:52 +0200 | [diff] [blame] | 20 | #include <asm/hardware/cache-tauros2.h> |
| 21 | |
| 22 | |
| 23 | /* |
| 24 | * When Tauros2 is used on a CPU that supports the v7 hierarchical |
| 25 | * cache operations, the cache handling code in proc-v7.S takes care |
| 26 | * of everything, including handling DMA coherency. |
| 27 | * |
| 28 | * So, we only need to register outer cache operations here if we're |
| 29 | * being used on a pre-v7 CPU, and we only need to build support for |
| 30 | * outer cache operations into the kernel image if the kernel has been |
| 31 | * configured to support a pre-v7 CPU. |
| 32 | */ |
| 33 | #if __LINUX_ARM_ARCH__ < 7 |
| 34 | /* |
| 35 | * Low-level cache maintenance operations. |
| 36 | */ |
| 37 | static inline void tauros2_clean_pa(unsigned long addr) |
| 38 | { |
| 39 | __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); |
| 40 | } |
| 41 | |
| 42 | static inline void tauros2_clean_inv_pa(unsigned long addr) |
| 43 | { |
| 44 | __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); |
| 45 | } |
| 46 | |
| 47 | static inline void tauros2_inv_pa(unsigned long addr) |
| 48 | { |
| 49 | __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); |
| 50 | } |
| 51 | |
| 52 | |
| 53 | /* |
| 54 | * Linux primitives. |
| 55 | * |
| 56 | * Note that the end addresses passed to Linux primitives are |
| 57 | * noninclusive. |
| 58 | */ |
| 59 | #define CACHE_LINE_SIZE 32 |
| 60 | |
| 61 | static void tauros2_inv_range(unsigned long start, unsigned long end) |
| 62 | { |
| 63 | /* |
| 64 | * Clean and invalidate partial first cache line. |
| 65 | */ |
| 66 | if (start & (CACHE_LINE_SIZE - 1)) { |
| 67 | tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); |
| 68 | start = (start | (CACHE_LINE_SIZE - 1)) + 1; |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * Clean and invalidate partial last cache line. |
| 73 | */ |
| 74 | if (end & (CACHE_LINE_SIZE - 1)) { |
| 75 | tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); |
| 76 | end &= ~(CACHE_LINE_SIZE - 1); |
| 77 | } |
| 78 | |
| 79 | /* |
| 80 | * Invalidate all full cache lines between 'start' and 'end'. |
| 81 | */ |
| 82 | while (start < end) { |
| 83 | tauros2_inv_pa(start); |
| 84 | start += CACHE_LINE_SIZE; |
| 85 | } |
| 86 | |
| 87 | dsb(); |
| 88 | } |
| 89 | |
| 90 | static void tauros2_clean_range(unsigned long start, unsigned long end) |
| 91 | { |
| 92 | start &= ~(CACHE_LINE_SIZE - 1); |
| 93 | while (start < end) { |
| 94 | tauros2_clean_pa(start); |
| 95 | start += CACHE_LINE_SIZE; |
| 96 | } |
| 97 | |
| 98 | dsb(); |
| 99 | } |
| 100 | |
| 101 | static void tauros2_flush_range(unsigned long start, unsigned long end) |
| 102 | { |
| 103 | start &= ~(CACHE_LINE_SIZE - 1); |
| 104 | while (start < end) { |
| 105 | tauros2_clean_inv_pa(start); |
| 106 | start += CACHE_LINE_SIZE; |
| 107 | } |
| 108 | |
| 109 | dsb(); |
| 110 | } |
| 111 | #endif |
| 112 | |
| 113 | static inline u32 __init read_extra_features(void) |
| 114 | { |
| 115 | u32 u; |
| 116 | |
| 117 | __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); |
| 118 | |
| 119 | return u; |
| 120 | } |
| 121 | |
| 122 | static inline void __init write_extra_features(u32 u) |
| 123 | { |
| 124 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); |
| 125 | } |
| 126 | |
| 127 | static void __init disable_l2_prefetch(void) |
| 128 | { |
| 129 | u32 u; |
| 130 | |
| 131 | /* |
| 132 | * Read the CPU Extra Features register and verify that the |
| 133 | * Disable L2 Prefetch bit is set. |
| 134 | */ |
| 135 | u = read_extra_features(); |
| 136 | if (!(u & 0x01000000)) { |
| 137 | printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); |
| 138 | write_extra_features(u | 0x01000000); |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | static inline int __init cpuid_scheme(void) |
| 143 | { |
| 144 | extern int processor_id; |
| 145 | |
| 146 | return !!((processor_id & 0x000f0000) == 0x000f0000); |
| 147 | } |
| 148 | |
| 149 | static inline u32 __init read_mmfr3(void) |
| 150 | { |
| 151 | u32 mmfr3; |
| 152 | |
| 153 | __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3)); |
| 154 | |
| 155 | return mmfr3; |
| 156 | } |
| 157 | |
| 158 | static inline u32 __init read_actlr(void) |
| 159 | { |
| 160 | u32 actlr; |
| 161 | |
| 162 | __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); |
| 163 | |
| 164 | return actlr; |
| 165 | } |
| 166 | |
| 167 | static inline void __init write_actlr(u32 actlr) |
| 168 | { |
| 169 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); |
| 170 | } |
| 171 | |
| 172 | void __init tauros2_init(void) |
| 173 | { |
| 174 | extern int processor_id; |
| 175 | char *mode; |
| 176 | |
| 177 | disable_l2_prefetch(); |
| 178 | |
| 179 | #ifdef CONFIG_CPU_32v5 |
| 180 | if ((processor_id & 0xff0f0000) == 0x56050000) { |
| 181 | u32 feat; |
| 182 | |
| 183 | /* |
| 184 | * v5 CPUs with Tauros2 have the L2 cache enable bit |
| 185 | * located in the CPU Extra Features register. |
| 186 | */ |
| 187 | feat = read_extra_features(); |
| 188 | if (!(feat & 0x00400000)) { |
| 189 | printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); |
| 190 | write_extra_features(feat | 0x00400000); |
| 191 | } |
| 192 | |
| 193 | mode = "ARMv5"; |
| 194 | outer_cache.inv_range = tauros2_inv_range; |
| 195 | outer_cache.clean_range = tauros2_clean_range; |
| 196 | outer_cache.flush_range = tauros2_flush_range; |
| 197 | } |
| 198 | #endif |
| 199 | |
| 200 | #ifdef CONFIG_CPU_32v6 |
| 201 | /* |
| 202 | * Check whether this CPU lacks support for the v7 hierarchical |
| 203 | * cache ops. (PJ4 is in its v6 personality mode if the MMFR3 |
| 204 | * register indicates no support for the v7 hierarchical cache |
| 205 | * ops.) |
| 206 | */ |
| 207 | if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) { |
| 208 | /* |
| 209 | * When Tauros2 is used in an ARMv6 system, the L2 |
| 210 | * enable bit is in the ARMv6 ARM-mandated position |
| 211 | * (bit [26] of the System Control Register). |
| 212 | */ |
| 213 | if (!(get_cr() & 0x04000000)) { |
| 214 | printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); |
| 215 | adjust_cr(0x04000000, 0x04000000); |
| 216 | } |
| 217 | |
| 218 | mode = "ARMv6"; |
| 219 | outer_cache.inv_range = tauros2_inv_range; |
| 220 | outer_cache.clean_range = tauros2_clean_range; |
| 221 | outer_cache.flush_range = tauros2_flush_range; |
| 222 | } |
| 223 | #endif |
| 224 | |
| 225 | #ifdef CONFIG_CPU_32v7 |
| 226 | /* |
| 227 | * Check whether this CPU has support for the v7 hierarchical |
| 228 | * cache ops. (PJ4 is in its v7 personality mode if the MMFR3 |
| 229 | * register indicates support for the v7 hierarchical cache |
| 230 | * ops.) |
| 231 | * |
| 232 | * (Although strictly speaking there may exist CPUs that |
| 233 | * implement the v7 cache ops but are only ARMv6 CPUs (due to |
| 234 | * not complying with all of the other ARMv7 requirements), |
| 235 | * there are no real-life examples of Tauros2 being used on |
| 236 | * such CPUs as of yet.) |
| 237 | */ |
| 238 | if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) { |
| 239 | u32 actlr; |
| 240 | |
| 241 | /* |
| 242 | * When Tauros2 is used in an ARMv7 system, the L2 |
| 243 | * enable bit is located in the Auxiliary System Control |
| 244 | * Register (which is the only register allowed by the |
| 245 | * ARMv7 spec to contain fine-grained cache control bits). |
| 246 | */ |
| 247 | actlr = read_actlr(); |
| 248 | if (!(actlr & 0x00000002)) { |
| 249 | printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); |
| 250 | write_actlr(actlr | 0x00000002); |
| 251 | } |
| 252 | |
| 253 | mode = "ARMv7"; |
| 254 | } |
| 255 | #endif |
| 256 | |
| 257 | if (mode == NULL) { |
| 258 | printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n"); |
| 259 | return; |
| 260 | } |
| 261 | |
| 262 | printk(KERN_INFO "Tauros2: L2 cache support initialised " |
| 263 | "in %s mode.\n", mode); |
| 264 | } |