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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/include/asm-arm/hardware/SA-1111.h
3 *
4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
5 *
6 * This file contains definitions for the SA-1111 Companion Chip.
7 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
8 *
9 * Macro that calculates real address for registers in the SA-1111
10 */
11
12#ifndef _ASM_ARCH_SA1111
13#define _ASM_ARCH_SA1111
14
15#include <asm/arch/bitfield.h>
16
17/*
18 * The SA1111 is always located at virtual 0xf4000000, and is always
19 * "native" endian.
20 */
21
22#define SA1111_VBASE 0xf4000000
23
24/* Don't use these! */
25#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
26#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
27
28#ifndef __ASSEMBLY__
29#define _SA1111(x) ((x) + sa1111->resource.start)
30#endif
31
32/*
33 * 26 bits of the SA-1110 address bus are available to the SA-1111.
34 * Use these when feeding target addresses to the DMA engines.
35 */
36
37#define SA1111_ADDR_WIDTH (26)
38#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
39#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
40
41/*
42 * Don't ask the (SAC) DMA engines to move less than this amount.
43 */
44
45#define SA1111_SAC_DMA_MIN_XFER (0x800)
46
47/*
48 * SA1111 register definitions.
49 */
50#define __CCREG(x) __REGP(SA1111_VBASE + (x))
51
52#define sa1111_writel(val,addr) __raw_writel(val, addr)
53#define sa1111_readl(addr) __raw_readl(addr)
54
55/*
56 * System Bus Interface (SBI)
57 *
58 * Registers
59 * SKCR Control Register
60 * SMCR Shared Memory Controller Register
61 * SKID ID Register
62 */
63#define SA1111_SKCR 0x0000
64#define SA1111_SMCR 0x0004
65#define SA1111_SKID 0x0008
66
67#define SKCR_PLL_BYPASS (1<<0)
68#define SKCR_RCLKEN (1<<1)
69#define SKCR_SLEEP (1<<2)
70#define SKCR_DOZE (1<<3)
71#define SKCR_VCO_OFF (1<<4)
72#define SKCR_SCANTSTEN (1<<5)
73#define SKCR_CLKTSTEN (1<<6)
74#define SKCR_RDYEN (1<<7)
75#define SKCR_SELAC (1<<8)
76#define SKCR_OPPC (1<<9)
77#define SKCR_PLLTSTEN (1<<10)
78#define SKCR_USBIOTSTEN (1<<11)
79/*
80 * Don't believe the specs! Take them, throw them outside. Leave them
81 * there for a week. Spit on them. Walk on them. Stamp on them.
82 * Pour gasoline over them and finally burn them. Now think about coding.
83 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
84 * - The Feb 2001 errata (278260-010) says that the previous errata
85 * (278260-009) is wrong, and its bit actually 12, fixed in spec
86 * 278242-003.
87 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
88 * - Reality is bit 13, 1 to enable.
89 * -- rmk
90 */
91#define SKCR_OE_EN (1<<13)
92
93#define SMCR_DTIM (1<<0)
94#define SMCR_MBGE (1<<1)
95#define SMCR_DRAC_0 (1<<2)
96#define SMCR_DRAC_1 (1<<3)
97#define SMCR_DRAC_2 (1<<4)
98#define SMCR_DRAC Fld(3, 2)
99#define SMCR_CLAT (1<<5)
100
101#define SKID_SIREV_MASK (0x000000f0)
102#define SKID_MTREV_MASK (0x0000000f)
103#define SKID_ID_MASK (0xffffff00)
104#define SKID_SA1111_ID (0x690cc200)
105
106/*
107 * System Controller
108 *
109 * Registers
110 * SKPCR Power Control Register
111 * SKCDR Clock Divider Register
112 * SKAUD Audio Clock Divider Register
113 * SKPMC PS/2 Mouse Clock Divider Register
114 * SKPTC PS/2 Track Pad Clock Divider Register
115 * SKPEN0 PWM0 Enable Register
116 * SKPWM0 PWM0 Clock Register
117 * SKPEN1 PWM1 Enable Register
118 * SKPWM1 PWM1 Clock Register
119 */
120#define SA1111_SKPCR 0x0200
121#define SA1111_SKCDR 0x0204
122#define SA1111_SKAUD 0x0208
123#define SA1111_SKPMC 0x020c
124#define SA1111_SKPTC 0x0210
125#define SA1111_SKPEN0 0x0214
126#define SA1111_SKPWM0 0x0218
127#define SA1111_SKPEN1 0x021c
128#define SA1111_SKPWM1 0x0220
129
130#define SKPCR_UCLKEN (1<<0)
131#define SKPCR_ACCLKEN (1<<1)
132#define SKPCR_I2SCLKEN (1<<2)
133#define SKPCR_L3CLKEN (1<<3)
134#define SKPCR_SCLKEN (1<<4)
135#define SKPCR_PMCLKEN (1<<5)
136#define SKPCR_PTCLKEN (1<<6)
137#define SKPCR_DCLKEN (1<<7)
138#define SKPCR_PWMCLKEN (1<<8)
139
140/*
141 * USB Host controller
142 */
143#define SA1111_USB 0x0400
144
145/*
146 * Offsets from SA1111_USB_BASE
147 */
148#define SA1111_USB_STATUS 0x0118
149#define SA1111_USB_RESET 0x011c
150#define SA1111_USB_IRQTEST 0x0120
151
152#define USB_RESET_FORCEIFRESET (1 << 0)
153#define USB_RESET_FORCEHCRESET (1 << 1)
154#define USB_RESET_CLKGENRESET (1 << 2)
155#define USB_RESET_SIMSCALEDOWN (1 << 3)
156#define USB_RESET_USBINTTEST (1 << 4)
157#define USB_RESET_SLEEPSTBYEN (1 << 5)
158#define USB_RESET_PWRSENSELOW (1 << 6)
159#define USB_RESET_PWRCTRLLOW (1 << 7)
160
161#define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
162#define USB_STATUS_IRQHCIBUFFACC (1 << 8)
163#define USB_STATUS_NIRQHCIM (1 << 9)
164#define USB_STATUS_NHCIMFCLR (1 << 10)
165#define USB_STATUS_USBPWRSENSE (1 << 11)
166
167/*
168 * Serial Audio Controller
169 *
170 * Registers
171 * SACR0 Serial Audio Common Control Register
172 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
173 * SACR2 Serial Audio AC-link Control Register
174 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
175 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
176 * SASCR Serial Audio Status Clear Register
177 * L3_CAR L3 Control Bus Address Register
178 * L3_CDR L3 Control Bus Data Register
179 * ACCAR AC-link Command Address Register
180 * ACCDR AC-link Command Data Register
181 * ACSAR AC-link Status Address Register
182 * ACSDR AC-link Status Data Register
183 * SADTCS Serial Audio DMA Transmit Control/Status Register
184 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
185 * SADTCA Serial Audio DMA Transmit Buffer Count Register A
186 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
187 * SADTCB Serial Audio DMA Transmit Buffer Count Register B
188 * SADRCS Serial Audio DMA Receive Control/Status Register
189 * SADRSA Serial Audio DMA Receive Buffer Start Address A
190 * SADRCA Serial Audio DMA Receive Buffer Count Register A
191 * SADRSB Serial Audio DMA Receive Buffer Start Address B
192 * SADRCB Serial Audio DMA Receive Buffer Count Register B
193 * SAITR Serial Audio Interrupt Test Register
194 * SADR Serial Audio Data Register (16 x 32-bit)
195 */
196
197#define _SACR0 _SA1111( 0x0600 )
198#define _SACR1 _SA1111( 0x0604 )
199#define _SACR2 _SA1111( 0x0608 )
200#define _SASR0 _SA1111( 0x060c )
201#define _SASR1 _SA1111( 0x0610 )
202#define _SASCR _SA1111( 0x0618 )
203#define _L3_CAR _SA1111( 0x061c )
204#define _L3_CDR _SA1111( 0x0620 )
205#define _ACCAR _SA1111( 0x0624 )
206#define _ACCDR _SA1111( 0x0628 )
207#define _ACSAR _SA1111( 0x062c )
208#define _ACSDR _SA1111( 0x0630 )
209#define _SADTCS _SA1111( 0x0634 )
210#define _SADTSA _SA1111( 0x0638 )
211#define _SADTCA _SA1111( 0x063c )
212#define _SADTSB _SA1111( 0x0640 )
213#define _SADTCB _SA1111( 0x0644 )
214#define _SADRCS _SA1111( 0x0648 )
215#define _SADRSA _SA1111( 0x064c )
216#define _SADRCA _SA1111( 0x0650 )
217#define _SADRSB _SA1111( 0x0654 )
218#define _SADRCB _SA1111( 0x0658 )
219#define _SAITR _SA1111( 0x065c )
220#define _SADR _SA1111( 0x0680 )
221
222#define SACR0 __CCREG(0x0600)
223#define SACR1 __CCREG(0x0604)
224#define SACR2 __CCREG(0x0608)
225#define SASR0 __CCREG(0x060c)
226#define SASR1 __CCREG(0x0610)
227#define SASCR __CCREG(0x0618)
228#define L3_CAR __CCREG(0x061c)
229#define L3_CDR __CCREG(0x0620)
230#define ACCAR __CCREG(0x0624)
231#define ACCDR __CCREG(0x0628)
232#define ACSAR __CCREG(0x062c)
233#define ACSDR __CCREG(0x0630)
234#define SADTCS __CCREG(0x0634)
235#define SADTSA __CCREG(0x0638)
236#define SADTCA __CCREG(0x063c)
237#define SADTSB __CCREG(0x0640)
238#define SADTCB __CCREG(0x0644)
239#define SADRCS __CCREG(0x0648)
240#define SADRSA __CCREG(0x064c)
241#define SADRCA __CCREG(0x0650)
242#define SADRSB __CCREG(0x0654)
243#define SADRCB __CCREG(0x0658)
244#define SAITR __CCREG(0x065c)
245#define SADR __CCREG(0x0680)
246
247#define SACR0_ENB (1<<0)
248#define SACR0_BCKD (1<<2)
249#define SACR0_RST (1<<3)
250
251#define SACR1_AMSL (1<<0)
252#define SACR1_L3EN (1<<1)
253#define SACR1_L3MB (1<<2)
254#define SACR1_DREC (1<<3)
255#define SACR1_DRPL (1<<4)
256#define SACR1_ENLBF (1<<5)
257
258#define SACR2_TS3V (1<<0)
259#define SACR2_TS4V (1<<1)
260#define SACR2_WKUP (1<<2)
261#define SACR2_DREC (1<<3)
262#define SACR2_DRPL (1<<4)
263#define SACR2_ENLBF (1<<5)
264#define SACR2_RESET (1<<6)
265
266#define SASR0_TNF (1<<0)
267#define SASR0_RNE (1<<1)
268#define SASR0_BSY (1<<2)
269#define SASR0_TFS (1<<3)
270#define SASR0_RFS (1<<4)
271#define SASR0_TUR (1<<5)
272#define SASR0_ROR (1<<6)
273#define SASR0_L3WD (1<<16)
274#define SASR0_L3RD (1<<17)
275
276#define SASR1_TNF (1<<0)
277#define SASR1_RNE (1<<1)
278#define SASR1_BSY (1<<2)
279#define SASR1_TFS (1<<3)
280#define SASR1_RFS (1<<4)
281#define SASR1_TUR (1<<5)
282#define SASR1_ROR (1<<6)
283#define SASR1_CADT (1<<16)
284#define SASR1_SADR (1<<17)
285#define SASR1_RSTO (1<<18)
286#define SASR1_CLPM (1<<19)
287#define SASR1_CRDY (1<<20)
288#define SASR1_RS3V (1<<21)
289#define SASR1_RS4V (1<<22)
290
291#define SASCR_TUR (1<<5)
292#define SASCR_ROR (1<<6)
293#define SASCR_DTS (1<<16)
294#define SASCR_RDD (1<<17)
295#define SASCR_STO (1<<18)
296
297#define SADTCS_TDEN (1<<0)
298#define SADTCS_TDIE (1<<1)
299#define SADTCS_TDBDA (1<<3)
300#define SADTCS_TDSTA (1<<4)
301#define SADTCS_TDBDB (1<<5)
302#define SADTCS_TDSTB (1<<6)
303#define SADTCS_TBIU (1<<7)
304
305#define SADRCS_RDEN (1<<0)
306#define SADRCS_RDIE (1<<1)
307#define SADRCS_RDBDA (1<<3)
308#define SADRCS_RDSTA (1<<4)
309#define SADRCS_RDBDB (1<<5)
310#define SADRCS_RDSTB (1<<6)
311#define SADRCS_RBIU (1<<7)
312
313#define SAD_CS_DEN (1<<0)
314#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
315#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
316#define SAD_CS_DSTA (1<<4)
317#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
318#define SAD_CS_DSTB (1<<6)
319#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
320
321#define SAITR_TFS (1<<0)
322#define SAITR_RFS (1<<1)
323#define SAITR_TUR (1<<2)
324#define SAITR_ROR (1<<3)
325#define SAITR_CADT (1<<4)
326#define SAITR_SADR (1<<5)
327#define SAITR_RSTO (1<<6)
328#define SAITR_TDBDA (1<<8)
329#define SAITR_TDBDB (1<<9)
330#define SAITR_RDBDA (1<<10)
331#define SAITR_RDBDB (1<<11)
332
333/*
334 * General-Purpose I/O Interface
335 *
336 * Registers
337 * PA_DDR GPIO Block A Data Direction
338 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
339 * PA_SDR GPIO Block A Sleep Direction
340 * PA_SSR GPIO Block A Sleep State
341 * PB_DDR GPIO Block B Data Direction
342 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
343 * PB_SDR GPIO Block B Sleep Direction
344 * PB_SSR GPIO Block B Sleep State
345 * PC_DDR GPIO Block C Data Direction
346 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
347 * PC_SDR GPIO Block C Sleep Direction
348 * PC_SSR GPIO Block C Sleep State
349 */
350
351#define _PA_DDR _SA1111( 0x1000 )
352#define _PA_DRR _SA1111( 0x1004 )
353#define _PA_DWR _SA1111( 0x1004 )
354#define _PA_SDR _SA1111( 0x1008 )
355#define _PA_SSR _SA1111( 0x100c )
356#define _PB_DDR _SA1111( 0x1010 )
357#define _PB_DRR _SA1111( 0x1014 )
358#define _PB_DWR _SA1111( 0x1014 )
359#define _PB_SDR _SA1111( 0x1018 )
360#define _PB_SSR _SA1111( 0x101c )
361#define _PC_DDR _SA1111( 0x1020 )
362#define _PC_DRR _SA1111( 0x1024 )
363#define _PC_DWR _SA1111( 0x1024 )
364#define _PC_SDR _SA1111( 0x1028 )
365#define _PC_SSR _SA1111( 0x102c )
366
367#define SA1111_GPIO 0x1000
368
369#define SA1111_GPIO_PADDR (0x000)
370#define SA1111_GPIO_PADRR (0x004)
371#define SA1111_GPIO_PADWR (0x004)
372#define SA1111_GPIO_PASDR (0x008)
373#define SA1111_GPIO_PASSR (0x00c)
374#define SA1111_GPIO_PBDDR (0x010)
375#define SA1111_GPIO_PBDRR (0x014)
376#define SA1111_GPIO_PBDWR (0x014)
377#define SA1111_GPIO_PBSDR (0x018)
378#define SA1111_GPIO_PBSSR (0x01c)
379#define SA1111_GPIO_PCDDR (0x020)
380#define SA1111_GPIO_PCDRR (0x024)
381#define SA1111_GPIO_PCDWR (0x024)
382#define SA1111_GPIO_PCSDR (0x028)
383#define SA1111_GPIO_PCSSR (0x02c)
384
385#define GPIO_A0 (1 << 0)
386#define GPIO_A1 (1 << 1)
387#define GPIO_A2 (1 << 2)
388#define GPIO_A3 (1 << 3)
389
390#define GPIO_B0 (1 << 8)
391#define GPIO_B1 (1 << 9)
392#define GPIO_B2 (1 << 10)
393#define GPIO_B3 (1 << 11)
394#define GPIO_B4 (1 << 12)
395#define GPIO_B5 (1 << 13)
396#define GPIO_B6 (1 << 14)
397#define GPIO_B7 (1 << 15)
398
399#define GPIO_C0 (1 << 16)
400#define GPIO_C1 (1 << 17)
401#define GPIO_C2 (1 << 18)
402#define GPIO_C3 (1 << 19)
403#define GPIO_C4 (1 << 20)
404#define GPIO_C5 (1 << 21)
405#define GPIO_C6 (1 << 22)
406#define GPIO_C7 (1 << 23)
407
408/*
409 * Interrupt Controller
410 *
411 * Registers
412 * INTTEST0 Test register 0
413 * INTTEST1 Test register 1
414 * INTEN0 Interrupt Enable register 0
415 * INTEN1 Interrupt Enable register 1
416 * INTPOL0 Interrupt Polarity selection 0
417 * INTPOL1 Interrupt Polarity selection 1
418 * INTTSTSEL Interrupt source selection
419 * INTSTATCLR0 Interrupt Status/Clear 0
420 * INTSTATCLR1 Interrupt Status/Clear 1
421 * INTSET0 Interrupt source set 0
422 * INTSET1 Interrupt source set 1
423 * WAKE_EN0 Wake-up source enable 0
424 * WAKE_EN1 Wake-up source enable 1
425 * WAKE_POL0 Wake-up polarity selection 0
426 * WAKE_POL1 Wake-up polarity selection 1
427 */
428#define SA1111_INTC 0x1600
429
430/*
431 * These are offsets from the above base.
432 */
433#define SA1111_INTTEST0 0x0000
434#define SA1111_INTTEST1 0x0004
435#define SA1111_INTEN0 0x0008
436#define SA1111_INTEN1 0x000c
437#define SA1111_INTPOL0 0x0010
438#define SA1111_INTPOL1 0x0014
439#define SA1111_INTTSTSEL 0x0018
440#define SA1111_INTSTATCLR0 0x001c
441#define SA1111_INTSTATCLR1 0x0020
442#define SA1111_INTSET0 0x0024
443#define SA1111_INTSET1 0x0028
444#define SA1111_WAKEEN0 0x002c
445#define SA1111_WAKEEN1 0x0030
446#define SA1111_WAKEPOL0 0x0034
447#define SA1111_WAKEPOL1 0x0038
448
449/*
450 * PS/2 Trackpad and Mouse Interfaces
451 *
452 * Registers
453 * PS2CR Control Register
454 * PS2STAT Status Register
455 * PS2DATA Transmit/Receive Data register
456 * PS2CLKDIV Clock Division Register
457 * PS2PRECNT Clock Precount Register
458 * PS2TEST1 Test register 1
459 * PS2TEST2 Test register 2
460 * PS2TEST3 Test register 3
461 * PS2TEST4 Test register 4
462 */
463
464#define SA1111_KBD 0x0a00
465#define SA1111_MSE 0x0c00
466
467/*
468 * These are offsets from the above bases.
469 */
470#define SA1111_PS2CR 0x0000
471#define SA1111_PS2STAT 0x0004
472#define SA1111_PS2DATA 0x0008
473#define SA1111_PS2CLKDIV 0x000c
474#define SA1111_PS2PRECNT 0x0010
475
476#define PS2CR_ENA 0x08
477#define PS2CR_FKD 0x02
478#define PS2CR_FKC 0x01
479
480#define PS2STAT_STP 0x0100
481#define PS2STAT_TXE 0x0080
482#define PS2STAT_TXB 0x0040
483#define PS2STAT_RXF 0x0020
484#define PS2STAT_RXB 0x0010
485#define PS2STAT_ENA 0x0008
486#define PS2STAT_RXP 0x0004
487#define PS2STAT_KBD 0x0002
488#define PS2STAT_KBC 0x0001
489
490/*
491 * PCMCIA Interface
492 *
493 * Registers
494 * PCSR Status Register
495 * PCCR Control Register
496 * PCSSR Sleep State Register
497 */
498
499#define SA1111_PCMCIA 0x1600
500
501/*
502 * These are offsets from the above base.
503 */
504#define SA1111_PCCR 0x0000
505#define SA1111_PCSSR 0x0004
506#define SA1111_PCSR 0x0008
507
508#define PCSR_S0_READY (1<<0)
509#define PCSR_S1_READY (1<<1)
510#define PCSR_S0_DETECT (1<<2)
511#define PCSR_S1_DETECT (1<<3)
512#define PCSR_S0_VS1 (1<<4)
513#define PCSR_S0_VS2 (1<<5)
514#define PCSR_S1_VS1 (1<<6)
515#define PCSR_S1_VS2 (1<<7)
516#define PCSR_S0_WP (1<<8)
517#define PCSR_S1_WP (1<<9)
518#define PCSR_S0_BVD1 (1<<10)
519#define PCSR_S0_BVD2 (1<<11)
520#define PCSR_S1_BVD1 (1<<12)
521#define PCSR_S1_BVD2 (1<<13)
522
523#define PCCR_S0_RST (1<<0)
524#define PCCR_S1_RST (1<<1)
525#define PCCR_S0_FLT (1<<2)
526#define PCCR_S1_FLT (1<<3)
527#define PCCR_S0_PWAITEN (1<<4)
528#define PCCR_S1_PWAITEN (1<<5)
529#define PCCR_S0_PSE (1<<6)
530#define PCCR_S1_PSE (1<<7)
531
532#define PCSSR_S0_SLEEP (1<<0)
533#define PCSSR_S1_SLEEP (1<<1)
534
535
536
537
538extern struct bus_type sa1111_bus_type;
539
540#define SA1111_DEVID_SBI 0
541#define SA1111_DEVID_SK 1
542#define SA1111_DEVID_USB 2
543#define SA1111_DEVID_SAC 3
544#define SA1111_DEVID_SSP 4
545#define SA1111_DEVID_PS2 5
546#define SA1111_DEVID_GPIO 6
547#define SA1111_DEVID_INT 7
548#define SA1111_DEVID_PCMCIA 8
549
550struct sa1111_dev {
551 struct device dev;
552 unsigned int devid;
553 struct resource res;
554 void __iomem *mapbase;
555 unsigned int skpcr_mask;
556 unsigned int irq[6];
557 u64 dma_mask;
558};
559
560#define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev)
561
562#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
563#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
564
565struct sa1111_driver {
566 struct device_driver drv;
567 unsigned int devid;
568 int (*probe)(struct sa1111_dev *);
569 int (*remove)(struct sa1111_dev *);
570 int (*suspend)(struct sa1111_dev *, pm_message_t);
571 int (*resume)(struct sa1111_dev *);
572};
573
574#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
575
576#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
577
578/*
579 * These frob the SKPCR register.
580 */
581void sa1111_enable_device(struct sa1111_dev *);
582void sa1111_disable_device(struct sa1111_dev *);
583
584unsigned int sa1111_pll_clock(struct sa1111_dev *);
585
586#define SA1111_AUDIO_ACLINK 0
587#define SA1111_AUDIO_I2S 1
588
589void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
590int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
591int sa1111_get_audio_rate(struct sa1111_dev *sadev);
592
593int sa1111_check_dma_bug(dma_addr_t addr);
594
595int sa1111_driver_register(struct sa1111_driver *);
596void sa1111_driver_unregister(struct sa1111_driver *);
597
598void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir);
599void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
600void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
601
602#endif /* _ASM_ARCH_SA1111 */