Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 1 | #ifndef _ASM_ARM_FUTEX_H |
| 2 | #define _ASM_ARM_FUTEX_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
| 5 | |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 6 | #include <linux/futex.h> |
| 7 | #include <linux/uaccess.h> |
| 8 | #include <asm/errno.h> |
| 9 | |
| 10 | #define __futex_atomic_ex_table(err_reg) \ |
| 11 | "3:\n" \ |
| 12 | " .pushsection __ex_table,\"a\"\n" \ |
| 13 | " .align 3\n" \ |
| 14 | " .long 1b, 4f, 2b, 4f\n" \ |
| 15 | " .popsection\n" \ |
Ard Biesheuvel | c4a84ae | 2015-03-24 10:41:09 +0100 | [diff] [blame] | 16 | " .pushsection .text.fixup,\"ax\"\n" \ |
Will Deacon | 667d1b4 | 2012-06-15 16:49:58 +0100 | [diff] [blame] | 17 | " .align 2\n" \ |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 18 | "4: mov %0, " err_reg "\n" \ |
| 19 | " b 3b\n" \ |
| 20 | " .popsection" |
| 21 | |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 22 | #ifdef CONFIG_SMP |
Jakub Jelinek | 4732efb | 2005-09-06 15:16:25 -0700 | [diff] [blame] | 23 | |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 24 | #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 25 | ({ \ |
| 26 | unsigned int __ua_flags; \ |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 27 | smp_mb(); \ |
Will Deacon | c32ffce | 2014-02-21 17:01:48 +0100 | [diff] [blame] | 28 | prefetchw(uaddr); \ |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 29 | __ua_flags = uaccess_save_and_enable(); \ |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 30 | __asm__ __volatile__( \ |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 31 | "1: ldrex %1, [%3]\n" \ |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 32 | " " insn "\n" \ |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 33 | "2: strex %2, %0, [%3]\n" \ |
| 34 | " teq %2, #0\n" \ |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 35 | " bne 1b\n" \ |
| 36 | " mov %0, #0\n" \ |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 37 | __futex_atomic_ex_table("%5") \ |
| 38 | : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 39 | : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 40 | : "cc", "memory"); \ |
| 41 | uaccess_restore(__ua_flags); \ |
| 42 | }) |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 43 | |
| 44 | static inline int |
| 45 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
| 46 | u32 oldval, u32 newval) |
| 47 | { |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 48 | unsigned int __ua_flags; |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 49 | int ret; |
| 50 | u32 val; |
| 51 | |
| 52 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
| 53 | return -EFAULT; |
| 54 | |
| 55 | smp_mb(); |
Will Deacon | c32ffce | 2014-02-21 17:01:48 +0100 | [diff] [blame] | 56 | /* Prefetching cannot fault */ |
| 57 | prefetchw(uaddr); |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 58 | __ua_flags = uaccess_save_and_enable(); |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 59 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" |
| 60 | "1: ldrex %1, [%4]\n" |
| 61 | " teq %1, %2\n" |
| 62 | " ite eq @ explicit IT needed for the 2b label\n" |
| 63 | "2: strexeq %0, %3, [%4]\n" |
| 64 | " movne %0, #0\n" |
| 65 | " teq %0, #0\n" |
| 66 | " bne 1b\n" |
| 67 | __futex_atomic_ex_table("%5") |
| 68 | : "=&r" (ret), "=&r" (val) |
| 69 | : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) |
| 70 | : "cc", "memory"); |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 71 | uaccess_restore(__ua_flags); |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 72 | smp_mb(); |
| 73 | |
| 74 | *uval = val; |
| 75 | return ret; |
| 76 | } |
Jakub Jelinek | 4732efb | 2005-09-06 15:16:25 -0700 | [diff] [blame] | 77 | |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 78 | #else /* !SMP, we can work around lack of atomic ops by disabling preemption */ |
| 79 | |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 80 | #include <linux/preempt.h> |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 81 | #include <asm/domain.h> |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 82 | |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 83 | #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 84 | ({ \ |
| 85 | unsigned int __ua_flags = uaccess_save_and_enable(); \ |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 86 | __asm__ __volatile__( \ |
Catalin Marinas | 4e7682d | 2012-01-25 11:38:13 +0100 | [diff] [blame] | 87 | "1: " TUSER(ldr) " %1, [%3]\n" \ |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 88 | " " insn "\n" \ |
Catalin Marinas | 4e7682d | 2012-01-25 11:38:13 +0100 | [diff] [blame] | 89 | "2: " TUSER(str) " %0, [%3]\n" \ |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 90 | " mov %0, #0\n" \ |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 91 | __futex_atomic_ex_table("%5") \ |
| 92 | : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 93 | : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 94 | : "cc", "memory"); \ |
| 95 | uaccess_restore(__ua_flags); \ |
| 96 | }) |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 97 | |
| 98 | static inline int |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 99 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
| 100 | u32 oldval, u32 newval) |
| 101 | { |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 102 | unsigned int __ua_flags; |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 103 | int ret = 0; |
| 104 | u32 val; |
| 105 | |
| 106 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
| 107 | return -EFAULT; |
| 108 | |
David Hildenbrand | 39919b0 | 2015-05-11 17:52:15 +0200 | [diff] [blame] | 109 | preempt_disable(); |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 110 | __ua_flags = uaccess_save_and_enable(); |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 111 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" |
Catalin Marinas | 4e7682d | 2012-01-25 11:38:13 +0100 | [diff] [blame] | 112 | "1: " TUSER(ldr) " %1, [%4]\n" |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 113 | " teq %1, %2\n" |
| 114 | " it eq @ explicit IT needed for the 2b label\n" |
Catalin Marinas | 4e7682d | 2012-01-25 11:38:13 +0100 | [diff] [blame] | 115 | "2: " TUSER(streq) " %3, [%4]\n" |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 116 | __futex_atomic_ex_table("%5") |
| 117 | : "+r" (ret), "=&r" (val) |
| 118 | : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) |
| 119 | : "cc", "memory"); |
Russell King | 3fba7e2 | 2015-08-19 11:02:28 +0100 | [diff] [blame] | 120 | uaccess_restore(__ua_flags); |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 121 | |
| 122 | *uval = val; |
David Hildenbrand | 39919b0 | 2015-05-11 17:52:15 +0200 | [diff] [blame] | 123 | preempt_enable(); |
| 124 | |
Will Deacon | c1b0db5 | 2011-04-28 18:43:01 +0100 | [diff] [blame] | 125 | return ret; |
| 126 | } |
| 127 | |
| 128 | #endif /* !SMP */ |
| 129 | |
| 130 | static inline int |
Michel Lespinasse | 8d7718a | 2011-03-10 18:50:58 -0800 | [diff] [blame] | 131 | futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 132 | { |
| 133 | int op = (encoded_op >> 28) & 7; |
| 134 | int cmp = (encoded_op >> 24) & 15; |
| 135 | int oparg = (encoded_op << 8) >> 20; |
| 136 | int cmparg = (encoded_op << 20) >> 20; |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 137 | int oldval = 0, ret, tmp; |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 138 | |
| 139 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) |
| 140 | oparg = 1 << oparg; |
| 141 | |
Michel Lespinasse | 8d7718a | 2011-03-10 18:50:58 -0800 | [diff] [blame] | 142 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 143 | return -EFAULT; |
| 144 | |
David Hildenbrand | 388b0e0 | 2015-05-11 17:52:16 +0200 | [diff] [blame] | 145 | #ifndef CONFIG_SMP |
| 146 | preempt_disable(); |
| 147 | #endif |
| 148 | pagefault_disable(); |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 149 | |
| 150 | switch (op) { |
| 151 | case FUTEX_OP_SET: |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 152 | __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg); |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 153 | break; |
| 154 | case FUTEX_OP_ADD: |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 155 | __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg); |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 156 | break; |
| 157 | case FUTEX_OP_OR: |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 158 | __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg); |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 159 | break; |
| 160 | case FUTEX_OP_ANDN: |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 161 | __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg); |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 162 | break; |
| 163 | case FUTEX_OP_XOR: |
Will Deacon | df77abc | 2011-09-23 14:34:12 +0100 | [diff] [blame] | 164 | __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg); |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 165 | break; |
| 166 | default: |
| 167 | ret = -ENOSYS; |
| 168 | } |
| 169 | |
David Hildenbrand | 388b0e0 | 2015-05-11 17:52:16 +0200 | [diff] [blame] | 170 | pagefault_enable(); |
| 171 | #ifndef CONFIG_SMP |
| 172 | preempt_enable(); |
| 173 | #endif |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 174 | |
| 175 | if (!ret) { |
| 176 | switch (cmp) { |
| 177 | case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; |
| 178 | case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; |
| 179 | case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; |
| 180 | case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; |
| 181 | case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; |
| 182 | case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; |
| 183 | default: ret = -ENOSYS; |
| 184 | } |
| 185 | } |
| 186 | return ret; |
| 187 | } |
| 188 | |
Mikael Pettersson | e589ed2 | 2008-08-20 09:36:07 +0100 | [diff] [blame] | 189 | #endif /* __KERNEL__ */ |
| 190 | #endif /* _ASM_ARM_FUTEX_H */ |