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Magnus Damma07e1032012-05-17 15:22:23 +09001/*
2 * Emma Mobile GPIO Support - GIO
3 *
4 * Copyright (C) 2012 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/bitops.h>
29#include <linux/err.h>
30#include <linux/gpio.h>
31#include <linux/slab.h>
32#include <linux/module.h>
33#include <linux/platform_data/gpio-em.h>
34
35struct em_gio_priv {
36 void __iomem *base0;
37 void __iomem *base1;
Magnus Damma07e1032012-05-17 15:22:23 +090038 spinlock_t sense_lock;
39 struct platform_device *pdev;
40 struct gpio_chip gpio_chip;
41 struct irq_chip irq_chip;
42 struct irq_domain *irq_domain;
43};
44
45#define GIO_E1 0x00
46#define GIO_E0 0x04
47#define GIO_EM 0x04
48#define GIO_OL 0x08
49#define GIO_OH 0x0c
50#define GIO_I 0x10
51#define GIO_IIA 0x14
52#define GIO_IEN 0x18
53#define GIO_IDS 0x1c
54#define GIO_IIM 0x1c
55#define GIO_RAW 0x20
56#define GIO_MST 0x24
57#define GIO_IIR 0x28
58
59#define GIO_IDT0 0x40
60#define GIO_IDT1 0x44
61#define GIO_IDT2 0x48
62#define GIO_IDT3 0x4c
63#define GIO_RAWBL 0x50
64#define GIO_RAWBH 0x54
65#define GIO_IRBL 0x58
66#define GIO_IRBH 0x5c
67
68#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
69
70static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
71{
72 if (offs < GIO_IDT0)
73 return ioread32(p->base0 + offs);
74 else
75 return ioread32(p->base1 + (offs - GIO_IDT0));
76}
77
78static inline void em_gio_write(struct em_gio_priv *p, int offs,
79 unsigned long value)
80{
81 if (offs < GIO_IDT0)
82 iowrite32(value, p->base0 + offs);
83 else
84 iowrite32(value, p->base1 + (offs - GIO_IDT0));
85}
86
Magnus Damma07e1032012-05-17 15:22:23 +090087static void em_gio_irq_disable(struct irq_data *d)
88{
Axel Lina9f77c92012-09-04 21:58:33 +080089 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damma07e1032012-05-17 15:22:23 +090090
91 em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
92}
93
94static void em_gio_irq_enable(struct irq_data *d)
95{
Axel Lina9f77c92012-09-04 21:58:33 +080096 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damma07e1032012-05-17 15:22:23 +090097
98 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
99}
100
101#define GIO_ASYNC(x) (x + 8)
102
103static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
104 [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
105 [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
106 [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
107 [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
108 [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
109};
110
111static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
112{
113 unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
Axel Lina9f77c92012-09-04 21:58:33 +0800114 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damma07e1032012-05-17 15:22:23 +0900115 unsigned int reg, offset, shift;
116 unsigned long flags;
117 unsigned long tmp;
118
119 if (!value)
120 return -EINVAL;
121
122 offset = irqd_to_hwirq(d);
123
124 pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
125
126 /* 8 x 4 bit fields in 4 IDT registers */
127 reg = GIO_IDT(offset >> 3);
128 shift = (offset & 0x07) << 4;
129
130 spin_lock_irqsave(&p->sense_lock, flags);
131
132 /* disable the interrupt in IIA */
133 tmp = em_gio_read(p, GIO_IIA);
134 tmp &= ~BIT(offset);
135 em_gio_write(p, GIO_IIA, tmp);
136
137 /* change the sense setting in IDT */
138 tmp = em_gio_read(p, reg);
139 tmp &= ~(0xf << shift);
140 tmp |= value << shift;
141 em_gio_write(p, reg, tmp);
142
143 /* clear pending interrupts */
144 em_gio_write(p, GIO_IIR, BIT(offset));
145
146 /* enable the interrupt in IIA */
147 tmp = em_gio_read(p, GIO_IIA);
148 tmp |= BIT(offset);
149 em_gio_write(p, GIO_IIA, tmp);
150
151 spin_unlock_irqrestore(&p->sense_lock, flags);
152
153 return 0;
154}
155
156static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
157{
158 struct em_gio_priv *p = dev_id;
159 unsigned long pending;
160 unsigned int offset, irqs_handled = 0;
161
162 while ((pending = em_gio_read(p, GIO_MST))) {
163 offset = __ffs(pending);
164 em_gio_write(p, GIO_IIR, BIT(offset));
165 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
166 irqs_handled++;
167 }
168
169 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
170}
171
172static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
173{
174 return container_of(chip, struct em_gio_priv, gpio_chip);
175}
176
177static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
178{
179 em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
180 return 0;
181}
182
183static int em_gio_get(struct gpio_chip *chip, unsigned offset)
184{
185 return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
186}
187
188static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
189 unsigned shift, int value)
190{
191 /* upper 16 bits contains mask and lower 16 actual value */
192 em_gio_write(gpio_to_priv(chip), reg,
193 (1 << (shift + 16)) | (value << shift));
194}
195
196static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
197{
198 /* output is split into two registers */
199 if (offset < 16)
200 __em_gio_set(chip, GIO_OL, offset, value);
201 else
202 __em_gio_set(chip, GIO_OH, offset - 16, value);
203}
204
205static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
206 int value)
207{
208 /* write GPIO value to output before selecting output mode of pin */
209 em_gio_set(chip, offset, value);
210 em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
211 return 0;
212}
213
214static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
215{
Linus Walleij73855002012-10-16 20:15:02 +0200216 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
Magnus Damma07e1032012-05-17 15:22:23 +0900217}
218
219static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
220 irq_hw_number_t hw)
221{
222 struct em_gio_priv *p = h->host_data;
223
224 pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq);
225
226 irq_set_chip_data(virq, h->host_data);
227 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
228 set_irq_flags(virq, IRQF_VALID); /* kill me now */
229 return 0;
230}
231
232static struct irq_domain_ops em_gio_irq_domain_ops = {
233 .map = em_gio_irq_domain_map,
234};
235
Magnus Damma07e1032012-05-17 15:22:23 +0900236static int __devinit em_gio_probe(struct platform_device *pdev)
237{
238 struct gpio_em_config *pdata = pdev->dev.platform_data;
239 struct em_gio_priv *p;
240 struct resource *io[2], *irq[2];
241 struct gpio_chip *gpio_chip;
242 struct irq_chip *irq_chip;
243 const char *name = dev_name(&pdev->dev);
244 int ret;
245
246 p = kzalloc(sizeof(*p), GFP_KERNEL);
247 if (!p) {
248 dev_err(&pdev->dev, "failed to allocate driver data\n");
249 ret = -ENOMEM;
250 goto err0;
251 }
252
253 p->pdev = pdev;
254 platform_set_drvdata(pdev, p);
255 spin_lock_init(&p->sense_lock);
256
257 io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
258 io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
259 irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
260 irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
261
262 if (!io[0] || !io[1] || !irq[0] || !irq[1] || !pdata) {
263 dev_err(&pdev->dev, "missing IRQ, IOMEM or configuration\n");
264 ret = -EINVAL;
265 goto err1;
266 }
267
268 p->base0 = ioremap_nocache(io[0]->start, resource_size(io[0]));
269 if (!p->base0) {
270 dev_err(&pdev->dev, "failed to remap low I/O memory\n");
271 ret = -ENXIO;
272 goto err1;
273 }
274
275 p->base1 = ioremap_nocache(io[1]->start, resource_size(io[1]));
276 if (!p->base1) {
277 dev_err(&pdev->dev, "failed to remap high I/O memory\n");
278 ret = -ENXIO;
279 goto err2;
280 }
281
282 gpio_chip = &p->gpio_chip;
283 gpio_chip->direction_input = em_gio_direction_input;
284 gpio_chip->get = em_gio_get;
285 gpio_chip->direction_output = em_gio_direction_output;
286 gpio_chip->set = em_gio_set;
287 gpio_chip->to_irq = em_gio_to_irq;
288 gpio_chip->label = name;
289 gpio_chip->owner = THIS_MODULE;
290 gpio_chip->base = pdata->gpio_base;
291 gpio_chip->ngpio = pdata->number_of_pins;
292
293 irq_chip = &p->irq_chip;
294 irq_chip->name = name;
295 irq_chip->irq_mask = em_gio_irq_disable;
296 irq_chip->irq_unmask = em_gio_irq_enable;
297 irq_chip->irq_enable = em_gio_irq_enable;
298 irq_chip->irq_disable = em_gio_irq_disable;
299 irq_chip->irq_set_type = em_gio_irq_set_type;
300 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
301
Linus Walleij73855002012-10-16 20:15:02 +0200302 p->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
303 pdata->number_of_pins,
304 &em_gio_irq_domain_ops, p);
305 if (!p->irq_domain)
306 err = -ENXIO;
Magnus Damma07e1032012-05-17 15:22:23 +0900307 dev_err(&pdev->dev, "cannot initialize irq domain\n");
308 goto err3;
309 }
310
311 if (request_irq(irq[0]->start, em_gio_irq_handler, 0, name, p)) {
312 dev_err(&pdev->dev, "failed to request low IRQ\n");
313 ret = -ENOENT;
314 goto err4;
315 }
316
317 if (request_irq(irq[1]->start, em_gio_irq_handler, 0, name, p)) {
318 dev_err(&pdev->dev, "failed to request high IRQ\n");
319 ret = -ENOENT;
320 goto err5;
321 }
322
323 ret = gpiochip_add(gpio_chip);
324 if (ret) {
325 dev_err(&pdev->dev, "failed to add GPIO controller\n");
326 goto err6;
327 }
328 return 0;
329
330err6:
331 free_irq(irq[1]->start, pdev);
332err5:
333 free_irq(irq[0]->start, pdev);
334err4:
Linus Walleij73855002012-10-16 20:15:02 +0200335 irq_domain_remove(p->irq_domain);
Magnus Damma07e1032012-05-17 15:22:23 +0900336err3:
337 iounmap(p->base1);
338err2:
339 iounmap(p->base0);
340err1:
341 kfree(p);
342err0:
343 return ret;
344}
345
346static int __devexit em_gio_remove(struct platform_device *pdev)
347{
348 struct em_gio_priv *p = platform_get_drvdata(pdev);
349 struct resource *irq[2];
350 int ret;
351
352 ret = gpiochip_remove(&p->gpio_chip);
353 if (ret)
354 return ret;
355
356 irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
357 irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
358
359 free_irq(irq[1]->start, pdev);
360 free_irq(irq[0]->start, pdev);
361 em_gio_irq_domain_cleanup(p);
362 iounmap(p->base1);
363 iounmap(p->base0);
364 kfree(p);
365 return 0;
366}
367
368static struct platform_driver em_gio_device_driver = {
369 .probe = em_gio_probe,
370 .remove = __devexit_p(em_gio_remove),
371 .driver = {
372 .name = "em_gio",
373 }
374};
375
376module_platform_driver(em_gio_device_driver);
377
378MODULE_AUTHOR("Magnus Damm");
379MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
380MODULE_LICENSE("GPL v2");