blob: 66f66ee8ca637fc2c6a29b12123a0cb7329a68ca [file] [log] [blame]
David S. Millerecba38a2006-06-23 21:23:01 -07001/* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Once again I am out to prove that every ethernet
3 * controller out there can be most efficiently programmed
4 * if you make it look like a LANCE.
5 *
David S. Millerecba38a2006-06-23 21:23:01 -07006 * Copyright (C) 1996, 1999, 2003, 2006 David S. Miller (davem@davemloft.net)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 */
8
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/errno.h>
13#include <linux/fcntl.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/in.h>
17#include <linux/slab.h>
18#include <linux/string.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/crc32.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/ethtool.h>
26#include <linux/bitops.h>
David S. Miller738f2b72008-08-27 18:09:11 -070027#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
29#include <asm/system.h>
30#include <asm/io.h>
31#include <asm/dma.h>
32#include <asm/byteorder.h>
33#include <asm/idprom.h>
34#include <asm/sbus.h>
35#include <asm/openprom.h>
36#include <asm/oplib.h>
37#include <asm/auxio.h>
38#include <asm/pgtable.h>
39#include <asm/irq.h>
40
41#include "sunqe.h"
42
Tom 'spot' Callaway10158282005-04-24 20:35:20 -070043#define DRV_NAME "sunqe"
David S. Millerecba38a2006-06-23 21:23:01 -070044#define DRV_VERSION "4.0"
45#define DRV_RELDATE "June 23, 2006"
46#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
Tom 'spot' Callaway10158282005-04-24 20:35:20 -070047
48static char version[] =
49 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
50
51MODULE_VERSION(DRV_VERSION);
52MODULE_AUTHOR(DRV_AUTHOR);
53MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver");
54MODULE_LICENSE("GPL");
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056static struct sunqec *root_qec_dev;
57
58static void qe_set_multicast(struct net_device *dev);
59
60#define QEC_RESET_TRIES 200
61
62static inline int qec_global_reset(void __iomem *gregs)
63{
64 int tries = QEC_RESET_TRIES;
65
66 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
67 while (--tries) {
68 u32 tmp = sbus_readl(gregs + GLOB_CTRL);
69 if (tmp & GLOB_CTRL_RESET) {
70 udelay(20);
71 continue;
72 }
73 break;
74 }
75 if (tries)
76 return 0;
77 printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
78 return -1;
79}
80
81#define MACE_RESET_RETRIES 200
82#define QE_RESET_RETRIES 200
83
84static inline int qe_stop(struct sunqe *qep)
85{
86 void __iomem *cregs = qep->qcregs;
87 void __iomem *mregs = qep->mregs;
88 int tries;
89
90 /* Reset the MACE, then the QEC channel. */
91 sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
92 tries = MACE_RESET_RETRIES;
93 while (--tries) {
94 u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
95 if (tmp & MREGS_BCONFIG_RESET) {
96 udelay(20);
97 continue;
98 }
99 break;
100 }
101 if (!tries) {
102 printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
103 return -1;
104 }
105
106 sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
107 tries = QE_RESET_RETRIES;
108 while (--tries) {
109 u32 tmp = sbus_readl(cregs + CREG_CTRL);
110 if (tmp & CREG_CTRL_RESET) {
111 udelay(20);
112 continue;
113 }
114 break;
115 }
116 if (!tries) {
117 printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
118 return -1;
119 }
120 return 0;
121}
122
123static void qe_init_rings(struct sunqe *qep)
124{
125 struct qe_init_block *qb = qep->qe_block;
126 struct sunqe_buffers *qbufs = qep->buffers;
127 __u32 qbufs_dvma = qep->buffers_dvma;
128 int i;
129
130 qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
131 memset(qb, 0, sizeof(struct qe_init_block));
132 memset(qbufs, 0, sizeof(struct sunqe_buffers));
133 for (i = 0; i < RX_RING_SIZE; i++) {
134 qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
135 qb->qe_rxd[i].rx_flags =
136 (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
137 }
138}
139
140static int qe_init(struct sunqe *qep, int from_irq)
141{
142 struct sunqec *qecp = qep->parent;
143 void __iomem *cregs = qep->qcregs;
144 void __iomem *mregs = qep->mregs;
145 void __iomem *gregs = qecp->gregs;
146 unsigned char *e = &qep->dev->dev_addr[0];
147 u32 tmp;
148 int i;
149
150 /* Shut it up. */
151 if (qe_stop(qep))
152 return -EAGAIN;
153
154 /* Setup initial rx/tx init block pointers. */
155 sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
156 sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
157
158 /* Enable/mask the various irq's. */
159 sbus_writel(0, cregs + CREG_RIMASK);
160 sbus_writel(1, cregs + CREG_TIMASK);
161
162 sbus_writel(0, cregs + CREG_QMASK);
163 sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
164
165 /* Setup the FIFO pointers into QEC local memory. */
166 tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
167 sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
168 sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
169
170 tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
171 sbus_readl(gregs + GLOB_RSIZE);
172 sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
173 sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
174
175 /* Clear the channel collision counter. */
176 sbus_writel(0, cregs + CREG_CCNT);
177
178 /* For 10baseT, inter frame space nor throttle seems to be necessary. */
179 sbus_writel(0, cregs + CREG_PIPG);
180
181 /* Now dork with the AMD MACE. */
182 sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
183 sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
184 sbus_writeb(0, mregs + MREGS_RXFCNTL);
185
186 /* The QEC dma's the rx'd packets from local memory out to main memory,
187 * and therefore it interrupts when the packet reception is "complete".
188 * So don't listen for the MACE talking about it.
189 */
190 sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
191 sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
192 sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
193 MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
194 mregs + MREGS_FCONFIG);
195
196 /* Only usable interface on QuadEther is twisted pair. */
197 sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
198
199 /* Tell MACE we are changing the ether address. */
200 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
201 mregs + MREGS_IACONFIG);
202 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
203 barrier();
204 sbus_writeb(e[0], mregs + MREGS_ETHADDR);
205 sbus_writeb(e[1], mregs + MREGS_ETHADDR);
206 sbus_writeb(e[2], mregs + MREGS_ETHADDR);
207 sbus_writeb(e[3], mregs + MREGS_ETHADDR);
208 sbus_writeb(e[4], mregs + MREGS_ETHADDR);
209 sbus_writeb(e[5], mregs + MREGS_ETHADDR);
210
211 /* Clear out the address filter. */
212 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
213 mregs + MREGS_IACONFIG);
214 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
215 barrier();
216 for (i = 0; i < 8; i++)
217 sbus_writeb(0, mregs + MREGS_FILTER);
218
219 /* Address changes are now complete. */
220 sbus_writeb(0, mregs + MREGS_IACONFIG);
221
222 qe_init_rings(qep);
223
224 /* Wait a little bit for the link to come up... */
225 mdelay(5);
226 if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
227 int tries = 50;
228
229 while (tries--) {
230 u8 tmp;
231
232 mdelay(5);
233 barrier();
234 tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
235 if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
236 break;
237 }
238 if (tries == 0)
239 printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
240 }
241
242 /* Missed packet counter is cleared on a read. */
243 sbus_readb(mregs + MREGS_MPCNT);
244
245 /* Reload multicast information, this will enable the receiver
246 * and transmitter.
247 */
248 qe_set_multicast(qep->dev);
249
250 /* QEC should now start to show interrupts. */
251 return 0;
252}
253
254/* Grrr, certain error conditions completely lock up the AMD MACE,
255 * so when we get these we _must_ reset the chip.
256 */
257static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
258{
259 struct net_device *dev = qep->dev;
260 int mace_hwbug_workaround = 0;
261
262 if (qe_status & CREG_STAT_EDEFER) {
263 printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700264 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 }
266
267 if (qe_status & CREG_STAT_CLOSS) {
268 printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700269 dev->stats.tx_errors++;
270 dev->stats.tx_carrier_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 }
272
273 if (qe_status & CREG_STAT_ERETRIES) {
274 printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700275 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 mace_hwbug_workaround = 1;
277 }
278
279 if (qe_status & CREG_STAT_LCOLL) {
280 printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700281 dev->stats.tx_errors++;
282 dev->stats.collisions++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 mace_hwbug_workaround = 1;
284 }
285
286 if (qe_status & CREG_STAT_FUFLOW) {
287 printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700288 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 mace_hwbug_workaround = 1;
290 }
291
292 if (qe_status & CREG_STAT_JERROR) {
293 printk(KERN_ERR "%s: Jabber error.\n", dev->name);
294 }
295
296 if (qe_status & CREG_STAT_BERROR) {
297 printk(KERN_ERR "%s: Babble error.\n", dev->name);
298 }
299
300 if (qe_status & CREG_STAT_CCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700301 dev->stats.tx_errors += 256;
302 dev->stats.collisions += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 }
304
305 if (qe_status & CREG_STAT_TXDERROR) {
306 printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700307 dev->stats.tx_errors++;
308 dev->stats.tx_aborted_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309 mace_hwbug_workaround = 1;
310 }
311
312 if (qe_status & CREG_STAT_TXLERR) {
313 printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700314 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 mace_hwbug_workaround = 1;
316 }
317
318 if (qe_status & CREG_STAT_TXPERR) {
319 printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700320 dev->stats.tx_errors++;
321 dev->stats.tx_aborted_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 mace_hwbug_workaround = 1;
323 }
324
325 if (qe_status & CREG_STAT_TXSERR) {
326 printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700327 dev->stats.tx_errors++;
328 dev->stats.tx_aborted_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 mace_hwbug_workaround = 1;
330 }
331
332 if (qe_status & CREG_STAT_RCCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700333 dev->stats.rx_errors += 256;
334 dev->stats.collisions += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 }
336
337 if (qe_status & CREG_STAT_RUOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700338 dev->stats.rx_errors += 256;
339 dev->stats.rx_over_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 }
341
342 if (qe_status & CREG_STAT_MCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700343 dev->stats.rx_errors += 256;
344 dev->stats.rx_missed_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 }
346
347 if (qe_status & CREG_STAT_RXFOFLOW) {
348 printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700349 dev->stats.rx_errors++;
350 dev->stats.rx_over_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 }
352
353 if (qe_status & CREG_STAT_RLCOLL) {
354 printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700355 dev->stats.rx_errors++;
356 dev->stats.collisions++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 }
358
359 if (qe_status & CREG_STAT_FCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700360 dev->stats.rx_errors += 256;
361 dev->stats.rx_frame_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 }
363
364 if (qe_status & CREG_STAT_CECOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700365 dev->stats.rx_errors += 256;
366 dev->stats.rx_crc_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 }
368
369 if (qe_status & CREG_STAT_RXDROP) {
370 printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700371 dev->stats.rx_errors++;
372 dev->stats.rx_dropped++;
373 dev->stats.rx_missed_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 }
375
376 if (qe_status & CREG_STAT_RXSMALL) {
377 printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700378 dev->stats.rx_errors++;
379 dev->stats.rx_length_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 }
381
382 if (qe_status & CREG_STAT_RXLERR) {
383 printk(KERN_ERR "%s: Receive late error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700384 dev->stats.rx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 mace_hwbug_workaround = 1;
386 }
387
388 if (qe_status & CREG_STAT_RXPERR) {
389 printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700390 dev->stats.rx_errors++;
391 dev->stats.rx_missed_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 mace_hwbug_workaround = 1;
393 }
394
395 if (qe_status & CREG_STAT_RXSERR) {
396 printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700397 dev->stats.rx_errors++;
398 dev->stats.rx_missed_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 mace_hwbug_workaround = 1;
400 }
401
402 if (mace_hwbug_workaround)
403 qe_init(qep, 1);
404 return mace_hwbug_workaround;
405}
406
407/* Per-QE receive interrupt service routine. Just like on the happy meal
408 * we receive directly into skb's with a small packet copy water mark.
409 */
410static void qe_rx(struct sunqe *qep)
411{
412 struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700413 struct net_device *dev = qep->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414 struct qe_rxd *this;
415 struct sunqe_buffers *qbufs = qep->buffers;
416 __u32 qbufs_dvma = qep->buffers_dvma;
417 int elem = qep->rx_new, drops = 0;
418 u32 flags;
419
420 this = &rxbase[elem];
421 while (!((flags = this->rx_flags) & RXD_OWN)) {
422 struct sk_buff *skb;
423 unsigned char *this_qbuf =
424 &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
425 __u32 this_qbuf_dvma = qbufs_dvma +
426 qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
427 struct qe_rxd *end_rxd =
428 &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
429 int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
430
431 /* Check for errors. */
432 if (len < ETH_ZLEN) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700433 dev->stats.rx_errors++;
434 dev->stats.rx_length_errors++;
435 dev->stats.rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 } else {
437 skb = dev_alloc_skb(len + 2);
438 if (skb == NULL) {
439 drops++;
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700440 dev->stats.rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 skb_reserve(skb, 2);
443 skb_put(skb, len);
David S. Miller8c7b7fa2007-07-10 22:08:12 -0700444 skb_copy_to_linear_data(skb, (unsigned char *) this_qbuf,
445 len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 skb->protocol = eth_type_trans(skb, qep->dev);
447 netif_rx(skb);
448 qep->dev->last_rx = jiffies;
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700449 dev->stats.rx_packets++;
450 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451 }
452 }
453 end_rxd->rx_addr = this_qbuf_dvma;
454 end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400455
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 elem = NEXT_RX(elem);
457 this = &rxbase[elem];
458 }
459 qep->rx_new = elem;
460 if (drops)
461 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name);
462}
463
464static void qe_tx_reclaim(struct sunqe *qep);
465
466/* Interrupts for all QE's get filtered out via the QEC master controller,
467 * so we just run through each qe and check to see who is signaling
468 * and thus needs to be serviced.
469 */
David Howells7d12e782006-10-05 14:55:46 +0100470static irqreturn_t qec_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471{
Jeff Garzikc31f28e2006-10-06 14:56:04 -0400472 struct sunqec *qecp = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 u32 qec_status;
474 int channel = 0;
475
476 /* Latch the status now. */
477 qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
478 while (channel < 4) {
479 if (qec_status & 0xf) {
480 struct sunqe *qep = qecp->qes[channel];
481 u32 qe_status;
482
483 qe_status = sbus_readl(qep->qcregs + CREG_STAT);
484 if (qe_status & CREG_STAT_ERRORS) {
485 if (qe_is_bolixed(qep, qe_status))
486 goto next;
487 }
488 if (qe_status & CREG_STAT_RXIRQ)
489 qe_rx(qep);
490 if (netif_queue_stopped(qep->dev) &&
491 (qe_status & CREG_STAT_TXIRQ)) {
492 spin_lock(&qep->lock);
493 qe_tx_reclaim(qep);
494 if (TX_BUFFS_AVAIL(qep) > 0) {
495 /* Wake net queue and return to
496 * lazy tx reclaim.
497 */
498 netif_wake_queue(qep->dev);
499 sbus_writel(1, qep->qcregs + CREG_TIMASK);
500 }
501 spin_unlock(&qep->lock);
502 }
503 next:
504 ;
505 }
506 qec_status >>= 4;
507 channel++;
508 }
509
510 return IRQ_HANDLED;
511}
512
513static int qe_open(struct net_device *dev)
514{
515 struct sunqe *qep = (struct sunqe *) dev->priv;
516
517 qep->mconfig = (MREGS_MCONFIG_TXENAB |
518 MREGS_MCONFIG_RXENAB |
519 MREGS_MCONFIG_MBAENAB);
520 return qe_init(qep, 0);
521}
522
523static int qe_close(struct net_device *dev)
524{
525 struct sunqe *qep = (struct sunqe *) dev->priv;
526
527 qe_stop(qep);
528 return 0;
529}
530
531/* Reclaim TX'd frames from the ring. This must always run under
532 * the IRQ protected qep->lock.
533 */
534static void qe_tx_reclaim(struct sunqe *qep)
535{
536 struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
537 int elem = qep->tx_old;
538
539 while (elem != qep->tx_new) {
540 u32 flags = txbase[elem].tx_flags;
541
542 if (flags & TXD_OWN)
543 break;
544 elem = NEXT_TX(elem);
545 }
546 qep->tx_old = elem;
547}
548
549static void qe_tx_timeout(struct net_device *dev)
550{
551 struct sunqe *qep = (struct sunqe *) dev->priv;
552 int tx_full;
553
554 spin_lock_irq(&qep->lock);
555
556 /* Try to reclaim, if that frees up some tx
557 * entries, we're fine.
558 */
559 qe_tx_reclaim(qep);
560 tx_full = TX_BUFFS_AVAIL(qep) <= 0;
561
562 spin_unlock_irq(&qep->lock);
563
564 if (! tx_full)
565 goto out;
566
567 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
568 qe_init(qep, 1);
569
570out:
571 netif_wake_queue(dev);
572}
573
574/* Get a packet queued to go onto the wire. */
575static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
576{
577 struct sunqe *qep = (struct sunqe *) dev->priv;
578 struct sunqe_buffers *qbufs = qep->buffers;
579 __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
580 unsigned char *txbuf;
581 int len, entry;
582
583 spin_lock_irq(&qep->lock);
584
585 qe_tx_reclaim(qep);
586
587 len = skb->len;
588 entry = qep->tx_new;
589
590 txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
591 txbuf_dvma = qbufs_dvma +
592 qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
593
594 /* Avoid a race... */
595 qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
596
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -0300597 skb_copy_from_linear_data(skb, txbuf, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598
599 qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
600 qep->qe_block->qe_txd[entry].tx_flags =
601 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
602 qep->tx_new = NEXT_TX(entry);
603
604 /* Get it going. */
605 dev->trans_start = jiffies;
606 sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
607
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700608 dev->stats.tx_packets++;
609 dev->stats.tx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610
611 if (TX_BUFFS_AVAIL(qep) <= 0) {
612 /* Halt the net queue and enable tx interrupts.
613 * When the tx queue empties the tx irq handler
614 * will wake up the queue and return us back to
615 * the lazy tx reclaim scheme.
616 */
617 netif_stop_queue(dev);
618 sbus_writel(0, qep->qcregs + CREG_TIMASK);
619 }
620 spin_unlock_irq(&qep->lock);
621
622 dev_kfree_skb(skb);
623
624 return 0;
625}
626
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627static void qe_set_multicast(struct net_device *dev)
628{
629 struct sunqe *qep = (struct sunqe *) dev->priv;
630 struct dev_mc_list *dmi = dev->mc_list;
631 u8 new_mconfig = qep->mconfig;
632 char *addrs;
633 int i;
634 u32 crc;
635
636 /* Lock out others. */
637 netif_stop_queue(dev);
638
639 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
640 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
641 qep->mregs + MREGS_IACONFIG);
642 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
643 barrier();
644 for (i = 0; i < 8; i++)
645 sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
646 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
647 } else if (dev->flags & IFF_PROMISC) {
648 new_mconfig |= MREGS_MCONFIG_PROMISC;
649 } else {
650 u16 hash_table[4];
651 u8 *hbytes = (unsigned char *) &hash_table[0];
652
653 for (i = 0; i < 4; i++)
654 hash_table[i] = 0;
655
656 for (i = 0; i < dev->mc_count; i++) {
657 addrs = dmi->dmi_addr;
658 dmi = dmi->next;
659
660 if (!(*addrs & 1))
661 continue;
662 crc = ether_crc_le(6, addrs);
663 crc >>= 26;
664 hash_table[crc >> 4] |= 1 << (crc & 0xf);
665 }
666 /* Program the qe with the new filter value. */
667 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
668 qep->mregs + MREGS_IACONFIG);
669 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
670 barrier();
671 for (i = 0; i < 8; i++) {
672 u8 tmp = *hbytes++;
673 sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
674 }
675 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
676 }
677
678 /* Any change of the logical address filter, the physical address,
679 * or enabling/disabling promiscuous mode causes the MACE to disable
680 * the receiver. So we must re-enable them here or else the MACE
681 * refuses to listen to anything on the network. Sheesh, took
682 * me a day or two to find this bug.
683 */
684 qep->mconfig = new_mconfig;
685 sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
686
687 /* Let us get going again. */
688 netif_wake_queue(dev);
689}
690
691/* Ethtool support... */
692static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
693{
694 struct sunqe *qep = dev->priv;
695
696 strcpy(info->driver, "sunqe");
697 strcpy(info->version, "3.0");
698 sprintf(info->bus_info, "SBUS:%d",
699 qep->qe_sdev->slot);
700}
701
702static u32 qe_get_link(struct net_device *dev)
703{
704 struct sunqe *qep = dev->priv;
705 void __iomem *mregs = qep->mregs;
706 u8 phyconfig;
707
708 spin_lock_irq(&qep->lock);
709 phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
710 spin_unlock_irq(&qep->lock);
711
712 return (phyconfig & MREGS_PHYCONFIG_LSTAT);
713}
714
Jeff Garzik7282d492006-09-13 14:30:00 -0400715static const struct ethtool_ops qe_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 .get_drvinfo = qe_get_drvinfo,
717 .get_link = qe_get_link,
718};
719
720/* This is only called once at boot time for each card probed. */
721static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev)
722{
723 u8 bsizes = qecp->qec_bursts;
724
725 if (sbus_can_burst64(qsdev) && (bsizes & DMA_BURST64)) {
726 sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
727 } else if (bsizes & DMA_BURST32) {
728 sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
729 } else {
730 sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
731 }
732
733 /* Packetsize only used in 100baseT BigMAC configurations,
734 * set it to zero just to be on the safe side.
735 */
736 sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
737
738 /* Set the local memsize register, divided up to one piece per QE channel. */
739 sbus_writel((qsdev->reg_addrs[1].reg_size >> 2),
740 qecp->gregs + GLOB_MSIZE);
741
742 /* Divide up the local QEC memory amongst the 4 QE receiver and
743 * transmitter FIFOs. Basically it is (total / 2 / num_channels).
744 */
745 sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
746 qecp->gregs + GLOB_TSIZE);
747 sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
748 qecp->gregs + GLOB_RSIZE);
749}
750
Adrian Bunk3edd76c2008-01-30 22:03:39 +0200751static u8 __devinit qec_get_burst(struct device_node *dp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 u8 bsizes, bsizes_more;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754
David S. Millerecba38a2006-06-23 21:23:01 -0700755 /* Find and set the burst sizes for the QEC, since it
756 * does the actual dma for all 4 channels.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 */
David S. Millerecba38a2006-06-23 21:23:01 -0700758 bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759 bsizes &= 0xff;
David S. Millerecba38a2006-06-23 21:23:01 -0700760 bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761
762 if (bsizes_more != 0xff)
763 bsizes &= bsizes_more;
764 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
David S. Millerecba38a2006-06-23 21:23:01 -0700765 (bsizes & DMA_BURST32)==0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 bsizes = (DMA_BURST32 - 1);
767
David S. Millerecba38a2006-06-23 21:23:01 -0700768 return bsizes;
769}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770
Adrian Bunk3edd76c2008-01-30 22:03:39 +0200771static struct sunqec * __devinit get_qec(struct sbus_dev *child_sdev)
David S. Millerecba38a2006-06-23 21:23:01 -0700772{
773 struct sbus_dev *qec_sdev = child_sdev->parent;
774 struct sunqec *qecp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775
David S. Millerecba38a2006-06-23 21:23:01 -0700776 for (qecp = root_qec_dev; qecp; qecp = qecp->next_module) {
777 if (qecp->qec_sdev == qec_sdev)
778 break;
779 }
780 if (!qecp) {
781 qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
782 if (qecp) {
783 u32 ctrl;
784
785 qecp->qec_sdev = qec_sdev;
786 qecp->gregs = sbus_ioremap(&qec_sdev->resource[0], 0,
787 GLOB_REG_SIZE,
788 "QEC Global Registers");
789 if (!qecp->gregs)
790 goto fail;
791
792 /* Make sure the QEC is in MACE mode. */
793 ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
794 ctrl &= 0xf0000000;
795 if (ctrl != GLOB_CTRL_MMODE) {
796 printk(KERN_ERR "qec: Not in MACE mode!\n");
797 goto fail;
798 }
799
800 if (qec_global_reset(qecp->gregs))
801 goto fail;
802
803 qecp->qec_bursts = qec_get_burst(qec_sdev->ofdev.node);
804
805 qec_init_once(qecp, qec_sdev);
806
807 if (request_irq(qec_sdev->irqs[0], &qec_interrupt,
Thomas Gleixner1fb9df52006-07-01 19:29:39 -0700808 IRQF_SHARED, "qec", (void *) qecp)) {
David S. Millerecba38a2006-06-23 21:23:01 -0700809 printk(KERN_ERR "qec: Can't register irq.\n");
810 goto fail;
811 }
812
813 qecp->next_module = root_qec_dev;
814 root_qec_dev = qecp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 }
David S. Millerecba38a2006-06-23 21:23:01 -0700816 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817
David S. Millerecba38a2006-06-23 21:23:01 -0700818 return qecp;
819
820fail:
821 if (qecp->gregs)
822 sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
823 kfree(qecp);
824 return NULL;
825}
826
Adrian Bunk3edd76c2008-01-30 22:03:39 +0200827static int __devinit qec_ether_init(struct sbus_dev *sdev)
David S. Millerecba38a2006-06-23 21:23:01 -0700828{
829 static unsigned version_printed;
830 struct net_device *dev;
831 struct sunqe *qe;
832 struct sunqec *qecp;
833 int i, res;
834
835 if (version_printed++ == 0)
836 printk(KERN_INFO "%s", version);
837
838 dev = alloc_etherdev(sizeof(struct sunqe));
839 if (!dev)
840 return -ENOMEM;
841
Marcel van Niesd0dc1122007-04-21 15:31:58 -0700842 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
843
David S. Millerecba38a2006-06-23 21:23:01 -0700844 qe = netdev_priv(dev);
845
846 i = of_getintprop_default(sdev->ofdev.node, "channel#", -1);
847 if (i == -1) {
848 struct sbus_dev *td = sdev->parent->child;
849 i = 0;
850 while (td != sdev) {
851 td = td->next;
852 i++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 }
David S. Millerecba38a2006-06-23 21:23:01 -0700854 }
855 qe->channel = i;
856 spin_lock_init(&qe->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400857
David S. Millerecba38a2006-06-23 21:23:01 -0700858 res = -ENODEV;
859 qecp = get_qec(sdev);
860 if (!qecp)
861 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862
David S. Millerecba38a2006-06-23 21:23:01 -0700863 qecp->qes[qe->channel] = qe;
864 qe->dev = dev;
865 qe->parent = qecp;
866 qe->qe_sdev = sdev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867
David S. Millerecba38a2006-06-23 21:23:01 -0700868 res = -ENOMEM;
869 qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0,
870 CREG_REG_SIZE, "QEC Channel Registers");
871 if (!qe->qcregs) {
872 printk(KERN_ERR "qe: Cannot map channel registers.\n");
873 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 }
875
David S. Millerecba38a2006-06-23 21:23:01 -0700876 qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0,
877 MREGS_REG_SIZE, "QE MACE Registers");
878 if (!qe->mregs) {
879 printk(KERN_ERR "qe: Cannot map MACE registers.\n");
880 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 }
882
David S. Miller738f2b72008-08-27 18:09:11 -0700883 qe->qe_block = dma_alloc_coherent(&qe->qe_sdev->ofdev.dev,
884 PAGE_SIZE,
885 &qe->qblock_dvma, GFP_ATOMIC);
886 qe->buffers = dma_alloc_coherent(&qe->qe_sdev->ofdev.dev,
887 sizeof(struct sunqe_buffers),
888 &qe->buffers_dvma, GFP_ATOMIC);
David S. Millerecba38a2006-06-23 21:23:01 -0700889 if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
890 qe->buffers == NULL || qe->buffers_dvma == 0)
891 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892
David S. Millerecba38a2006-06-23 21:23:01 -0700893 /* Stop this QE. */
894 qe_stop(qe);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895
David S. Millerecba38a2006-06-23 21:23:01 -0700896 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897
David S. Millerecba38a2006-06-23 21:23:01 -0700898 dev->open = qe_open;
899 dev->stop = qe_close;
900 dev->hard_start_xmit = qe_start_xmit;
David S. Millerecba38a2006-06-23 21:23:01 -0700901 dev->set_multicast_list = qe_set_multicast;
902 dev->tx_timeout = qe_tx_timeout;
903 dev->watchdog_timeo = 5*HZ;
904 dev->irq = sdev->irqs[0];
905 dev->dma = 0;
906 dev->ethtool_ops = &qe_ethtool_ops;
907
908 res = register_netdev(dev);
909 if (res)
910 goto fail;
911
912 dev_set_drvdata(&sdev->ofdev.dev, qe);
913
914 printk(KERN_INFO "%s: qe channel[%d] ", dev->name, qe->channel);
915 for (i = 0; i < 6; i++)
916 printk ("%2.2x%c",
917 dev->dev_addr[i],
918 i == 5 ? ' ': ':');
919 printk("\n");
920
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921
922 return 0;
923
David S. Millerecba38a2006-06-23 21:23:01 -0700924fail:
925 if (qe->qcregs)
926 sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
927 if (qe->mregs)
928 sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
929 if (qe->qe_block)
David S. Miller738f2b72008-08-27 18:09:11 -0700930 dma_free_coherent(&qe->qe_sdev->ofdev.dev,
931 PAGE_SIZE,
932 qe->qe_block,
933 qe->qblock_dvma);
David S. Millerecba38a2006-06-23 21:23:01 -0700934 if (qe->buffers)
David S. Miller738f2b72008-08-27 18:09:11 -0700935 dma_free_coherent(&qe->qe_sdev->ofdev.dev,
936 sizeof(struct sunqe_buffers),
937 qe->buffers,
938 qe->buffers_dvma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939
David S. Millerecba38a2006-06-23 21:23:01 -0700940 free_netdev(dev);
941
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 return res;
943}
944
David S. Millerecba38a2006-06-23 21:23:01 -0700945static int __devinit qec_sbus_probe(struct of_device *dev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946{
David S. Millerecba38a2006-06-23 21:23:01 -0700947 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948
David S. Millerecba38a2006-06-23 21:23:01 -0700949 return qec_ether_init(sdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950}
951
David S. Millerecba38a2006-06-23 21:23:01 -0700952static int __devexit qec_sbus_remove(struct of_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700953{
David S. Millerecba38a2006-06-23 21:23:01 -0700954 struct sunqe *qp = dev_get_drvdata(&dev->dev);
955 struct net_device *net_dev = qp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956
Marcel van Niesd0dc1122007-04-21 15:31:58 -0700957 unregister_netdev(net_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958
David S. Millerecba38a2006-06-23 21:23:01 -0700959 sbus_iounmap(qp->qcregs, CREG_REG_SIZE);
960 sbus_iounmap(qp->mregs, MREGS_REG_SIZE);
David S. Miller738f2b72008-08-27 18:09:11 -0700961 dma_free_coherent(&qp->qe_sdev->ofdev.dev,
962 PAGE_SIZE,
963 qp->qe_block,
964 qp->qblock_dvma);
965 dma_free_coherent(&qp->qe_sdev->ofdev.dev,
966 sizeof(struct sunqe_buffers),
967 qp->buffers,
968 qp->buffers_dvma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969
David S. Millerecba38a2006-06-23 21:23:01 -0700970 free_netdev(net_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971
David S. Millerecba38a2006-06-23 21:23:01 -0700972 dev_set_drvdata(&dev->dev, NULL);
973
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 return 0;
975}
976
David S. Millerecba38a2006-06-23 21:23:01 -0700977static struct of_device_id qec_sbus_match[] = {
978 {
979 .name = "qe",
980 },
981 {},
982};
983
984MODULE_DEVICE_TABLE(of, qec_sbus_match);
985
986static struct of_platform_driver qec_sbus_driver = {
987 .name = "qec",
988 .match_table = qec_sbus_match,
989 .probe = qec_sbus_probe,
990 .remove = __devexit_p(qec_sbus_remove),
991};
992
993static int __init qec_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994{
David S. Millerecba38a2006-06-23 21:23:01 -0700995 return of_register_driver(&qec_sbus_driver, &sbus_bus_type);
996}
997
998static void __exit qec_exit(void)
999{
1000 of_unregister_driver(&qec_sbus_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001
1002 while (root_qec_dev) {
David S. Millerecba38a2006-06-23 21:23:01 -07001003 struct sunqec *next = root_qec_dev->next_module;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004
David S. Millerecba38a2006-06-23 21:23:01 -07001005 free_irq(root_qec_dev->qec_sdev->irqs[0],
1006 (void *) root_qec_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007 sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE);
David S. Millerecba38a2006-06-23 21:23:01 -07001008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 kfree(root_qec_dev);
David S. Millerecba38a2006-06-23 21:23:01 -07001010
1011 root_qec_dev = next;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 }
1013}
1014
David S. Millerecba38a2006-06-23 21:23:01 -07001015module_init(qec_init);
1016module_exit(qec_exit);