blob: a65b75161aa49d16749258407db18c7cfc30f79f [file] [log] [blame]
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02001/*
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +02002 * GPIOs on MPC512x/8349/8572/8610 and compatible
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02003 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
Rob Herring5af50732013-09-17 14:28:33 -050017#include <linux/of_irq.h>
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +010018#include <linux/of_platform.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020019#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090020#include <linux/slab.h>
Peter Korsgaard345e5c82010-01-07 17:57:46 +010021#include <linux/irq.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020022
23#define MPC8XXX_GPIO_PINS 32
24
25#define GPIO_DIR 0x00
26#define GPIO_ODR 0x04
27#define GPIO_DAT 0x08
28#define GPIO_IER 0x0c
29#define GPIO_IMR 0x10
30#define GPIO_ICR 0x14
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +020031#define GPIO_ICR2 0x18
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020032
33struct mpc8xxx_gpio_chip {
34 struct of_mm_gpio_chip mm_gc;
35 spinlock_t lock;
36
37 /*
38 * shadowed data register to be able to clear/set output pins in
39 * open drain mode safely
40 */
41 u32 data;
Grant Likelybae1d8f2012-02-14 14:06:50 -070042 struct irq_domain *irq;
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +010043 unsigned int irqn;
Uwe Kleine-König01a04dd2012-05-21 21:57:39 +020044 const void *of_dev_id_data;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020045};
46
47static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
48{
49 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
50}
51
52static inline struct mpc8xxx_gpio_chip *
53to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
54{
55 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
56}
57
58static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
59{
60 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
61
62 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
63}
64
Felix Radenskyc1a676d2009-08-12 08:57:39 +030065/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
66 * defined as output cannot be determined by reading GPDAT register,
67 * so we use shadow data register instead. The status of input pins
68 * is determined by reading GPDAT register.
69 */
70static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
71{
72 u32 val;
73 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
74 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
Liu Gang1aeef302013-11-22 16:12:40 +080075 u32 out_mask, out_shadow;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030076
Liu Gang1aeef302013-11-22 16:12:40 +080077 out_mask = in_be32(mm->regs + GPIO_DIR);
Felix Radenskyc1a676d2009-08-12 08:57:39 +030078
Liu Gang1aeef302013-11-22 16:12:40 +080079 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
80 out_shadow = mpc8xxx_gc->data & out_mask;
81
82 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
Felix Radenskyc1a676d2009-08-12 08:57:39 +030083}
84
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020085static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88
89 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
90}
91
92static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
93{
94 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
95 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
96 unsigned long flags;
97
98 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
99
100 if (val)
101 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
102 else
103 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
104
105 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
106
107 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
108}
109
Rojhalat Ibrahime5db3b32014-11-04 17:12:09 +0100110static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
111 unsigned long *mask, unsigned long *bits)
112{
113 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
114 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
115 unsigned long flags;
116 int i;
117
118 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
119
120 for (i = 0; i < gc->ngpio; i++) {
121 if (*mask == 0)
122 break;
123 if (__test_and_clear_bit(i, mask)) {
124 if (test_bit(i, bits))
125 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
126 else
127 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
128 }
129 }
130
131 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
132
133 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
134}
135
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200136static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
137{
138 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
139 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
140 unsigned long flags;
141
142 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
143
144 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
145
146 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
147
148 return 0;
149}
150
151static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
152{
153 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
155 unsigned long flags;
156
157 mpc8xxx_gpio_set(gc, gpio, val);
158
159 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
160
161 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
162
163 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
164
165 return 0;
166}
167
Wolfram Sang28538df2011-12-13 10:12:48 +0100168static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
169{
170 /* GPIO 28..31 are input only on MPC5121 */
171 if (gpio >= 28)
172 return -EINVAL;
173
174 return mpc8xxx_gpio_dir_out(gc, gpio, val);
175}
176
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100177static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
178{
179 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
180 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
181
182 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
183 return irq_create_mapping(mpc8xxx_gc->irq, offset);
184 else
185 return -ENXIO;
186}
187
188static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
189{
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100190 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
Felix Radenskycfadd832011-10-11 10:24:21 +0200191 struct irq_chip *chip = irq_desc_get_chip(desc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100192 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
193 unsigned int mask;
194
195 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
196 if (mask)
197 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
198 32 - ffs(mask)));
Thomas Gleixnerd6de85e2012-05-03 12:22:06 +0200199 if (chip->irq_eoi)
200 chip->irq_eoi(&desc->irq_data);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100201}
202
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000203static void mpc8xxx_irq_unmask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100204{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000205 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100206 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
207 unsigned long flags;
208
209 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
210
Grant Likely476eb492011-05-04 15:02:15 +1000211 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100212
213 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
214}
215
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000216static void mpc8xxx_irq_mask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100217{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000218 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100219 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
220 unsigned long flags;
221
222 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223
Grant Likely476eb492011-05-04 15:02:15 +1000224 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100225
226 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
227}
228
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000229static void mpc8xxx_irq_ack(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100230{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000231 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100232 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
233
Grant Likely476eb492011-05-04 15:02:15 +1000234 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100235}
236
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000237static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100238{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000239 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100240 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
241 unsigned long flags;
242
243 switch (flow_type) {
244 case IRQ_TYPE_EDGE_FALLING:
245 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
246 setbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000247 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100248 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
249 break;
250
251 case IRQ_TYPE_EDGE_BOTH:
252 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
253 clrbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000254 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100255 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
256 break;
257
258 default:
259 return -EINVAL;
260 }
261
262 return 0;
263}
264
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000265static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200266{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000267 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200268 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
Grant Likely476eb492011-05-04 15:02:15 +1000269 unsigned long gpio = irqd_to_hwirq(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200270 void __iomem *reg;
271 unsigned int shift;
272 unsigned long flags;
273
274 if (gpio < 16) {
275 reg = mm->regs + GPIO_ICR;
276 shift = (15 - gpio) * 2;
277 } else {
278 reg = mm->regs + GPIO_ICR2;
279 shift = (15 - (gpio % 16)) * 2;
280 }
281
282 switch (flow_type) {
283 case IRQ_TYPE_EDGE_FALLING:
284 case IRQ_TYPE_LEVEL_LOW:
285 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
286 clrsetbits_be32(reg, 3 << shift, 2 << shift);
287 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
288 break;
289
290 case IRQ_TYPE_EDGE_RISING:
291 case IRQ_TYPE_LEVEL_HIGH:
292 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
293 clrsetbits_be32(reg, 3 << shift, 1 << shift);
294 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
295 break;
296
297 case IRQ_TYPE_EDGE_BOTH:
298 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
299 clrbits32(reg, 3 << shift);
300 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
301 break;
302
303 default:
304 return -EINVAL;
305 }
306
307 return 0;
308}
309
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100310static struct irq_chip mpc8xxx_irq_chip = {
311 .name = "mpc8xxx-gpio",
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000312 .irq_unmask = mpc8xxx_irq_unmask,
313 .irq_mask = mpc8xxx_irq_mask,
314 .irq_ack = mpc8xxx_irq_ack,
315 .irq_set_type = mpc8xxx_irq_set_type,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100316};
317
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200318static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
319 irq_hw_number_t hwirq)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100320{
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200321 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
322
323 if (mpc8xxx_gc->of_dev_id_data)
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000324 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200325
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200326 irq_set_chip_data(irq, h->host_data);
327 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100328
329 return 0;
330}
331
Grant Likelybae1d8f2012-02-14 14:06:50 -0700332static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100333 .map = mpc8xxx_gpio_irq_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700334 .xlate = irq_domain_xlate_twocell,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100335};
336
Kevin Hao32c006a2015-02-12 14:52:49 +0800337static struct of_device_id mpc8xxx_gpio_ids[] = {
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200338 { .compatible = "fsl,mpc8349-gpio", },
339 { .compatible = "fsl,mpc8572-gpio", },
340 { .compatible = "fsl,mpc8610-gpio", },
341 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
Kumar Gala15a51482011-10-22 16:20:42 -0500342 { .compatible = "fsl,pq3-gpio", },
Anatolij Gustschind1dcfbb2011-01-08 16:51:16 +0100343 { .compatible = "fsl,qoriq-gpio", },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200344 {}
345};
346
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100347static int mpc8xxx_probe(struct platform_device *pdev)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200348{
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100349 struct device_node *np = pdev->dev.of_node;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200350 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
351 struct of_mm_gpio_chip *mm_gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200352 struct gpio_chip *gc;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200353 const struct of_device_id *id;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200354 int ret;
355
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100356 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
357 if (!mpc8xxx_gc)
358 return -ENOMEM;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200359
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100360 platform_set_drvdata(pdev, mpc8xxx_gc);
361
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200362 spin_lock_init(&mpc8xxx_gc->lock);
363
364 mm_gc = &mpc8xxx_gc->mm_gc;
Anton Vorontsova19e3da2010-06-08 07:48:16 -0600365 gc = &mm_gc->gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200366
367 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200368 gc->ngpio = MPC8XXX_GPIO_PINS;
369 gc->direction_input = mpc8xxx_gpio_dir_in;
Wolfram Sang28538df2011-12-13 10:12:48 +0100370 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
371 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
372 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
373 mpc8572_gpio_get : mpc8xxx_gpio_get;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200374 gc->set = mpc8xxx_gpio_set;
Rojhalat Ibrahime5db3b32014-11-04 17:12:09 +0100375 gc->set_multiple = mpc8xxx_gpio_set_multiple;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100376 gc->to_irq = mpc8xxx_gpio_to_irq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200377
378 ret = of_mm_gpiochip_add(np, mm_gc);
379 if (ret)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100380 return ret;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200381
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100382 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
383 if (mpc8xxx_gc->irqn == NO_IRQ)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100384 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100385
Grant Likelya8db8cf2012-02-14 14:06:54 -0700386 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
387 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100388 if (!mpc8xxx_gc->irq)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100389 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100390
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200391 id = of_match_node(mpc8xxx_gpio_ids, np);
392 if (id)
393 mpc8xxx_gc->of_dev_id_data = id->data;
394
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100395 /* ack and mask all irqs */
396 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
397 out_be32(mm_gc->regs + GPIO_IMR, 0);
398
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100399 irq_set_handler_data(mpc8xxx_gc->irqn, mpc8xxx_gc);
400 irq_set_chained_handler(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade);
401
402 return 0;
403}
404
405static int mpc8xxx_remove(struct platform_device *pdev)
406{
407 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
408
409 if (mpc8xxx_gc->irq) {
410 irq_set_handler_data(mpc8xxx_gc->irqn, NULL);
411 irq_set_chained_handler(mpc8xxx_gc->irqn, NULL);
412 irq_domain_remove(mpc8xxx_gc->irq);
413 }
414
415 of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100416
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200417 return 0;
418}
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100419
420static struct platform_driver mpc8xxx_plat_driver = {
421 .probe = mpc8xxx_probe,
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100422 .remove = mpc8xxx_remove,
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100423 .driver = {
424 .name = "gpio-mpc8xxx",
425 .of_match_table = mpc8xxx_gpio_ids,
426 },
427};
428
429static int __init mpc8xxx_init(void)
430{
431 return platform_driver_register(&mpc8xxx_plat_driver);
432}
433
434arch_initcall(mpc8xxx_init);