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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * dib3000mb_priv.h
3 *
4 * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
9 *
10 * for more information see dib3000mb.c .
11 */
12
13#ifndef __DIB3000MB_PRIV_H_INCLUDED__
14#define __DIB3000MB_PRIV_H_INCLUDED__
15
Patrick Boettcher74340b02006-07-04 13:47:16 -030016/* info and err, taken from usb.h, if there is anything available like by default. */
17#define err(format, arg...) printk(KERN_ERR "dib3000: " format "\n" , ## arg)
18#define info(format, arg...) printk(KERN_INFO "dib3000: " format "\n" , ## arg)
19#define warn(format, arg...) printk(KERN_WARNING "dib3000: " format "\n" , ## arg)
20
21/* handy shortcuts */
22#define rd(reg) dib3000_read_reg(state,reg)
23
24#define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
25 { err("while sending 0x%04x to 0x%04x.",val,reg); return -EREMOTEIO; }
26
27#define wr_foreach(a,v) { int i; \
28 if (sizeof(a) != sizeof(v)) \
29 err("sizeof: %zu %zu is different",sizeof(a),sizeof(v));\
30 for (i=0; i < sizeof(a)/sizeof(u16); i++) \
31 wr(a[i],v[i]); \
32 }
33
34#define set_or(reg,val) wr(reg,rd(reg) | val)
35
36#define set_and(reg,val) wr(reg,rd(reg) & val)
37
38/* debug */
39
40#ifdef CONFIG_DVB_DIBCOM_DEBUG
41#define dprintk(level,args...) \
42 do { if ((debug & level)) { printk(args); } } while (0)
43#else
44#define dprintk(args...) do { } while (0)
45#endif
46
47/* mask for enabling a specific pid for the pid_filter */
48#define DIB3000_ACTIVATE_PID_FILTERING (0x2000)
49
50/* common values for tuning */
51#define DIB3000_ALPHA_0 ( 0)
52#define DIB3000_ALPHA_1 ( 1)
53#define DIB3000_ALPHA_2 ( 2)
54#define DIB3000_ALPHA_4 ( 4)
55
56#define DIB3000_CONSTELLATION_QPSK ( 0)
57#define DIB3000_CONSTELLATION_16QAM ( 1)
58#define DIB3000_CONSTELLATION_64QAM ( 2)
59
60#define DIB3000_GUARD_TIME_1_32 ( 0)
61#define DIB3000_GUARD_TIME_1_16 ( 1)
62#define DIB3000_GUARD_TIME_1_8 ( 2)
63#define DIB3000_GUARD_TIME_1_4 ( 3)
64
65#define DIB3000_TRANSMISSION_MODE_2K ( 0)
66#define DIB3000_TRANSMISSION_MODE_8K ( 1)
67
68#define DIB3000_SELECT_LP ( 0)
69#define DIB3000_SELECT_HP ( 1)
70
71#define DIB3000_FEC_1_2 ( 1)
72#define DIB3000_FEC_2_3 ( 2)
73#define DIB3000_FEC_3_4 ( 3)
74#define DIB3000_FEC_5_6 ( 5)
75#define DIB3000_FEC_7_8 ( 7)
76
77#define DIB3000_HRCH_OFF ( 0)
78#define DIB3000_HRCH_ON ( 1)
79
80#define DIB3000_DDS_INVERSION_OFF ( 0)
81#define DIB3000_DDS_INVERSION_ON ( 1)
82
83#define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
84#define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
85
86/* for auto search */
87extern u16 dib3000_seq[2][2][2];
88
89#define DIB3000_REG_MANUFACTOR_ID ( 1025)
90#define DIB3000_I2C_ID_DIBCOM (0x01b3)
91
92#define DIB3000_REG_DEVICE_ID ( 1026)
93#define DIB3000MB_DEVICE_ID (0x3000)
94#define DIB3000MC_DEVICE_ID (0x3001)
95#define DIB3000P_DEVICE_ID (0x3002)
96
97/* frontend state */
98struct dib3000_state {
99 struct i2c_adapter* i2c;
100
101/* configuration settings */
102 struct dib3000_config config;
103
104 struct dvb_frontend frontend;
105 int timing_offset;
106 int timing_offset_comp_done;
107
108 fe_bandwidth_t last_tuned_bw;
109 u32 last_tuned_freq;
110};
111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112/* register addresses and some of their default values */
113
114/* restart subsystems */
115#define DIB3000MB_REG_RESTART ( 0)
116
117#define DIB3000MB_RESTART_OFF ( 0)
118#define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1)
119#define DIB3000MB_RESTART_CTRL (1 << 2)
120#define DIB3000MB_RESTART_AGC (1 << 3)
121
122/* FFT size */
123#define DIB3000MB_REG_FFT ( 1)
124
125/* Guard time */
126#define DIB3000MB_REG_GUARD_TIME ( 2)
127
128/* QAM */
129#define DIB3000MB_REG_QAM ( 3)
130
131/* Alpha coefficient high priority Viterbi algorithm */
132#define DIB3000MB_REG_VIT_ALPHA ( 4)
133
134/* spectrum inversion */
135#define DIB3000MB_REG_DDS_INV ( 5)
136
137/* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
138#define DIB3000MB_REG_DDS_FREQ_MSB ( 6)
139#define DIB3000MB_REG_DDS_FREQ_LSB ( 7)
140#define DIB3000MB_DDS_FREQ_MSB ( 178)
141#define DIB3000MB_DDS_FREQ_LSB ( 8990)
142
143/* timing frequency (carrier spacing) */
144static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
145static u16 dib3000mb_timing_freq[][2] = {
146 { 126 , 48873 }, /* 6 MHz */
147 { 147 , 57019 }, /* 7 MHz */
148 { 168 , 65164 }, /* 8 MHz */
149};
150
151/* impulse noise parameter */
152/* 36 ??? */
153
154static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
155
156enum dib3000mb_impulse_noise_type {
157 DIB3000MB_IMPNOISE_OFF,
158 DIB3000MB_IMPNOISE_MOBILE,
159 DIB3000MB_IMPNOISE_FIXED,
160 DIB3000MB_IMPNOISE_DEFAULT
161};
162
163static u16 dib3000mb_impulse_noise_values[][5] = {
164 { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
165 { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
166 { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
167 { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
168};
169
170/*
171 * Dual Automatic-Gain-Control
172 * - gains RF in tuner (AGC1)
173 * - gains IF after filtering (AGC2)
174 */
175
176/* also from 16 to 18 */
177static u16 dib3000mb_reg_agc_gain[] = {
178 19,20,21,22,23,24,25,26,27,28,29,30,31,32
179};
180
181static u16 dib3000mb_default_agc_gain[] =
182 { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */
183 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */
184
185/* phase noise */
186/* 36 is set when setting the impulse noise */
187static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
188
189static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
190
191/* lock duration */
192static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
193static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
194
195/* AGC loop bandwidth */
196static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
197
198static u16 dib3000mb_agc_bandwidth_low[] =
199 { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
200static u16 dib3000mb_agc_bandwidth_high[] =
201 { 2349, 5, 2349, 5, 2586, 2, 2586, 2 };
202
203/*
204 * lock0 definition (coff_lock)
205 */
206#define DIB3000MB_REG_LOCK0_MASK ( 51)
207#define DIB3000MB_LOCK0_DEFAULT ( 4)
208
209/*
210 * lock1 definition (cpil_lock)
211 * for auto search
212 * which values hide behind the lock masks
213 */
214#define DIB3000MB_REG_LOCK1_MASK ( 52)
215#define DIB3000MB_LOCK1_SEARCH_4 (0x0004)
216#define DIB3000MB_LOCK1_SEARCH_2048 (0x0800)
217#define DIB3000MB_LOCK1_DEFAULT (0x0001)
218
219/*
220 * lock2 definition (fec_lock) */
221#define DIB3000MB_REG_LOCK2_MASK ( 53)
222#define DIB3000MB_LOCK2_DEFAULT (0x0080)
223
224/*
225 * SEQ ? what was that again ... :)
226 * changes when, inversion, guard time and fft is
227 * either automatically detected or not
228 */
229#define DIB3000MB_REG_SEQ ( 54)
230
231/* bandwidth */
232static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
233static u16 dib3000mb_bandwidth_6mhz[] =
234 { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
235
236static u16 dib3000mb_bandwidth_7mhz[] =
237 { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 };
238
239static u16 dib3000mb_bandwidth_8mhz[] =
240 { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
241
242#define DIB3000MB_REG_UNK_68 ( 68)
243#define DIB3000MB_UNK_68 ( 0)
244
245#define DIB3000MB_REG_UNK_69 ( 69)
246#define DIB3000MB_UNK_69 ( 0)
247
248#define DIB3000MB_REG_UNK_71 ( 71)
249#define DIB3000MB_UNK_71 ( 0)
250
251#define DIB3000MB_REG_UNK_77 ( 77)
252#define DIB3000MB_UNK_77 ( 6)
253
254#define DIB3000MB_REG_UNK_78 ( 78)
255#define DIB3000MB_UNK_78 (0x0080)
256
257/* isi */
258#define DIB3000MB_REG_ISI ( 79)
259#define DIB3000MB_ISI_ACTIVATE ( 0)
260#define DIB3000MB_ISI_INHIBIT ( 1)
261
262/* sync impovement */
263#define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84)
264#define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3)
265#define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0)
266
267/* phase noise compensation inhibition */
268#define DIB3000MB_REG_PHASE_NOISE ( 87)
269#define DIB3000MB_PHASE_NOISE_DEFAULT ( 0)
270
271#define DIB3000MB_REG_UNK_92 ( 92)
272#define DIB3000MB_UNK_92 (0x0080)
273
274#define DIB3000MB_REG_UNK_96 ( 96)
275#define DIB3000MB_UNK_96 (0x0010)
276
277#define DIB3000MB_REG_UNK_97 ( 97)
278#define DIB3000MB_UNK_97 (0x0009)
279
280/* mobile mode ??? */
281#define DIB3000MB_REG_MOBILE_MODE ( 101)
282#define DIB3000MB_MOBILE_MODE_ON ( 1)
283#define DIB3000MB_MOBILE_MODE_OFF ( 0)
284
285#define DIB3000MB_REG_UNK_106 ( 106)
286#define DIB3000MB_UNK_106 (0x0080)
287
288#define DIB3000MB_REG_UNK_107 ( 107)
289#define DIB3000MB_UNK_107 (0x0080)
290
291#define DIB3000MB_REG_UNK_108 ( 108)
292#define DIB3000MB_UNK_108 (0x0080)
293
294/* fft */
295#define DIB3000MB_REG_UNK_121 ( 121)
296#define DIB3000MB_UNK_121_2K ( 7)
297#define DIB3000MB_UNK_121_DEFAULT ( 5)
298
299#define DIB3000MB_REG_UNK_122 ( 122)
300#define DIB3000MB_UNK_122 ( 2867)
301
302/* QAM for mobile mode */
303#define DIB3000MB_REG_MOBILE_MODE_QAM ( 126)
304#define DIB3000MB_MOBILE_MODE_QAM_64 ( 3)
305#define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1)
306#define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0)
307
308/*
309 * data diversity when having more than one chip on-board
310 * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
311 */
312#define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127)
313#define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0)
314#define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2)
315
316/* vit hrch */
317#define DIB3000MB_REG_VIT_HRCH ( 128)
318
319/* vit code rate */
320#define DIB3000MB_REG_VIT_CODE_RATE ( 129)
321
322/* vit select hp */
323#define DIB3000MB_REG_VIT_HP ( 130)
324
325/* time frame for Bit-Error-Rate calculation */
326#define DIB3000MB_REG_BERLEN ( 135)
327#define DIB3000MB_BERLEN_LONG ( 0)
328#define DIB3000MB_BERLEN_DEFAULT ( 1)
329#define DIB3000MB_BERLEN_MEDIUM ( 2)
330#define DIB3000MB_BERLEN_SHORT ( 3)
331
332/* 142 - 152 FIFO parameters
333 * which is what ?
334 */
335
336#define DIB3000MB_REG_FIFO_142 ( 142)
337#define DIB3000MB_FIFO_142 ( 0)
338
339/* MPEG2 TS output mode */
340#define DIB3000MB_REG_MPEG2_OUT_MODE ( 143)
341#define DIB3000MB_MPEG2_OUT_MODE_204 ( 0)
342#define DIB3000MB_MPEG2_OUT_MODE_188 ( 1)
343
344#define DIB3000MB_REG_PID_PARSE ( 144)
345#define DIB3000MB_PID_PARSE_INHIBIT ( 0)
346#define DIB3000MB_PID_PARSE_ACTIVATE ( 1)
347
348#define DIB3000MB_REG_FIFO ( 145)
349#define DIB3000MB_FIFO_INHIBIT ( 1)
350#define DIB3000MB_FIFO_ACTIVATE ( 0)
351
352#define DIB3000MB_REG_FIFO_146 ( 146)
353#define DIB3000MB_FIFO_146 ( 3)
354
355#define DIB3000MB_REG_FIFO_147 ( 147)
356#define DIB3000MB_FIFO_147 (0x0100)
357
358/*
359 * pidfilter
360 * it is not a hardware pidfilter but a filter which drops all pids
361 * except the ones set. Necessary because of the limited USB1.1 bandwidth.
362 * regs 153-168
363 */
364
365#define DIB3000MB_REG_FIRST_PID ( 153)
366#define DIB3000MB_NUM_PIDS ( 16)
367
368/*
369 * output mode
370 * USB devices have to use 'slave'-mode
371 * see also DIB3000MB_REG_ELECT_OUT_MODE
372 */
373#define DIB3000MB_REG_OUTPUT_MODE ( 169)
374#define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0)
375#define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1)
376#define DIB3000MB_OUTPUT_MODE_SERIAL ( 2)
377#define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5)
378#define DIB3000MB_OUTPUT_MODE_SLAVE ( 6)
379
380/* irq event mask */
381#define DIB3000MB_REG_IRQ_EVENT_MASK ( 170)
382#define DIB3000MB_IRQ_EVENT_MASK ( 0)
383
384/* filter coefficients */
385static u16 dib3000mb_reg_filter_coeffs[] = {
386 171, 172, 173, 174, 175, 176, 177, 178,
387 179, 180, 181, 182, 183, 184, 185, 186,
388 188, 189, 190, 191, 192, 194
389};
390
391static u16 dib3000mb_filter_coeffs[] = {
392 226, 160, 29,
Johannes Stezenbach776338e2005-06-23 22:02:35 -0700393 979, 998, 19,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 22, 1019, 1006,
395 1022, 12, 6,
396 1017, 1017, 3,
397 6, 1019,
398 1021, 2, 3,
399 1, 0,
400};
401
402/*
403 * mobile algorithm (when you are moving with your device)
404 * but not faster than 90 km/h
405 */
406#define DIB3000MB_REG_MOBILE_ALGO ( 195)
407#define DIB3000MB_MOBILE_ALGO_ON ( 0)
408#define DIB3000MB_MOBILE_ALGO_OFF ( 1)
409
410/* multiple demodulators algorithm */
411#define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206)
412#define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207)
413
414/* terminator, no more demods */
415#define DIB3000MB_MULTI_DEMOD_MSB ( 32767)
416#define DIB3000MB_MULTI_DEMOD_LSB ( 4095)
417
418/* bring the device into a known */
419#define DIB3000MB_REG_RESET_DEVICE ( 1024)
420#define DIB3000MB_RESET_DEVICE (0x812c)
421#define DIB3000MB_RESET_DEVICE_RST ( 0)
422
423/* hardware clock configuration */
424#define DIB3000MB_REG_CLOCK ( 1027)
425#define DIB3000MB_CLOCK_DEFAULT (0x9000)
426#define DIB3000MB_CLOCK_DIVERSITY (0x92b0)
427
428/* power down config */
429#define DIB3000MB_REG_POWER_CONTROL ( 1028)
430#define DIB3000MB_POWER_DOWN ( 1)
431#define DIB3000MB_POWER_UP ( 0)
432
433/* electrical output mode */
434#define DIB3000MB_REG_ELECT_OUT_MODE ( 1029)
435#define DIB3000MB_ELECT_OUT_MODE_OFF ( 0)
436#define DIB3000MB_ELECT_OUT_MODE_ON ( 1)
437
438/* set the tuner i2c address */
439#define DIB3000MB_REG_TUNER ( 1089)
440
441/* monitoring registers (read only) */
442
443/* agc loop locked (size: 1) */
444#define DIB3000MB_REG_AGC_LOCK ( 324)
445
446/* agc power (size: 16) */
447#define DIB3000MB_REG_AGC_POWER ( 325)
448
449/* agc1 value (16) */
450#define DIB3000MB_REG_AGC1_VALUE ( 326)
451
452/* agc2 value (16) */
453#define DIB3000MB_REG_AGC2_VALUE ( 327)
454
455/* total RF power (16), can be used for signal strength */
456#define DIB3000MB_REG_RF_POWER ( 328)
457
458/* dds_frequency with offset (24) */
459#define DIB3000MB_REG_DDS_VALUE_MSB ( 339)
460#define DIB3000MB_REG_DDS_VALUE_LSB ( 340)
461
462/* timing offset signed (24) */
463#define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341)
464#define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342)
465
466/* fft start position (13) */
467#define DIB3000MB_REG_FFT_WINDOW_POS ( 353)
468
469/* carriers locked (1) */
470#define DIB3000MB_REG_CARRIER_LOCK ( 355)
471
472/* noise power (24) */
473#define DIB3000MB_REG_NOISE_POWER_MSB ( 372)
474#define DIB3000MB_REG_NOISE_POWER_LSB ( 373)
475
476#define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374)
477#define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375)
478
479/*
480 * signal power (16), this and the above can be
481 * used to calculate the signal/noise - ratio
482 */
483#define DIB3000MB_REG_SIGNAL_POWER ( 380)
484
485/* mer (24) */
486#define DIB3000MB_REG_MER_MSB ( 381)
487#define DIB3000MB_REG_MER_LSB ( 382)
488
489/*
490 * Transmission Parameter Signalling (TPS)
491 * the following registers can be used to get TPS-information.
492 * The values are according to the DVB-T standard.
493 */
494
495/* TPS locked (1) */
496#define DIB3000MB_REG_TPS_LOCK ( 394)
497
498/* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
499#define DIB3000MB_REG_TPS_QAM ( 398)
500
501/* hierarchy from TPS (1) */
502#define DIB3000MB_REG_TPS_HRCH ( 399)
503
504/* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
505#define DIB3000MB_REG_TPS_VIT_ALPHA ( 400)
506
507/* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
508#define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401)
509
510/* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
511#define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402)
512
513/* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
514#define DIB3000MB_REG_TPS_GUARD_TIME ( 403)
515
516/* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
517#define DIB3000MB_REG_TPS_FFT ( 404)
518
519/* cell id from TPS (16) */
520#define DIB3000MB_REG_TPS_CELL_ID ( 406)
521
522/* TPS (68) */
523#define DIB3000MB_REG_TPS_1 ( 408)
524#define DIB3000MB_REG_TPS_2 ( 409)
525#define DIB3000MB_REG_TPS_3 ( 410)
526#define DIB3000MB_REG_TPS_4 ( 411)
527#define DIB3000MB_REG_TPS_5 ( 412)
528
529/* bit error rate (before RS correction) (21) */
530#define DIB3000MB_REG_BER_MSB ( 414)
531#define DIB3000MB_REG_BER_LSB ( 415)
532
533/* packet error rate (uncorrected TS packets) (16) */
534#define DIB3000MB_REG_PACKET_ERROR_RATE ( 417)
535
536/* uncorrected packet count (16) */
537#define DIB3000MB_REG_UNC ( 420)
538
539/* viterbi locked (1) */
540#define DIB3000MB_REG_VIT_LCK ( 421)
541
542/* viterbi inidcator (16) */
543#define DIB3000MB_REG_VIT_INDICATOR ( 422)
544
545/* transport stream sync lock (1) */
546#define DIB3000MB_REG_TS_SYNC_LOCK ( 423)
547
548/* transport stream RS lock (1) */
549#define DIB3000MB_REG_TS_RS_LOCK ( 424)
550
551/* lock mask 0 value (1) */
552#define DIB3000MB_REG_LOCK0_VALUE ( 425)
553
554/* lock mask 1 value (1) */
555#define DIB3000MB_REG_LOCK1_VALUE ( 426)
556
557/* lock mask 2 value (1) */
558#define DIB3000MB_REG_LOCK2_VALUE ( 427)
559
560/* interrupt pending for auto search */
561#define DIB3000MB_REG_AS_IRQ_PENDING ( 434)
562
563#endif