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gerrit-public.fairphone.software / kernel / msm-4.9 / 7492e7ca0f954e26b3d0d44374240b66c21427e9 / . / arch / arm / boot / dts / tegra20.dtsi
blob: f3a09d0d45bc801a012fe7ea97f73548384ae9ad [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]7 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]8 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]11 interrupt-controller;
12 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]16 compatible = "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]18 interrupts = <0 104 0x04
19 0 105 0x04
20 0 106 0x04
21 0 107 0x04
22 0 108 0x04
23 0 109 0x04
24 0 110 0x04
25 0 111 0x04
26 0 112 0x04
27 0 113 0x04
28 0 114 0x04
29 0 115 0x04
30 0 116 0x04
31 0 117 0x04
32 0 118 0x04
33 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]34 };
35
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]36 ahb {
37 compatible = "nvidia,tegra20-ahb";
38 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]39 };
40
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]41 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]42 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]43 reg = <0x6000d000 0x1000>;
44 interrupts = <0 32 0x04
45 0 33 0x04
46 0 34 0x04
47 0 35 0x04
48 0 55 0x04
49 0 87 0x04
50 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]51 #gpio-cells = <2>;
52 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]53 #interrupt-cells = <2>;
54 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]55 };
56
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]57 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]58 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]59 reg = <0x70000014 0x10 /* Tri-state registers */
60 0x70000080 0x20 /* Mux registers */
61 0x700000a0 0x14 /* Pull-up/down registers */
62 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]63 };
64
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]65 das {
66 compatible = "nvidia,tegra20-das";
67 reg = <0x70000c00 0x80>;
68 };
69
70 tegra_i2s1: i2s@70002800 {
71 compatible = "nvidia,tegra20-i2s";
72 reg = <0x70002800 0x200>;
73 interrupts = <0 13 0x04>;
74 nvidia,dma-request-selector = <&apbdma 2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]75 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]76 };
77
78 tegra_i2s2: i2s@70002a00 {
79 compatible = "nvidia,tegra20-i2s";
80 reg = <0x70002a00 0x200>;
81 interrupts = <0 3 0x04>;
82 nvidia,dma-request-selector = <&apbdma 1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]83 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]84 };
85
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]86 serial@70006000 {
87 compatible = "nvidia,tegra20-uart";
88 reg = <0x70006000 0x40>;
89 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]90 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]91 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]92 };
93
94 serial@70006040 {
95 compatible = "nvidia,tegra20-uart";
96 reg = <0x70006040 0x40>;
97 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]98 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]99 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]100 };
101
102 serial@70006200 {
103 compatible = "nvidia,tegra20-uart";
104 reg = <0x70006200 0x100>;
105 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]106 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]107 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]108 };
109
110 serial@70006300 {
111 compatible = "nvidia,tegra20-uart";
112 reg = <0x70006300 0x100>;
113 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]114 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]115 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]116 };
117
118 serial@70006400 {
119 compatible = "nvidia,tegra20-uart";
120 reg = <0x70006400 0x100>;
121 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]122 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]123 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]124 };
125
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]126 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]127 compatible = "nvidia,tegra20-pwm";
128 reg = <0x7000a000 0x100>;
129 #pwm-cells = <2>;
130 };
131
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]132 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]133 compatible = "nvidia,tegra20-i2c";
134 reg = <0x7000c000 0x100>;
135 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]136 #address-cells = <1>;
137 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]138 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]139 };
140
141 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]142 compatible = "nvidia,tegra20-i2c";
143 reg = <0x7000c400 0x100>;
144 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]145 #address-cells = <1>;
146 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]147 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]148 };
149
150 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]151 compatible = "nvidia,tegra20-i2c";
152 reg = <0x7000c500 0x100>;
153 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]154 #address-cells = <1>;
155 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]156 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]157 };
158
159 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]160 compatible = "nvidia,tegra20-i2c-dvc";
161 reg = <0x7000d000 0x200>;
162 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]163 #address-cells = <1>;
164 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]165 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]166 };
167
168 pmc {
169 compatible = "nvidia,tegra20-pmc";
170 reg = <0x7000e400 0x400>;
171 };
172
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]173 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]174 compatible = "nvidia,tegra20-mc";
175 reg = <0x7000f000 0x024
176 0x7000f03c 0x3c4>;
177 interrupts = <0 77 0x04>;
178 };
179
180 gart {
181 compatible = "nvidia,tegra20-gart";
182 reg = <0x7000f024 0x00000018 /* controller registers */
183 0x58000000 0x02000000>; /* GART aperture */
184 };
185
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]186 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]187 compatible = "nvidia,tegra20-emc";
188 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]189 #address-cells = <1>;
190 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]191 };
192
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]193 usb@c5000000 {
194 compatible = "nvidia,tegra20-ehci", "usb-ehci";
195 reg = <0xc5000000 0x4000>;
196 interrupts = <0 20 0x04>;
197 phy_type = "utmi";
198 nvidia,has-legacy-mode;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]199 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]200 };
201
202 usb@c5004000 {
203 compatible = "nvidia,tegra20-ehci", "usb-ehci";
204 reg = <0xc5004000 0x4000>;
205 interrupts = <0 21 0x04>;
206 phy_type = "ulpi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]207 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]208 };
209
210 usb@c5008000 {
211 compatible = "nvidia,tegra20-ehci", "usb-ehci";
212 reg = <0xc5008000 0x4000>;
213 interrupts = <0 97 0x04>;
214 phy_type = "utmi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]215 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]216 };
217
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]218 sdhci@c8000000 {
219 compatible = "nvidia,tegra20-sdhci";
220 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]221 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]222 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]223 };
224
225 sdhci@c8000200 {
226 compatible = "nvidia,tegra20-sdhci";
227 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]228 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]229 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]230 };
231
232 sdhci@c8000400 {
233 compatible = "nvidia,tegra20-sdhci";
234 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]235 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]236 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]237 };
238
239 sdhci@c8000600 {
240 compatible = "nvidia,tegra20-sdhci";
241 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]242 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]243 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]244 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]245
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]246 pmu {
247 compatible = "arm,cortex-a9-pmu";
248 interrupts = <0 56 0x04
249 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]250 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]251};