| Padmavathi Venna | 74ac23a | 2011-12-26 16:42:15 +0900 | [diff] [blame^] | 1 | /* linux/arch/arm/mach-exynos4/setup-spi.c |
| 2 | * |
| 3 | * Copyright (C) 2011 Samsung Electronics Ltd. |
| 4 | * http://www.samsung.com/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/gpio.h> |
| 12 | #include <linux/platform_device.h> |
| 13 | |
| 14 | #include <plat/gpio-cfg.h> |
| 15 | #include <plat/s3c64xx-spi.h> |
| 16 | |
| 17 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
| 18 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { |
| 19 | .fifo_lvl_mask = 0x1ff, |
| 20 | .rx_lvl_offset = 15, |
| 21 | .high_speed = 1, |
| 22 | .clk_from_cmu = true, |
| 23 | .tx_st_done = 25, |
| 24 | }; |
| 25 | |
| 26 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) |
| 27 | { |
| 28 | s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); |
| 29 | s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); |
| 30 | s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, |
| 31 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
| 32 | return 0; |
| 33 | } |
| 34 | #endif |
| 35 | |
| 36 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
| 37 | struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { |
| 38 | .fifo_lvl_mask = 0x7f, |
| 39 | .rx_lvl_offset = 15, |
| 40 | .high_speed = 1, |
| 41 | .clk_from_cmu = true, |
| 42 | .tx_st_done = 25, |
| 43 | }; |
| 44 | |
| 45 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) |
| 46 | { |
| 47 | s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); |
| 48 | s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); |
| 49 | s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, |
| 50 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
| 51 | return 0; |
| 52 | } |
| 53 | #endif |
| 54 | |
| 55 | #ifdef CONFIG_S3C64XX_DEV_SPI2 |
| 56 | struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { |
| 57 | .fifo_lvl_mask = 0x7f, |
| 58 | .rx_lvl_offset = 15, |
| 59 | .high_speed = 1, |
| 60 | .clk_from_cmu = true, |
| 61 | .tx_st_done = 25, |
| 62 | }; |
| 63 | |
| 64 | int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) |
| 65 | { |
| 66 | s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); |
| 67 | s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); |
| 68 | s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, |
| 69 | S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP); |
| 70 | return 0; |
| 71 | } |
| 72 | #endif |