Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $ |
| 2 | * pgtable.h: SpitFire page table operations. |
| 3 | * |
| 4 | * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) |
| 5 | * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
| 6 | */ |
| 7 | |
| 8 | #ifndef _SPARC64_PGTABLE_H |
| 9 | #define _SPARC64_PGTABLE_H |
| 10 | |
| 11 | /* This file contains the functions and defines necessary to modify and use |
| 12 | * the SpitFire page tables. |
| 13 | */ |
| 14 | |
| 15 | #include <asm-generic/pgtable-nopud.h> |
| 16 | |
| 17 | #include <linux/config.h> |
| 18 | #include <linux/compiler.h> |
| 19 | #include <asm/types.h> |
| 20 | #include <asm/spitfire.h> |
| 21 | #include <asm/asi.h> |
| 22 | #include <asm/system.h> |
| 23 | #include <asm/page.h> |
| 24 | #include <asm/processor.h> |
| 25 | #include <asm/const.h> |
| 26 | |
David S. Miller | 729b4f7 | 2005-09-20 12:18:38 -0700 | [diff] [blame] | 27 | /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB). |
David S. Miller | 74bf431 | 2006-01-31 18:29:18 -0800 | [diff] [blame^] | 28 | * The page copy blockops can use 0x2000000 to 0x4000000. |
| 29 | * The TSB is mapped in the 0x4000000 to 0x6000000 range. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * The PROM resides in an area spanning 0xf0000000 to 0x100000000. |
David S. Miller | 729b4f7 | 2005-09-20 12:18:38 -0700 | [diff] [blame] | 31 | * The vmalloc area spans 0x100000000 to 0x200000000. |
| 32 | * Since modules need to be in the lowest 32-bits of the address space, |
| 33 | * we place them right before the OBP area from 0x10000000 to 0xf0000000. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | * There is a single static kernel PMD which maps from 0x0 to address |
| 35 | * 0x400000000. |
| 36 | */ |
David S. Miller | 729b4f7 | 2005-09-20 12:18:38 -0700 | [diff] [blame] | 37 | #define TLBTEMP_BASE _AC(0x0000000002000000,UL) |
David S. Miller | 74bf431 | 2006-01-31 18:29:18 -0800 | [diff] [blame^] | 38 | #define TSBMAP_BASE _AC(0x0000000004000000,UL) |
David S. Miller | 729b4f7 | 2005-09-20 12:18:38 -0700 | [diff] [blame] | 39 | #define MODULES_VADDR _AC(0x0000000010000000,UL) |
| 40 | #define MODULES_LEN _AC(0x00000000e0000000,UL) |
| 41 | #define MODULES_END _AC(0x00000000f0000000,UL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) |
| 43 | #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) |
David S. Miller | 729b4f7 | 2005-09-20 12:18:38 -0700 | [diff] [blame] | 44 | #define VMALLOC_START _AC(0x0000000100000000,UL) |
| 45 | #define VMALLOC_END _AC(0x0000000200000000,UL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
| 47 | /* XXX All of this needs to be rethought so we can take advantage |
| 48 | * XXX cheetah's full 64-bit virtual address space, ie. no more hole |
| 49 | * XXX in the middle like on spitfire. -DaveM |
| 50 | */ |
| 51 | /* |
| 52 | * Given a virtual address, the lowest PAGE_SHIFT bits determine offset |
| 53 | * into the page; the next higher PAGE_SHIFT-3 bits determine the pte# |
| 54 | * in the proper pagetable (the -3 is from the 8 byte ptes, and each page |
| 55 | * table is a single page long). The next higher PMD_BITS determine pmd# |
| 56 | * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2) |
| 57 | * since the pmd entries are 4 bytes, and each pmd page is a single page |
| 58 | * long). Finally, the higher few bits determine pgde#. |
| 59 | */ |
| 60 | |
| 61 | /* PMD_SHIFT determines the size of the area a second-level page |
| 62 | * table can map |
| 63 | */ |
| 64 | #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) |
David S. Miller | 5642530 | 2005-09-25 16:46:57 -0700 | [diff] [blame] | 65 | #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | #define PMD_MASK (~(PMD_SIZE-1)) |
| 67 | #define PMD_BITS (PAGE_SHIFT - 2) |
| 68 | |
| 69 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ |
| 70 | #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS) |
David S. Miller | 5642530 | 2005-09-25 16:46:57 -0700 | [diff] [blame] | 71 | #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
| 73 | #define PGDIR_BITS (PAGE_SHIFT - 2) |
| 74 | |
| 75 | #ifndef __ASSEMBLY__ |
| 76 | |
| 77 | #include <linux/sched.h> |
| 78 | |
| 79 | /* Entries per page directory level. */ |
| 80 | #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) |
| 81 | #define PTRS_PER_PMD (1UL << PMD_BITS) |
| 82 | #define PTRS_PER_PGD (1UL << PGDIR_BITS) |
| 83 | |
| 84 | /* Kernel has a separate 44bit address space. */ |
Hugh Dickins | d455a36 | 2005-04-19 13:29:23 -0700 | [diff] [blame] | 85 | #define FIRST_USER_ADDRESS 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | #define pte_ERROR(e) __builtin_trap() |
| 88 | #define pmd_ERROR(e) __builtin_trap() |
| 89 | #define pgd_ERROR(e) __builtin_trap() |
| 90 | |
| 91 | #endif /* !(__ASSEMBLY__) */ |
| 92 | |
| 93 | /* Spitfire/Cheetah TTE bits. */ |
| 94 | #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ |
| 95 | #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/ |
| 96 | #define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */ |
| 97 | #define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */ |
| 98 | #define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */ |
| 99 | #define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */ |
| 100 | #define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */ |
| 101 | #define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */ |
| 102 | #define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ |
David S. Miller | f16af55 | 2005-09-27 22:37:08 -0700 | [diff] [blame] | 103 | #define _PAGE_RES1 _AC(0x0002000000000000,UL) /* Reserved */ |
| 104 | #define _PAGE_SZ32MB _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ |
| 105 | #define _PAGE_SZ256MB _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | #define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ |
| 107 | #define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */ |
| 108 | #define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/ |
| 109 | #define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */ |
| 110 | #define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */ |
| 111 | #define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */ |
| 112 | #define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ |
| 113 | #define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ |
| 114 | #define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */ |
| 115 | #define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */ |
| 116 | #define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */ |
| 117 | #define _PAGE_G _AC(0x0000000000000001,UL) /* Global */ |
| 118 | |
| 119 | /* Here are the SpitFire software bits we use in the TTE's. |
| 120 | * |
| 121 | * WARNING: If you are going to try and start using some |
| 122 | * of the soft2 bits, you will need to make |
| 123 | * modifications to the swap entry implementation. |
| 124 | * For example, one thing that could happen is that |
| 125 | * swp_entry_to_pte() would BUG_ON() if you tried |
| 126 | * to use one of the soft2 bits for _PAGE_FILE. |
| 127 | * |
| 128 | * Like other architectures, I have aliased _PAGE_FILE with |
| 129 | * _PAGE_MODIFIED. This works because _PAGE_FILE is never |
| 130 | * interpreted that way unless _PAGE_PRESENT is clear. |
| 131 | */ |
| 132 | #define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */ |
| 133 | #define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */ |
| 134 | #define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */ |
| 135 | #define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ |
| 136 | #define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */ |
| 137 | #define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */ |
| 138 | #define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */ |
| 139 | |
| 140 | #if PAGE_SHIFT == 13 |
| 141 | #define _PAGE_SZBITS _PAGE_SZ8K |
| 142 | #elif PAGE_SHIFT == 16 |
| 143 | #define _PAGE_SZBITS _PAGE_SZ64K |
| 144 | #elif PAGE_SHIFT == 19 |
| 145 | #define _PAGE_SZBITS _PAGE_SZ512K |
| 146 | #elif PAGE_SHIFT == 22 |
| 147 | #define _PAGE_SZBITS _PAGE_SZ4MB |
| 148 | #else |
| 149 | #error Wrong PAGE_SHIFT specified |
| 150 | #endif |
| 151 | |
| 152 | #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) |
| 153 | #define _PAGE_SZHUGE _PAGE_SZ4MB |
| 154 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) |
| 155 | #define _PAGE_SZHUGE _PAGE_SZ512K |
| 156 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) |
| 157 | #define _PAGE_SZHUGE _PAGE_SZ64K |
| 158 | #endif |
| 159 | |
| 160 | #define _PAGE_CACHE (_PAGE_CP | _PAGE_CV) |
| 161 | |
| 162 | #define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W) |
| 163 | #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R) |
| 164 | #define __PRIV_BITS _PAGE_P |
| 165 | |
| 166 | #define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE) |
| 167 | |
| 168 | /* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */ |
| 169 | #define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ |
| 170 | __ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC) |
| 171 | |
| 172 | #define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ |
| 173 | __ACCESS_BITS | _PAGE_EXEC) |
| 174 | |
| 175 | #define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ |
| 176 | __ACCESS_BITS | _PAGE_EXEC) |
| 177 | |
| 178 | #define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ |
| 179 | __PRIV_BITS | \ |
| 180 | __ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC) |
| 181 | |
| 182 | #define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ |
| 183 | _PAGE_CACHE | \ |
| 184 | __ACCESS_BITS | _PAGE_WRITE) |
| 185 | |
| 186 | #define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ |
| 187 | _PAGE_CACHE | __ACCESS_BITS) |
| 188 | |
| 189 | #define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ |
| 190 | _PAGE_CACHE | __ACCESS_BITS) |
| 191 | |
| 192 | #define _PFN_MASK _PAGE_PADDR |
| 193 | |
| 194 | #define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \ |
| 195 | __ACCESS_BITS | _PAGE_E) |
| 196 | |
| 197 | #define __P000 PAGE_NONE |
| 198 | #define __P001 PAGE_READONLY_NOEXEC |
| 199 | #define __P010 PAGE_COPY_NOEXEC |
| 200 | #define __P011 PAGE_COPY_NOEXEC |
| 201 | #define __P100 PAGE_READONLY |
| 202 | #define __P101 PAGE_READONLY |
| 203 | #define __P110 PAGE_COPY |
| 204 | #define __P111 PAGE_COPY |
| 205 | |
| 206 | #define __S000 PAGE_NONE |
| 207 | #define __S001 PAGE_READONLY_NOEXEC |
| 208 | #define __S010 PAGE_SHARED_NOEXEC |
| 209 | #define __S011 PAGE_SHARED_NOEXEC |
| 210 | #define __S100 PAGE_READONLY |
| 211 | #define __S101 PAGE_READONLY |
| 212 | #define __S110 PAGE_SHARED |
| 213 | #define __S111 PAGE_SHARED |
| 214 | |
| 215 | #ifndef __ASSEMBLY__ |
| 216 | |
| 217 | extern unsigned long phys_base; |
| 218 | extern unsigned long pfn_base; |
| 219 | |
| 220 | extern struct page *mem_map_zero; |
| 221 | #define ZERO_PAGE(vaddr) (mem_map_zero) |
| 222 | |
| 223 | /* PFNs are real physical page numbers. However, mem_map only begins to record |
| 224 | * per-page information starting at pfn_base. This is to handle systems where |
| 225 | * the first physical page in the machine is at some huge physical address, |
| 226 | * such as 4GB. This is common on a partitioned E10000, for example. |
| 227 | */ |
| 228 | |
| 229 | #define pfn_pte(pfn, prot) \ |
| 230 | __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS) |
| 231 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) |
| 232 | |
| 233 | #define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT) |
| 234 | #define pte_page(x) pfn_to_page(pte_pfn(x)) |
| 235 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) |
| 237 | { |
| 238 | pte_t __pte; |
| 239 | const unsigned long preserve_mask = (_PFN_MASK | |
| 240 | _PAGE_MODIFIED | _PAGE_ACCESSED | |
| 241 | _PAGE_CACHE | _PAGE_E | |
| 242 | _PAGE_PRESENT | _PAGE_SZBITS); |
| 243 | |
| 244 | pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) | |
| 245 | (pgprot_val(new_prot) & ~preserve_mask); |
| 246 | |
| 247 | return __pte; |
| 248 | } |
| 249 | #define pmd_set(pmdp, ptep) \ |
| 250 | (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL)) |
| 251 | #define pud_set(pudp, pmdp) \ |
| 252 | (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL)) |
| 253 | #define __pmd_page(pmd) \ |
| 254 | ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL))) |
| 255 | #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) |
| 256 | #define pud_page(pud) \ |
| 257 | ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL))) |
| 258 | #define pte_none(pte) (!pte_val(pte)) |
| 259 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) |
| 260 | #define pmd_none(pmd) (!pmd_val(pmd)) |
| 261 | #define pmd_bad(pmd) (0) |
| 262 | #define pmd_present(pmd) (pmd_val(pmd) != 0U) |
| 263 | #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U) |
| 264 | #define pud_none(pud) (!pud_val(pud)) |
| 265 | #define pud_bad(pud) (0) |
| 266 | #define pud_present(pud) (pud_val(pud) != 0U) |
| 267 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0U) |
| 268 | |
| 269 | /* The following only work if pte_present() is true. |
| 270 | * Undefined behaviour if not.. |
| 271 | */ |
| 272 | #define pte_read(pte) (pte_val(pte) & _PAGE_READ) |
| 273 | #define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC) |
| 274 | #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE) |
| 275 | #define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED) |
| 276 | #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED) |
| 277 | #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W))) |
| 278 | #define pte_rdprotect(pte) \ |
| 279 | (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ)) |
| 280 | #define pte_mkclean(pte) \ |
| 281 | (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W))) |
| 282 | #define pte_mkold(pte) \ |
| 283 | (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED)) |
| 284 | |
| 285 | /* Permanent address of a page. */ |
| 286 | #define __page_address(page) page_address(page) |
| 287 | |
| 288 | /* Be very careful when you change these three, they are delicate. */ |
| 289 | #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R)) |
| 290 | #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE)) |
| 291 | #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W)) |
David Gibson | 63551ae | 2005-06-21 17:14:44 -0700 | [diff] [blame] | 292 | #define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | |
| 294 | /* to find an entry in a page-table-directory. */ |
| 295 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) |
| 296 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
| 297 | |
| 298 | /* to find an entry in a kernel page-table-directory */ |
| 299 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) |
| 300 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | /* Find an entry in the second-level page table.. */ |
| 302 | #define pmd_offset(pudp, address) \ |
| 303 | ((pmd_t *) pud_page(*(pudp)) + \ |
| 304 | (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) |
| 305 | |
| 306 | /* Find an entry in the third-level page table.. */ |
| 307 | #define pte_index(dir, address) \ |
| 308 | ((pte_t *) __pmd_page(*(dir)) + \ |
| 309 | ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) |
| 310 | #define pte_offset_kernel pte_index |
| 311 | #define pte_offset_map pte_index |
| 312 | #define pte_offset_map_nested pte_index |
| 313 | #define pte_unmap(pte) do { } while (0) |
| 314 | #define pte_unmap_nested(pte) do { } while (0) |
| 315 | |
| 316 | /* Actual page table PTE updates. */ |
| 317 | extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig); |
| 318 | |
| 319 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) |
| 320 | { |
| 321 | pte_t orig = *ptep; |
| 322 | |
| 323 | *ptep = pte; |
| 324 | |
| 325 | /* It is more efficient to let flush_tlb_kernel_range() |
| 326 | * handle init_mm tlb flushes. |
| 327 | */ |
| 328 | if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID)) |
| 329 | tlb_batch_add(mm, addr, ptep, orig); |
| 330 | } |
| 331 | |
| 332 | #define pte_clear(mm,addr,ptep) \ |
| 333 | set_pte_at((mm), (addr), (ptep), __pte(0UL)) |
| 334 | |
David S. Miller | 5642530 | 2005-09-25 16:46:57 -0700 | [diff] [blame] | 335 | extern pgd_t swapper_pg_dir[2048]; |
| 336 | extern pmd_t swapper_low_pmd_dir[2048]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | |
David S. Miller | 801ab3c | 2005-09-28 21:31:25 -0700 | [diff] [blame] | 338 | extern void paging_init(void); |
David S. Miller | 1014757 | 2005-09-28 21:46:43 -0700 | [diff] [blame] | 339 | extern unsigned long find_ecache_flush_span(unsigned long size); |
David S. Miller | 801ab3c | 2005-09-28 21:31:25 -0700 | [diff] [blame] | 340 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | /* These do nothing with the way I have things setup. */ |
| 342 | #define mmu_lockarea(vaddr, len) (vaddr) |
| 343 | #define mmu_unlockarea(vaddr, len) do { } while(0) |
| 344 | |
| 345 | struct vm_area_struct; |
| 346 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); |
| 347 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | /* Encode and de-code a swap entry */ |
| 349 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) |
| 350 | #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) |
| 351 | #define __swp_entry(type, offset) \ |
| 352 | ( (swp_entry_t) \ |
| 353 | { \ |
| 354 | (((long)(type) << PAGE_SHIFT) | \ |
| 355 | ((long)(offset) << (PAGE_SHIFT + 8UL))) \ |
| 356 | } ) |
| 357 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) |
| 358 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) |
| 359 | |
| 360 | /* File offset in PTE support. */ |
| 361 | #define pte_file(pte) (pte_val(pte) & _PAGE_FILE) |
| 362 | #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) |
| 363 | #define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE)) |
| 364 | #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) |
| 365 | |
| 366 | extern unsigned long prom_virt_to_phys(unsigned long, int *); |
| 367 | |
| 368 | static __inline__ unsigned long |
| 369 | sun4u_get_pte (unsigned long addr) |
| 370 | { |
| 371 | pgd_t *pgdp; |
| 372 | pud_t *pudp; |
| 373 | pmd_t *pmdp; |
| 374 | pte_t *ptep; |
| 375 | |
| 376 | if (addr >= PAGE_OFFSET) |
| 377 | return addr & _PAGE_PADDR; |
| 378 | if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS)) |
| 379 | return prom_virt_to_phys(addr, NULL); |
| 380 | pgdp = pgd_offset_k(addr); |
| 381 | pudp = pud_offset(pgdp, addr); |
| 382 | pmdp = pmd_offset(pudp, addr); |
| 383 | ptep = pte_offset_kernel(pmdp, addr); |
| 384 | return pte_val(*ptep) & _PAGE_PADDR; |
| 385 | } |
| 386 | |
| 387 | static __inline__ unsigned long |
| 388 | __get_phys (unsigned long addr) |
| 389 | { |
| 390 | return sun4u_get_pte (addr); |
| 391 | } |
| 392 | |
| 393 | static __inline__ int |
| 394 | __get_iospace (unsigned long addr) |
| 395 | { |
| 396 | return ((sun4u_get_pte (addr) & 0xf0000000) >> 28); |
| 397 | } |
| 398 | |
| 399 | extern unsigned long *sparc64_valid_addr_bitmap; |
| 400 | |
| 401 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ |
| 402 | #define kern_addr_valid(addr) \ |
| 403 | (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap)) |
| 404 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, |
| 406 | unsigned long pfn, |
| 407 | unsigned long size, pgprot_t prot); |
| 408 | |
David S. Miller | d7be828 | 2005-04-21 21:41:33 -0700 | [diff] [blame] | 409 | /* Clear virtual and physical cachability, set side-effect bit. */ |
| 410 | #define pgprot_noncached(prot) \ |
| 411 | (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \ |
| 412 | _PAGE_E)) |
| 413 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | /* |
| 415 | * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in |
| 416 | * its high 4 bits. These macros/functions put it there or get it from there. |
| 417 | */ |
| 418 | #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) |
| 419 | #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) |
| 420 | #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) |
| 421 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | #include <asm-generic/pgtable.h> |
| 423 | |
| 424 | /* We provide our own get_unmapped_area to cope with VA holes for userland */ |
| 425 | #define HAVE_ARCH_UNMAPPED_AREA |
| 426 | |
| 427 | /* We provide a special get_unmapped_area for framebuffer mmaps to try and use |
| 428 | * the largest alignment possible such that larget PTEs can be used. |
| 429 | */ |
| 430 | extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, |
| 431 | unsigned long, unsigned long, |
| 432 | unsigned long); |
| 433 | #define HAVE_ARCH_FB_UNMAPPED_AREA |
| 434 | |
| 435 | /* |
| 436 | * No page table caches to initialise |
| 437 | */ |
| 438 | #define pgtable_cache_init() do { } while (0) |
| 439 | |
| 440 | extern void check_pgt_cache(void); |
| 441 | |
| 442 | #endif /* !(__ASSEMBLY__) */ |
| 443 | |
| 444 | #endif /* !(_SPARC64_PGTABLE_H) */ |