David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 14 | #include <linux/clk.h> |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/spmi.h> |
| 24 | |
| 25 | /* PMIC Arbiter debug register offsets */ |
| 26 | #define PMIC_ARB_DEBUG_CMD0 0x00 |
| 27 | #define PMIC_ARB_DEBUG_CMD1 0x04 |
| 28 | #define PMIC_ARB_DEBUG_CMD2 0x08 |
| 29 | #define PMIC_ARB_DEBUG_CMD3 0x0C |
| 30 | #define PMIC_ARB_DEBUG_STATUS 0x14 |
| 31 | #define PMIC_ARB_DEBUG_WDATA(n) (0x18 + 4 * (n)) |
| 32 | #define PMIC_ARB_DEBUG_RDATA(n) (0x38 + 4 * (n)) |
| 33 | |
| 34 | /* Transaction status flag bits */ |
| 35 | enum pmic_arb_chnl_status { |
| 36 | PMIC_ARB_STATUS_DONE = BIT(0), |
| 37 | PMIC_ARB_STATUS_FAILURE = BIT(1), |
| 38 | PMIC_ARB_STATUS_DENIED = BIT(2), |
| 39 | PMIC_ARB_STATUS_DROPPED = BIT(3), |
| 40 | }; |
| 41 | |
| 42 | /* Command Opcodes */ |
| 43 | enum pmic_arb_cmd_op_code { |
| 44 | PMIC_ARB_OP_EXT_WRITEL = 0, |
| 45 | PMIC_ARB_OP_EXT_READL = 1, |
| 46 | PMIC_ARB_OP_EXT_WRITE = 2, |
| 47 | PMIC_ARB_OP_RESET = 3, |
| 48 | PMIC_ARB_OP_SLEEP = 4, |
| 49 | PMIC_ARB_OP_SHUTDOWN = 5, |
| 50 | PMIC_ARB_OP_WAKEUP = 6, |
| 51 | PMIC_ARB_OP_AUTHENTICATE = 7, |
| 52 | PMIC_ARB_OP_MSTR_READ = 8, |
| 53 | PMIC_ARB_OP_MSTR_WRITE = 9, |
| 54 | PMIC_ARB_OP_EXT_READ = 13, |
| 55 | PMIC_ARB_OP_WRITE = 14, |
| 56 | PMIC_ARB_OP_READ = 15, |
| 57 | PMIC_ARB_OP_ZERO_WRITE = 16, |
| 58 | }; |
| 59 | |
| 60 | #define PMIC_ARB_TIMEOUT_US 100 |
| 61 | #define PMIC_ARB_MAX_TRANS_BYTES 8 |
| 62 | #define PMIC_ARB_MAX_SID 0xF |
| 63 | |
| 64 | /** |
| 65 | * spmi_pmic_arb_debug - SPMI PMIC Arbiter debug object |
| 66 | * |
| 67 | * @addr: base address of SPMI PMIC arbiter debug module |
| 68 | * @lock: lock to synchronize accesses. |
| 69 | */ |
| 70 | struct spmi_pmic_arb_debug { |
| 71 | void __iomem *addr; |
| 72 | raw_spinlock_t lock; |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 73 | struct clk *clock; |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | static inline void pmic_arb_debug_write(struct spmi_pmic_arb_debug *pa, |
| 77 | u32 offset, u32 val) |
| 78 | { |
| 79 | writel_relaxed(val, pa->addr + offset); |
| 80 | } |
| 81 | |
| 82 | static inline u32 pmic_arb_debug_read(struct spmi_pmic_arb_debug *pa, |
| 83 | u32 offset) |
| 84 | { |
| 85 | return readl_relaxed(pa->addr + offset); |
| 86 | } |
| 87 | |
| 88 | /* pa->lock must be held by the caller. */ |
| 89 | static int pmic_arb_debug_wait_for_done(struct spmi_controller *ctrl) |
| 90 | { |
| 91 | struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl); |
| 92 | u32 status = 0; |
| 93 | u32 timeout = PMIC_ARB_TIMEOUT_US; |
| 94 | |
| 95 | while (timeout--) { |
| 96 | status = pmic_arb_debug_read(pa, PMIC_ARB_DEBUG_STATUS); |
| 97 | |
| 98 | if (status & PMIC_ARB_STATUS_DONE) { |
| 99 | if (status & PMIC_ARB_STATUS_DENIED) { |
| 100 | dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n", |
| 101 | __func__, status); |
| 102 | return -EPERM; |
| 103 | } |
| 104 | |
| 105 | if (status & PMIC_ARB_STATUS_FAILURE) { |
| 106 | dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n", |
| 107 | __func__, status); |
| 108 | return -EIO; |
| 109 | } |
| 110 | |
| 111 | if (status & PMIC_ARB_STATUS_DROPPED) { |
| 112 | dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n", |
| 113 | __func__, status); |
| 114 | return -EIO; |
| 115 | } |
| 116 | |
| 117 | return 0; |
| 118 | } |
| 119 | udelay(1); |
| 120 | } |
| 121 | |
| 122 | dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n", __func__, status); |
| 123 | return -ETIMEDOUT; |
| 124 | } |
| 125 | |
| 126 | /* pa->lock must be held by the caller. */ |
| 127 | static int pmic_arb_debug_issue_command(struct spmi_controller *ctrl, u8 opc, |
| 128 | u8 sid, u16 addr, size_t len) |
| 129 | { |
| 130 | struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl); |
| 131 | u16 pid = (addr >> 8) & 0xFF; |
| 132 | u16 offset = addr & 0xFF; |
| 133 | u8 byte_count = len - 1; |
| 134 | |
| 135 | if (byte_count >= PMIC_ARB_MAX_TRANS_BYTES) { |
| 136 | dev_err(&ctrl->dev, "pmic-arb supports 1 to %d bytes per transaction, but %zu requested", |
| 137 | PMIC_ARB_MAX_TRANS_BYTES, len); |
| 138 | return -EINVAL; |
| 139 | } |
| 140 | |
| 141 | if (sid > PMIC_ARB_MAX_SID) { |
| 142 | dev_err(&ctrl->dev, "pmic-arb supports sid 0 to %u, but %u requested", |
| 143 | PMIC_ARB_MAX_SID, sid); |
| 144 | return -EINVAL; |
| 145 | } |
| 146 | |
| 147 | pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD3, offset); |
| 148 | pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD2, pid); |
| 149 | pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD1, (byte_count << 4) | sid); |
| 150 | |
| 151 | /* Start the transaction */ |
| 152 | pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_CMD0, opc << 1); |
| 153 | |
| 154 | return pmic_arb_debug_wait_for_done(ctrl); |
| 155 | } |
| 156 | |
| 157 | /* Non-data command */ |
| 158 | static int pmic_arb_debug_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) |
| 159 | { |
| 160 | dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); |
| 161 | |
| 162 | /* Check for valid non-data command */ |
| 163 | if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) |
| 164 | return -EINVAL; |
| 165 | |
| 166 | return -EOPNOTSUPP; |
| 167 | } |
| 168 | |
| 169 | static int pmic_arb_debug_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| 170 | u16 addr, u8 *buf, size_t len) |
| 171 | { |
| 172 | struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl); |
| 173 | unsigned long flags; |
| 174 | int i, rc; |
| 175 | |
| 176 | /* Check the opcode */ |
| 177 | if (opc >= 0x60 && opc <= 0x7F) |
| 178 | opc = PMIC_ARB_OP_READ; |
| 179 | else if (opc >= 0x20 && opc <= 0x2F) |
| 180 | opc = PMIC_ARB_OP_EXT_READ; |
| 181 | else if (opc >= 0x38 && opc <= 0x3F) |
| 182 | opc = PMIC_ARB_OP_EXT_READL; |
| 183 | else |
| 184 | return -EINVAL; |
| 185 | |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 186 | rc = clk_prepare_enable(pa->clock); |
| 187 | if (rc) { |
| 188 | pr_err("%s: failed to enable core clock, rc=%d\n", |
| 189 | __func__, rc); |
| 190 | return rc; |
| 191 | } |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 192 | raw_spin_lock_irqsave(&pa->lock, flags); |
| 193 | |
| 194 | rc = pmic_arb_debug_issue_command(ctrl, opc, sid, addr, len); |
| 195 | if (rc) |
| 196 | goto done; |
| 197 | |
| 198 | /* Read data from FIFO */ |
| 199 | for (i = 0; i < len; i++) |
| 200 | buf[i] = pmic_arb_debug_read(pa, PMIC_ARB_DEBUG_RDATA(i)); |
| 201 | done: |
| 202 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 203 | clk_disable_unprepare(pa->clock); |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 204 | |
| 205 | return rc; |
| 206 | } |
| 207 | |
| 208 | static int pmic_arb_debug_write_cmd(struct spmi_controller *ctrl, u8 opc, |
| 209 | u8 sid, u16 addr, const u8 *buf, size_t len) |
| 210 | { |
| 211 | struct spmi_pmic_arb_debug *pa = spmi_controller_get_drvdata(ctrl); |
| 212 | unsigned long flags; |
| 213 | int i, rc; |
| 214 | |
| 215 | if (len > PMIC_ARB_MAX_TRANS_BYTES) { |
| 216 | dev_err(&ctrl->dev, "pmic-arb supports 1 to %d bytes per transaction, but %zu requested", |
| 217 | PMIC_ARB_MAX_TRANS_BYTES, len); |
| 218 | return -EINVAL; |
| 219 | } |
| 220 | |
| 221 | /* Check the opcode */ |
| 222 | if (opc >= 0x40 && opc <= 0x5F) |
| 223 | opc = PMIC_ARB_OP_WRITE; |
| 224 | else if (opc >= 0x00 && opc <= 0x0F) |
| 225 | opc = PMIC_ARB_OP_EXT_WRITE; |
| 226 | else if (opc >= 0x30 && opc <= 0x37) |
| 227 | opc = PMIC_ARB_OP_EXT_WRITEL; |
| 228 | else if (opc >= 0x80) |
| 229 | opc = PMIC_ARB_OP_ZERO_WRITE; |
| 230 | else |
| 231 | return -EINVAL; |
| 232 | |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 233 | rc = clk_prepare_enable(pa->clock); |
| 234 | if (rc) { |
| 235 | pr_err("%s: failed to enable core clock, rc=%d\n", |
| 236 | __func__, rc); |
| 237 | return rc; |
| 238 | } |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 239 | raw_spin_lock_irqsave(&pa->lock, flags); |
| 240 | |
| 241 | /* Write data to FIFO */ |
| 242 | for (i = 0; i < len; i++) |
| 243 | pmic_arb_debug_write(pa, PMIC_ARB_DEBUG_WDATA(i), buf[i]); |
| 244 | |
| 245 | rc = pmic_arb_debug_issue_command(ctrl, opc, sid, addr, len); |
| 246 | |
| 247 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 248 | clk_disable_unprepare(pa->clock); |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 249 | |
| 250 | return rc; |
| 251 | } |
| 252 | |
| 253 | static int spmi_pmic_arb_debug_probe(struct platform_device *pdev) |
| 254 | { |
| 255 | struct spmi_pmic_arb_debug *pa; |
| 256 | struct spmi_controller *ctrl; |
| 257 | struct resource *res; |
| 258 | int rc; |
| 259 | u32 fuse_val, fuse_bit; |
| 260 | void __iomem *fuse_addr; |
| 261 | |
| 262 | /* Check if the debug bus is disabled by a fuse. */ |
| 263 | rc = of_property_read_u32(pdev->dev.of_node, "qcom,fuse-disable-bit", |
| 264 | &fuse_bit); |
| 265 | if (!rc) { |
| 266 | if (fuse_bit > 31) { |
| 267 | dev_err(&pdev->dev, "qcom,fuse-disable-bit supports values 0 to 31, but %u specified\n", |
| 268 | fuse_bit); |
| 269 | return -EINVAL; |
| 270 | } |
| 271 | |
| 272 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 273 | "fuse"); |
| 274 | if (!res) { |
| 275 | dev_err(&pdev->dev, "fuse address not specified\n"); |
| 276 | return -EINVAL; |
| 277 | } |
| 278 | |
| 279 | fuse_addr = devm_ioremap_resource(&pdev->dev, res); |
| 280 | if (IS_ERR(fuse_addr)) |
| 281 | return PTR_ERR(fuse_addr); |
| 282 | |
| 283 | fuse_val = readl_relaxed(fuse_addr); |
| 284 | devm_iounmap(&pdev->dev, fuse_addr); |
| 285 | |
| 286 | if (fuse_val & BIT(fuse_bit)) { |
| 287 | dev_err(&pdev->dev, "SPMI PMIC arbiter debug bus disabled by fuse\n"); |
| 288 | return -ENODEV; |
| 289 | } |
| 290 | } |
| 291 | |
| 292 | |
| 293 | ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); |
| 294 | if (!ctrl) |
| 295 | return -ENOMEM; |
| 296 | |
| 297 | pa = spmi_controller_get_drvdata(ctrl); |
| 298 | |
| 299 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
| 300 | if (!res) { |
| 301 | dev_err(&pdev->dev, "core address not specified\n"); |
| 302 | rc = -EINVAL; |
| 303 | goto err_put_ctrl; |
| 304 | } |
| 305 | |
| 306 | pa->addr = devm_ioremap_resource(&ctrl->dev, res); |
| 307 | if (IS_ERR(pa->addr)) { |
| 308 | rc = PTR_ERR(pa->addr); |
| 309 | goto err_put_ctrl; |
| 310 | } |
| 311 | |
David Collins | 9a33914 | 2017-04-20 16:34:46 -0700 | [diff] [blame] | 312 | if (of_find_property(pdev->dev.of_node, "clock-names", NULL)) { |
| 313 | pa->clock = devm_clk_get(&pdev->dev, "core_clk"); |
| 314 | if (IS_ERR(pa->clock)) { |
| 315 | rc = PTR_ERR(pa->clock); |
| 316 | if (rc != -EPROBE_DEFER) |
| 317 | dev_err(&pdev->dev, "unable to request core clock, rc=%d\n", |
| 318 | rc); |
| 319 | goto err_put_ctrl; |
| 320 | } |
| 321 | } |
| 322 | |
David Collins | 858c33a | 2017-04-10 17:27:47 -0700 | [diff] [blame] | 323 | platform_set_drvdata(pdev, ctrl); |
| 324 | raw_spin_lock_init(&pa->lock); |
| 325 | |
| 326 | ctrl->cmd = pmic_arb_debug_cmd; |
| 327 | ctrl->read_cmd = pmic_arb_debug_read_cmd; |
| 328 | ctrl->write_cmd = pmic_arb_debug_write_cmd; |
| 329 | |
| 330 | rc = spmi_controller_add(ctrl); |
| 331 | if (rc) |
| 332 | goto err_put_ctrl; |
| 333 | |
| 334 | dev_info(&ctrl->dev, "SPMI PMIC arbiter debug bus controller added\n"); |
| 335 | |
| 336 | return 0; |
| 337 | |
| 338 | err_put_ctrl: |
| 339 | spmi_controller_put(ctrl); |
| 340 | return rc; |
| 341 | } |
| 342 | |
| 343 | static int spmi_pmic_arb_debug_remove(struct platform_device *pdev) |
| 344 | { |
| 345 | struct spmi_controller *ctrl = platform_get_drvdata(pdev); |
| 346 | |
| 347 | spmi_controller_remove(ctrl); |
| 348 | spmi_controller_put(ctrl); |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | static const struct of_device_id spmi_pmic_arb_debug_match_table[] = { |
| 354 | { .compatible = "qcom,spmi-pmic-arb-debug", }, |
| 355 | {}, |
| 356 | }; |
| 357 | MODULE_DEVICE_TABLE(of, spmi_pmic_arb_debug_match_table); |
| 358 | |
| 359 | static struct platform_driver spmi_pmic_arb_debug_driver = { |
| 360 | .probe = spmi_pmic_arb_debug_probe, |
| 361 | .remove = spmi_pmic_arb_debug_remove, |
| 362 | .driver = { |
| 363 | .name = "spmi_pmic_arb_debug", |
| 364 | .of_match_table = spmi_pmic_arb_debug_match_table, |
| 365 | }, |
| 366 | }; |
| 367 | |
| 368 | int __init spmi_pmic_arb_debug_init(void) |
| 369 | { |
| 370 | return platform_driver_register(&spmi_pmic_arb_debug_driver); |
| 371 | } |
| 372 | arch_initcall(spmi_pmic_arb_debug_init); |
| 373 | |
| 374 | static void __exit spmi_pmic_arb_debug_exit(void) |
| 375 | { |
| 376 | platform_driver_unregister(&spmi_pmic_arb_debug_driver); |
| 377 | } |
| 378 | module_exit(spmi_pmic_arb_debug_exit); |
| 379 | |
| 380 | MODULE_LICENSE("GPL v2"); |
| 381 | MODULE_ALIAS("platform:spmi_pmic_arb_debug"); |