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gerrit-public.fairphone.software / kernel / msm-4.9 / 74ddcdb868a84f4a9f65e33c1ca0d24e1134e53a / . / drivers / dma / ioat / hw.h
blob: d2ff3fda0b18c3b7c8ca1d2fe656ecc53bea0ba3 [file] [log] [blame]
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]1/*
Maciej Sosnowski211a22c2009-02-26 11:05:43 +0100[diff] [blame]2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef _IOAT_HW_H_
22#define _IOAT_HW_H_
23
24/* PCI Configuration Space Values */
Dan Williamse6c0b692009-09-08 17:29:44 -0700[diff] [blame]25#define IOAT_MMIO_BAR 0
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800[diff] [blame]26
27/* CB device ID's */
28#define IOAT_PCI_DID_5000 0x1A38
29#define IOAT_PCI_DID_CNB 0x360B
30#define IOAT_PCI_DID_SCNB 0x65FF
31#define IOAT_PCI_DID_SNB 0x402F
32
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800[diff] [blame]33#define IOAT_VER_1_2 0x12 /* Version 1.2 */
34#define IOAT_VER_2_0 0x20 /* Version 2.0 */
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700[diff] [blame]35#define IOAT_VER_3_0 0x30 /* Version 3.0 */
Dan Williams2aec0482009-09-08 17:42:54 -0700[diff] [blame]36#define IOAT_VER_3_2 0x32 /* Version 3.2 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]37
Dan Williams228c4f52009-11-19 17:07:10 -0700[diff] [blame]38int system_has_dca_enabled(struct pci_dev *pdev);
39
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]40struct ioat_dma_descriptor {
41 uint32_t size;
Dan Williamsc7984f42009-07-28 14:44:04 -0700[diff] [blame]42 union {
43 uint32_t ctl;
44 struct {
45 unsigned int int_en:1;
46 unsigned int src_snoop_dis:1;
47 unsigned int dest_snoop_dis:1;
48 unsigned int compl_write:1;
49 unsigned int fence:1;
50 unsigned int null:1;
51 unsigned int src_brk:1;
52 unsigned int dest_brk:1;
53 unsigned int bundle:1;
54 unsigned int dest_dca:1;
55 unsigned int hint:1;
56 unsigned int rsvd2:13;
Dan Williams2aec0482009-09-08 17:42:54 -0700[diff] [blame]57 #define IOAT_OP_COPY 0x00
Dan Williamsc7984f42009-07-28 14:44:04 -0700[diff] [blame]58 unsigned int op:8;
59 } ctl_f;
60 };
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]61 uint64_t src_addr;
62 uint64_t dst_addr;
63 uint64_t next;
64 uint64_t rsv1;
65 uint64_t rsv2;
Dan Williamsad643f52009-09-08 12:01:38 -0700[diff] [blame]66 /* store some driver data in an unused portion of the descriptor */
67 union {
68 uint64_t user1;
69 uint64_t tx_cnt;
70 };
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]71 uint64_t user2;
72};
Dan Williams2aec0482009-09-08 17:42:54 -0700[diff] [blame]73
74struct ioat_fill_descriptor {
75 uint32_t size;
76 union {
77 uint32_t ctl;
78 struct {
79 unsigned int int_en:1;
80 unsigned int rsvd:1;
81 unsigned int dest_snoop_dis:1;
82 unsigned int compl_write:1;
83 unsigned int fence:1;
84 unsigned int rsvd2:2;
85 unsigned int dest_brk:1;
86 unsigned int bundle:1;
87 unsigned int rsvd4:15;
88 #define IOAT_OP_FILL 0x01
89 unsigned int op:8;
90 } ctl_f;
91 };
92 uint64_t src_data;
93 uint64_t dst_addr;
94 uint64_t next;
95 uint64_t rsv1;
96 uint64_t next_dst_addr;
97 uint64_t user1;
98 uint64_t user2;
99};
100
101struct ioat_xor_descriptor {
102 uint32_t size;
103 union {
104 uint32_t ctl;
105 struct {
106 unsigned int int_en:1;
107 unsigned int src_snoop_dis:1;
108 unsigned int dest_snoop_dis:1;
109 unsigned int compl_write:1;
110 unsigned int fence:1;
111 unsigned int src_cnt:3;
112 unsigned int bundle:1;
113 unsigned int dest_dca:1;
114 unsigned int hint:1;
115 unsigned int rsvd:13;
116 #define IOAT_OP_XOR 0x87
117 #define IOAT_OP_XOR_VAL 0x88
118 unsigned int op:8;
119 } ctl_f;
120 };
121 uint64_t src_addr;
122 uint64_t dst_addr;
123 uint64_t next;
124 uint64_t src_addr2;
125 uint64_t src_addr3;
126 uint64_t src_addr4;
127 uint64_t src_addr5;
128};
129
130struct ioat_xor_ext_descriptor {
131 uint64_t src_addr6;
132 uint64_t src_addr7;
133 uint64_t src_addr8;
134 uint64_t next;
135 uint64_t rsvd[4];
136};
137
138struct ioat_pq_descriptor {
139 uint32_t size;
140 union {
141 uint32_t ctl;
142 struct {
143 unsigned int int_en:1;
144 unsigned int src_snoop_dis:1;
145 unsigned int dest_snoop_dis:1;
146 unsigned int compl_write:1;
147 unsigned int fence:1;
148 unsigned int src_cnt:3;
149 unsigned int bundle:1;
150 unsigned int dest_dca:1;
151 unsigned int hint:1;
152 unsigned int p_disable:1;
153 unsigned int q_disable:1;
154 unsigned int rsvd:11;
155 #define IOAT_OP_PQ 0x89
156 #define IOAT_OP_PQ_VAL 0x8a
157 unsigned int op:8;
158 } ctl_f;
159 };
160 uint64_t src_addr;
161 uint64_t p_addr;
162 uint64_t next;
163 uint64_t src_addr2;
164 uint64_t src_addr3;
165 uint8_t coef[8];
166 uint64_t q_addr;
167};
168
169struct ioat_pq_ext_descriptor {
170 uint64_t src_addr4;
171 uint64_t src_addr5;
172 uint64_t src_addr6;
173 uint64_t next;
174 uint64_t src_addr7;
175 uint64_t src_addr8;
176 uint64_t rsvd[2];
177};
178
179struct ioat_pq_update_descriptor {
180 uint32_t size;
181 union {
182 uint32_t ctl;
183 struct {
184 unsigned int int_en:1;
185 unsigned int src_snoop_dis:1;
186 unsigned int dest_snoop_dis:1;
187 unsigned int compl_write:1;
188 unsigned int fence:1;
189 unsigned int src_cnt:3;
190 unsigned int bundle:1;
191 unsigned int dest_dca:1;
192 unsigned int hint:1;
193 unsigned int p_disable:1;
194 unsigned int q_disable:1;
195 unsigned int rsvd:3;
196 unsigned int coef:8;
197 #define IOAT_OP_PQ_UP 0x8b
198 unsigned int op:8;
199 } ctl_f;
200 };
201 uint64_t src_addr;
202 uint64_t p_addr;
203 uint64_t next;
204 uint64_t src_addr2;
205 uint64_t p_src;
206 uint64_t q_src;
207 uint64_t q_addr;
208};
209
210struct ioat_raw_descriptor {
211 uint64_t field[8];
212};
Chris Leech0bbd5f42006-05-23 17:35:34 -0700[diff] [blame]213#endif