| Vicky Wallace | ce2159e | 2016-12-27 15:58:35 -0800 | [diff] [blame] | 1 | Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding |
| 2 | -------------------------------------------------------------------- |
| 3 | |
| 4 | Required properties : |
| 5 | - compatible : shall contain only one of the following: |
| 6 | "qcom,gpucc-sdm845", |
| Vicky Wallace | 442e295 | 2017-07-12 18:46:26 -0700 | [diff] [blame] | 7 | "qcom,gpucc-sdm845-v2", |
| 8 | "qcom,gfxcc-sdm845", |
| 9 | "qcom,gfxcc-sdm845-v2" |
| Vicky Wallace | ce2159e | 2016-12-27 15:58:35 -0800 | [diff] [blame] | 10 | |
| 11 | - reg : shall contain base register offset and size. |
| 12 | - #clock-cells : shall contain 1. |
| 13 | - #reset-cells : shall contain 1. |
| 14 | - #vdd_<rail>-supply : The logic rail supply. |
| 15 | |
| 16 | Optional properties : |
| 17 | - #power-domain-cells : shall contain 1. |
| 18 | |
| 19 | Example: |
| 20 | clock_gfx: qcom,gfxcc@5090000 { |
| 21 | compatible = "qcom,gfxcc-sdm845"; |
| 22 | reg = <0x5090000 0x9000>; |
| 23 | vdd_gfx-supply = <&pm8005_s1_level>; |
| 24 | vdd_mx-supply = <&pm8998_s6_level>; |
| 25 | #clock-cells = <1>; |
| 26 | #reset-cells = <1>; |
| 27 | }; |
| 28 | |
| 29 | clock_gpucc: qcom,gpucc@5090000 { |
| 30 | compatible = "qcom,gpucc-sdm845"; |
| 31 | reg = <0x5090000 0x9000>; |
| 32 | vdd_cx-supply = <&pm8998_s9_level>; |
| 33 | #clock-cells = <1>; |
| 34 | #reset-cells = <1>; |
| 35 | }; |