Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 1 | /* |
Deepak Katragadda | 9c5c5aa2 | 2017-02-01 14:20:55 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Deepak Katragadda | 9abd794 | 2017-06-13 14:20:09 -0700 | [diff] [blame] | 14 | #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| 15 | |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/clk-provider.h> |
| 25 | #include <linux/regmap.h> |
| 26 | #include <linux/reset-controller.h> |
| 27 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 28 | #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 29 | |
| 30 | #include "common.h" |
| 31 | #include "clk-regmap.h" |
| 32 | #include "clk-pll.h" |
| 33 | #include "clk-rcg.h" |
| 34 | #include "clk-branch.h" |
| 35 | #include "reset.h" |
| 36 | #include "clk-alpha-pll.h" |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 37 | #include "vdd-level-sdm845.h" |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 38 | |
| 39 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| 40 | |
| 41 | static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner); |
| 42 | |
| 43 | enum { |
| 44 | P_BI_TCXO, |
| 45 | P_CORE_BI_PLL_TEST_SE, |
| 46 | P_VIDEO_PLL0_OUT_EVEN, |
| 47 | P_VIDEO_PLL0_OUT_MAIN, |
| 48 | P_VIDEO_PLL0_OUT_ODD, |
| 49 | }; |
| 50 | |
| 51 | static const struct parent_map video_cc_parent_map_0[] = { |
| 52 | { P_BI_TCXO, 0 }, |
| 53 | { P_VIDEO_PLL0_OUT_MAIN, 1 }, |
| 54 | { P_VIDEO_PLL0_OUT_EVEN, 2 }, |
| 55 | { P_VIDEO_PLL0_OUT_ODD, 3 }, |
| 56 | { P_CORE_BI_PLL_TEST_SE, 4 }, |
| 57 | }; |
| 58 | |
| 59 | static const char * const video_cc_parent_names_0[] = { |
| 60 | "bi_tcxo", |
| 61 | "video_pll0", |
| 62 | "video_pll0_out_even", |
| 63 | "video_pll0_out_odd", |
| 64 | "core_bi_pll_test_se", |
| 65 | }; |
| 66 | |
| 67 | static struct pll_vco fabia_vco[] = { |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 68 | { 249600000, 2000000000, 0 }, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 69 | { 125000000, 1000000000, 1 }, |
| 70 | }; |
| 71 | |
| 72 | static const struct pll_config video_pll0_config = { |
Deepak Katragadda | 9c5c5aa2 | 2017-02-01 14:20:55 -0800 | [diff] [blame] | 73 | .l = 0x10, |
| 74 | .frac = 0xaaab, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | static struct clk_alpha_pll video_pll0 = { |
| 78 | .offset = 0x42c, |
| 79 | .vco_table = fabia_vco, |
| 80 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 81 | .type = FABIA_PLL, |
| 82 | .clkr = { |
| 83 | .hw.init = &(struct clk_init_data){ |
| 84 | .name = "video_pll0", |
| 85 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 86 | .num_parents = 1, |
| 87 | .ops = &clk_fabia_pll_ops, |
Deepak Katragadda | d04d2ca | 2017-03-30 11:03:20 -0700 | [diff] [blame] | 88 | VDD_CX_FMAX_MAP4( |
| 89 | MIN, 615000000, |
| 90 | LOW, 1066000000, |
| 91 | LOW_L1, 1600000000, |
| 92 | NOMINAL, 2000000000), |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 93 | }, |
| 94 | }, |
| 95 | }; |
| 96 | |
| 97 | static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { |
Deepak Katragadda | 9c5c5aa2 | 2017-02-01 14:20:55 -0800 | [diff] [blame] | 98 | F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0), |
| 99 | F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), |
| 100 | F(320000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 101 | F(380000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 102 | F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 103 | F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 104 | { } |
| 105 | }; |
| 106 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 107 | static const struct freq_tbl ftbl_video_cc_venus_clk_src_sdm845_v2[] = { |
| 108 | F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0), |
| 109 | F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), |
| 110 | F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 111 | F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 112 | F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 113 | F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
| 114 | { } |
| 115 | }; |
| 116 | |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 117 | static struct clk_rcg2 video_cc_venus_clk_src = { |
| 118 | .cmd_rcgr = 0x7f0, |
| 119 | .mnd_width = 0, |
| 120 | .hid_width = 5, |
| 121 | .parent_map = video_cc_parent_map_0, |
| 122 | .freq_tbl = ftbl_video_cc_venus_clk_src, |
| 123 | .enable_safe_config = true, |
| 124 | .clkr.hw.init = &(struct clk_init_data){ |
| 125 | .name = "video_cc_venus_clk_src", |
| 126 | .parent_names = video_cc_parent_names_0, |
| 127 | .num_parents = 5, |
| 128 | .flags = CLK_SET_RATE_PARENT, |
| 129 | .ops = &clk_rcg2_ops, |
| 130 | VDD_CX_FMAX_MAP6( |
| 131 | MIN, 100000000, |
| 132 | LOWER, 200000000, |
Deepak Katragadda | 9c5c5aa2 | 2017-02-01 14:20:55 -0800 | [diff] [blame] | 133 | LOW, 320000000, |
| 134 | LOW_L1, 380000000, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 135 | NOMINAL, 444000000, |
| 136 | HIGH, 533000000), |
| 137 | }, |
| 138 | }; |
| 139 | |
| 140 | static struct clk_branch video_cc_apb_clk = { |
| 141 | .halt_reg = 0x990, |
| 142 | .halt_check = BRANCH_HALT, |
| 143 | .clkr = { |
| 144 | .enable_reg = 0x990, |
| 145 | .enable_mask = BIT(0), |
| 146 | .hw.init = &(struct clk_init_data){ |
| 147 | .name = "video_cc_apb_clk", |
| 148 | .ops = &clk_branch2_ops, |
| 149 | }, |
| 150 | }, |
| 151 | }; |
| 152 | |
| 153 | static struct clk_branch video_cc_at_clk = { |
| 154 | .halt_reg = 0x9f0, |
| 155 | .halt_check = BRANCH_HALT, |
| 156 | .clkr = { |
| 157 | .enable_reg = 0x9f0, |
| 158 | .enable_mask = BIT(0), |
| 159 | .hw.init = &(struct clk_init_data){ |
| 160 | .name = "video_cc_at_clk", |
| 161 | .ops = &clk_branch2_ops, |
| 162 | }, |
| 163 | }, |
| 164 | }; |
| 165 | |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 166 | static struct clk_branch video_cc_qdss_trig_clk = { |
| 167 | .halt_reg = 0x970, |
| 168 | .halt_check = BRANCH_HALT, |
| 169 | .clkr = { |
| 170 | .enable_reg = 0x970, |
| 171 | .enable_mask = BIT(0), |
| 172 | .hw.init = &(struct clk_init_data){ |
| 173 | .name = "video_cc_qdss_trig_clk", |
| 174 | .ops = &clk_branch2_ops, |
| 175 | }, |
| 176 | }, |
| 177 | }; |
| 178 | |
| 179 | static struct clk_branch video_cc_qdss_tsctr_div8_clk = { |
| 180 | .halt_reg = 0x9d0, |
| 181 | .halt_check = BRANCH_HALT, |
| 182 | .clkr = { |
| 183 | .enable_reg = 0x9d0, |
| 184 | .enable_mask = BIT(0), |
| 185 | .hw.init = &(struct clk_init_data){ |
| 186 | .name = "video_cc_qdss_tsctr_div8_clk", |
| 187 | .ops = &clk_branch2_ops, |
| 188 | }, |
| 189 | }, |
| 190 | }; |
| 191 | |
| 192 | static struct clk_branch video_cc_vcodec0_axi_clk = { |
| 193 | .halt_reg = 0x930, |
| 194 | .halt_check = BRANCH_HALT, |
| 195 | .clkr = { |
| 196 | .enable_reg = 0x930, |
| 197 | .enable_mask = BIT(0), |
| 198 | .hw.init = &(struct clk_init_data){ |
| 199 | .name = "video_cc_vcodec0_axi_clk", |
| 200 | .ops = &clk_branch2_ops, |
| 201 | }, |
| 202 | }, |
| 203 | }; |
| 204 | |
| 205 | static struct clk_branch video_cc_vcodec0_core_clk = { |
| 206 | .halt_reg = 0x890, |
| 207 | .halt_check = BRANCH_VOTED, |
| 208 | .clkr = { |
| 209 | .enable_reg = 0x890, |
| 210 | .enable_mask = BIT(0), |
| 211 | .hw.init = &(struct clk_init_data){ |
| 212 | .name = "video_cc_vcodec0_core_clk", |
| 213 | .parent_names = (const char *[]){ |
| 214 | "video_cc_venus_clk_src", |
| 215 | }, |
| 216 | .num_parents = 1, |
| 217 | .flags = CLK_SET_RATE_PARENT, |
| 218 | .ops = &clk_branch2_ops, |
| 219 | }, |
| 220 | }, |
| 221 | }; |
| 222 | |
| 223 | static struct clk_branch video_cc_vcodec1_axi_clk = { |
| 224 | .halt_reg = 0x950, |
| 225 | .halt_check = BRANCH_HALT, |
| 226 | .clkr = { |
| 227 | .enable_reg = 0x950, |
| 228 | .enable_mask = BIT(0), |
| 229 | .hw.init = &(struct clk_init_data){ |
| 230 | .name = "video_cc_vcodec1_axi_clk", |
| 231 | .ops = &clk_branch2_ops, |
| 232 | }, |
| 233 | }, |
| 234 | }; |
| 235 | |
| 236 | static struct clk_branch video_cc_vcodec1_core_clk = { |
| 237 | .halt_reg = 0x8d0, |
| 238 | .halt_check = BRANCH_VOTED, |
| 239 | .clkr = { |
| 240 | .enable_reg = 0x8d0, |
| 241 | .enable_mask = BIT(0), |
| 242 | .hw.init = &(struct clk_init_data){ |
| 243 | .name = "video_cc_vcodec1_core_clk", |
| 244 | .parent_names = (const char *[]){ |
| 245 | "video_cc_venus_clk_src", |
| 246 | }, |
| 247 | .num_parents = 1, |
| 248 | .flags = CLK_SET_RATE_PARENT, |
| 249 | .ops = &clk_branch2_ops, |
| 250 | }, |
| 251 | }, |
| 252 | }; |
| 253 | |
| 254 | static struct clk_branch video_cc_venus_ahb_clk = { |
| 255 | .halt_reg = 0x9b0, |
| 256 | .halt_check = BRANCH_HALT, |
| 257 | .clkr = { |
| 258 | .enable_reg = 0x9b0, |
| 259 | .enable_mask = BIT(0), |
| 260 | .hw.init = &(struct clk_init_data){ |
| 261 | .name = "video_cc_venus_ahb_clk", |
| 262 | .ops = &clk_branch2_ops, |
| 263 | }, |
| 264 | }, |
| 265 | }; |
| 266 | |
| 267 | static struct clk_branch video_cc_venus_ctl_axi_clk = { |
| 268 | .halt_reg = 0x910, |
| 269 | .halt_check = BRANCH_HALT, |
| 270 | .clkr = { |
| 271 | .enable_reg = 0x910, |
| 272 | .enable_mask = BIT(0), |
| 273 | .hw.init = &(struct clk_init_data){ |
| 274 | .name = "video_cc_venus_ctl_axi_clk", |
| 275 | .ops = &clk_branch2_ops, |
| 276 | }, |
| 277 | }, |
| 278 | }; |
| 279 | |
| 280 | static struct clk_branch video_cc_venus_ctl_core_clk = { |
| 281 | .halt_reg = 0x850, |
| 282 | .halt_check = BRANCH_HALT, |
| 283 | .clkr = { |
| 284 | .enable_reg = 0x850, |
| 285 | .enable_mask = BIT(0), |
| 286 | .hw.init = &(struct clk_init_data){ |
| 287 | .name = "video_cc_venus_ctl_core_clk", |
| 288 | .parent_names = (const char *[]){ |
| 289 | "video_cc_venus_clk_src", |
| 290 | }, |
| 291 | .num_parents = 1, |
| 292 | .flags = CLK_SET_RATE_PARENT, |
| 293 | .ops = &clk_branch2_ops, |
| 294 | }, |
| 295 | }, |
| 296 | }; |
| 297 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 298 | static struct clk_regmap *video_cc_sdm845_clocks[] = { |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 299 | [VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr, |
| 300 | [VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 301 | [VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr, |
| 302 | [VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr, |
| 303 | [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, |
| 304 | [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, |
| 305 | [VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr, |
| 306 | [VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr, |
| 307 | [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, |
| 308 | [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, |
| 309 | [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, |
| 310 | [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, |
| 311 | [VIDEO_PLL0] = &video_pll0.clkr, |
| 312 | }; |
| 313 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 314 | static const struct regmap_config video_cc_sdm845_regmap_config = { |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 315 | .reg_bits = 32, |
| 316 | .reg_stride = 4, |
| 317 | .val_bits = 32, |
| 318 | .max_register = 0xb90, |
| 319 | .fast_io = true, |
| 320 | }; |
| 321 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 322 | static const struct qcom_cc_desc video_cc_sdm845_desc = { |
| 323 | .config = &video_cc_sdm845_regmap_config, |
| 324 | .clks = video_cc_sdm845_clocks, |
| 325 | .num_clks = ARRAY_SIZE(video_cc_sdm845_clocks), |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 326 | }; |
| 327 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 328 | static const struct of_device_id video_cc_sdm845_match_table[] = { |
| 329 | { .compatible = "qcom,video_cc-sdm845" }, |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 330 | { .compatible = "qcom,video_cc-sdm845-v2" }, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 331 | { } |
| 332 | }; |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 333 | MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 334 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 335 | static void video_cc_sdm845_fixup_sdm845v2(void) |
| 336 | { |
| 337 | video_cc_venus_clk_src.freq_tbl = ftbl_video_cc_venus_clk_src_sdm845_v2; |
| 338 | video_cc_venus_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW] = 330000000; |
| 339 | video_cc_venus_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW_L1] = |
| 340 | 404000000; |
| 341 | } |
| 342 | |
| 343 | static int video_cc_sdm845_fixup(struct platform_device *pdev) |
| 344 | { |
| 345 | const char *compat = NULL; |
| 346 | int compatlen = 0; |
| 347 | |
| 348 | compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen); |
| 349 | if (!compat || (compatlen <= 0)) |
| 350 | return -EINVAL; |
| 351 | |
| 352 | if (!strcmp(compat, "qcom,video_cc-sdm845-v2")) |
| 353 | video_cc_sdm845_fixup_sdm845v2(); |
| 354 | |
| 355 | return 0; |
| 356 | } |
| 357 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 358 | static int video_cc_sdm845_probe(struct platform_device *pdev) |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 359 | { |
| 360 | struct regmap *regmap; |
| 361 | int ret = 0; |
| 362 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 363 | regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 364 | if (IS_ERR(regmap)) { |
| 365 | pr_err("Failed to map the Video CC registers\n"); |
| 366 | return PTR_ERR(regmap); |
| 367 | } |
| 368 | |
| 369 | vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); |
| 370 | if (IS_ERR(vdd_cx.regulator[0])) { |
| 371 | if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) |
| 372 | dev_err(&pdev->dev, |
| 373 | "Unable to get vdd_cx regulator\n"); |
| 374 | return PTR_ERR(vdd_cx.regulator[0]); |
| 375 | } |
| 376 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 377 | ret = video_cc_sdm845_fixup(pdev); |
| 378 | if (ret) |
| 379 | return ret; |
| 380 | |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 381 | clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); |
| 382 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 383 | ret = qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 384 | if (ret) { |
| 385 | dev_err(&pdev->dev, "Failed to register Video CC clocks\n"); |
| 386 | return ret; |
| 387 | } |
| 388 | |
| 389 | dev_info(&pdev->dev, "Registered Video CC clocks\n"); |
| 390 | return ret; |
| 391 | } |
| 392 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 393 | static struct platform_driver video_cc_sdm845_driver = { |
| 394 | .probe = video_cc_sdm845_probe, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 395 | .driver = { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 396 | .name = "video_cc-sdm845", |
| 397 | .of_match_table = video_cc_sdm845_match_table, |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 398 | }, |
| 399 | }; |
| 400 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 401 | static int __init video_cc_sdm845_init(void) |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 402 | { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 403 | return platform_driver_register(&video_cc_sdm845_driver); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 404 | } |
Deepak Katragadda | ef44e10 | 2017-06-21 10:30:46 -0700 | [diff] [blame] | 405 | subsys_initcall(video_cc_sdm845_init); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 406 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 407 | static void __exit video_cc_sdm845_exit(void) |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 408 | { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 409 | platform_driver_unregister(&video_cc_sdm845_driver); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 410 | } |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 411 | module_exit(video_cc_sdm845_exit); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 412 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 413 | MODULE_DESCRIPTION("QCOM VIDEO_CC SDM845 Driver"); |
Deepak Katragadda | 136dd25 | 2016-11-09 17:45:15 -0800 | [diff] [blame] | 414 | MODULE_LICENSE("GPL v2"); |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 415 | MODULE_ALIAS("platform:video_cc-sdm845"); |