Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel I/OAT DMA Linux driver |
| 3 | * Copyright(c) 2004 - 2015 Intel Corporation. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * The full GNU General Public License is included in this distribution in |
| 15 | * the file called "COPYING". |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/dmaengine.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/workqueue.h> |
| 28 | #include <linux/prefetch.h> |
| 29 | #include <linux/dca.h> |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 30 | #include <linux/aer.h> |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 31 | #include <linux/sizes.h> |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 32 | #include "dma.h" |
| 33 | #include "registers.h" |
| 34 | #include "hw.h" |
| 35 | |
| 36 | #include "../dmaengine.h" |
| 37 | |
| 38 | MODULE_VERSION(IOAT_DMA_VERSION); |
| 39 | MODULE_LICENSE("Dual BSD/GPL"); |
| 40 | MODULE_AUTHOR("Intel Corporation"); |
| 41 | |
| 42 | static struct pci_device_id ioat_pci_tbl[] = { |
| 43 | /* I/OAT v3 platforms */ |
| 44 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, |
| 45 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, |
| 46 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, |
| 47 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, |
| 48 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, |
| 49 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, |
| 50 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, |
| 51 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, |
| 52 | |
| 53 | /* I/OAT v3.2 platforms */ |
| 54 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, |
| 55 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, |
| 56 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, |
| 57 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, |
| 58 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, |
| 59 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, |
| 60 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, |
| 61 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, |
| 62 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, |
| 63 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, |
| 64 | |
| 65 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) }, |
| 66 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) }, |
| 67 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) }, |
| 68 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) }, |
| 69 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) }, |
| 70 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) }, |
| 71 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) }, |
| 72 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) }, |
| 73 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) }, |
| 74 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) }, |
| 75 | |
| 76 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) }, |
| 77 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) }, |
| 78 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) }, |
| 79 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) }, |
| 80 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) }, |
| 81 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) }, |
| 82 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) }, |
| 83 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) }, |
| 84 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) }, |
| 85 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) }, |
| 86 | |
| 87 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) }, |
| 88 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) }, |
| 89 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) }, |
| 90 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) }, |
| 91 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) }, |
| 92 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) }, |
| 93 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) }, |
| 94 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) }, |
| 95 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) }, |
| 96 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) }, |
| 97 | |
Dave Jiang | ab98193 | 2015-08-26 14:16:27 -0700 | [diff] [blame] | 98 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) }, |
| 99 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) }, |
| 100 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) }, |
| 101 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) }, |
| 102 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) }, |
| 103 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) }, |
| 104 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) }, |
| 105 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) }, |
| 106 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) }, |
| 107 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) }, |
| 108 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 109 | /* I/OAT v3.3 platforms */ |
| 110 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) }, |
| 111 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) }, |
| 112 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) }, |
| 113 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) }, |
| 114 | |
| 115 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) }, |
| 116 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) }, |
| 117 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) }, |
| 118 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) }, |
| 119 | |
| 120 | { 0, } |
| 121 | }; |
| 122 | MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); |
| 123 | |
| 124 | static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); |
| 125 | static void ioat_remove(struct pci_dev *pdev); |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 126 | static void |
| 127 | ioat_init_channel(struct ioatdma_device *ioat_dma, |
| 128 | struct ioatdma_chan *ioat_chan, int idx); |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 129 | static void ioat_intr_quirk(struct ioatdma_device *ioat_dma); |
| 130 | static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma); |
| 131 | static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 132 | |
| 133 | static int ioat_dca_enabled = 1; |
| 134 | module_param(ioat_dca_enabled, int, 0644); |
| 135 | MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); |
| 136 | int ioat_pending_level = 4; |
| 137 | module_param(ioat_pending_level, int, 0644); |
| 138 | MODULE_PARM_DESC(ioat_pending_level, |
| 139 | "high-water mark for pushing ioat descriptors (default: 4)"); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 140 | static char ioat_interrupt_style[32] = "msix"; |
| 141 | module_param_string(ioat_interrupt_style, ioat_interrupt_style, |
| 142 | sizeof(ioat_interrupt_style), 0644); |
| 143 | MODULE_PARM_DESC(ioat_interrupt_style, |
| 144 | "set ioat interrupt style: msix (default), msi, intx"); |
| 145 | |
| 146 | struct kmem_cache *ioat_cache; |
| 147 | struct kmem_cache *ioat_sed_cache; |
| 148 | |
| 149 | static bool is_jf_ioat(struct pci_dev *pdev) |
| 150 | { |
| 151 | switch (pdev->device) { |
| 152 | case PCI_DEVICE_ID_INTEL_IOAT_JSF0: |
| 153 | case PCI_DEVICE_ID_INTEL_IOAT_JSF1: |
| 154 | case PCI_DEVICE_ID_INTEL_IOAT_JSF2: |
| 155 | case PCI_DEVICE_ID_INTEL_IOAT_JSF3: |
| 156 | case PCI_DEVICE_ID_INTEL_IOAT_JSF4: |
| 157 | case PCI_DEVICE_ID_INTEL_IOAT_JSF5: |
| 158 | case PCI_DEVICE_ID_INTEL_IOAT_JSF6: |
| 159 | case PCI_DEVICE_ID_INTEL_IOAT_JSF7: |
| 160 | case PCI_DEVICE_ID_INTEL_IOAT_JSF8: |
| 161 | case PCI_DEVICE_ID_INTEL_IOAT_JSF9: |
| 162 | return true; |
| 163 | default: |
| 164 | return false; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | static bool is_snb_ioat(struct pci_dev *pdev) |
| 169 | { |
| 170 | switch (pdev->device) { |
| 171 | case PCI_DEVICE_ID_INTEL_IOAT_SNB0: |
| 172 | case PCI_DEVICE_ID_INTEL_IOAT_SNB1: |
| 173 | case PCI_DEVICE_ID_INTEL_IOAT_SNB2: |
| 174 | case PCI_DEVICE_ID_INTEL_IOAT_SNB3: |
| 175 | case PCI_DEVICE_ID_INTEL_IOAT_SNB4: |
| 176 | case PCI_DEVICE_ID_INTEL_IOAT_SNB5: |
| 177 | case PCI_DEVICE_ID_INTEL_IOAT_SNB6: |
| 178 | case PCI_DEVICE_ID_INTEL_IOAT_SNB7: |
| 179 | case PCI_DEVICE_ID_INTEL_IOAT_SNB8: |
| 180 | case PCI_DEVICE_ID_INTEL_IOAT_SNB9: |
| 181 | return true; |
| 182 | default: |
| 183 | return false; |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | static bool is_ivb_ioat(struct pci_dev *pdev) |
| 188 | { |
| 189 | switch (pdev->device) { |
| 190 | case PCI_DEVICE_ID_INTEL_IOAT_IVB0: |
| 191 | case PCI_DEVICE_ID_INTEL_IOAT_IVB1: |
| 192 | case PCI_DEVICE_ID_INTEL_IOAT_IVB2: |
| 193 | case PCI_DEVICE_ID_INTEL_IOAT_IVB3: |
| 194 | case PCI_DEVICE_ID_INTEL_IOAT_IVB4: |
| 195 | case PCI_DEVICE_ID_INTEL_IOAT_IVB5: |
| 196 | case PCI_DEVICE_ID_INTEL_IOAT_IVB6: |
| 197 | case PCI_DEVICE_ID_INTEL_IOAT_IVB7: |
| 198 | case PCI_DEVICE_ID_INTEL_IOAT_IVB8: |
| 199 | case PCI_DEVICE_ID_INTEL_IOAT_IVB9: |
| 200 | return true; |
| 201 | default: |
| 202 | return false; |
| 203 | } |
| 204 | |
| 205 | } |
| 206 | |
| 207 | static bool is_hsw_ioat(struct pci_dev *pdev) |
| 208 | { |
| 209 | switch (pdev->device) { |
| 210 | case PCI_DEVICE_ID_INTEL_IOAT_HSW0: |
| 211 | case PCI_DEVICE_ID_INTEL_IOAT_HSW1: |
| 212 | case PCI_DEVICE_ID_INTEL_IOAT_HSW2: |
| 213 | case PCI_DEVICE_ID_INTEL_IOAT_HSW3: |
| 214 | case PCI_DEVICE_ID_INTEL_IOAT_HSW4: |
| 215 | case PCI_DEVICE_ID_INTEL_IOAT_HSW5: |
| 216 | case PCI_DEVICE_ID_INTEL_IOAT_HSW6: |
| 217 | case PCI_DEVICE_ID_INTEL_IOAT_HSW7: |
| 218 | case PCI_DEVICE_ID_INTEL_IOAT_HSW8: |
| 219 | case PCI_DEVICE_ID_INTEL_IOAT_HSW9: |
| 220 | return true; |
| 221 | default: |
| 222 | return false; |
| 223 | } |
| 224 | |
| 225 | } |
| 226 | |
Dave Jiang | ab98193 | 2015-08-26 14:16:27 -0700 | [diff] [blame] | 227 | static bool is_bdx_ioat(struct pci_dev *pdev) |
| 228 | { |
| 229 | switch (pdev->device) { |
| 230 | case PCI_DEVICE_ID_INTEL_IOAT_BDX0: |
| 231 | case PCI_DEVICE_ID_INTEL_IOAT_BDX1: |
| 232 | case PCI_DEVICE_ID_INTEL_IOAT_BDX2: |
| 233 | case PCI_DEVICE_ID_INTEL_IOAT_BDX3: |
| 234 | case PCI_DEVICE_ID_INTEL_IOAT_BDX4: |
| 235 | case PCI_DEVICE_ID_INTEL_IOAT_BDX5: |
| 236 | case PCI_DEVICE_ID_INTEL_IOAT_BDX6: |
| 237 | case PCI_DEVICE_ID_INTEL_IOAT_BDX7: |
| 238 | case PCI_DEVICE_ID_INTEL_IOAT_BDX8: |
| 239 | case PCI_DEVICE_ID_INTEL_IOAT_BDX9: |
| 240 | return true; |
| 241 | default: |
| 242 | return false; |
| 243 | } |
| 244 | } |
| 245 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 246 | static bool is_xeon_cb32(struct pci_dev *pdev) |
| 247 | { |
| 248 | return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) || |
Dave Jiang | ab98193 | 2015-08-26 14:16:27 -0700 | [diff] [blame] | 249 | is_hsw_ioat(pdev) || is_bdx_ioat(pdev); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | bool is_bwd_ioat(struct pci_dev *pdev) |
| 253 | { |
| 254 | switch (pdev->device) { |
| 255 | case PCI_DEVICE_ID_INTEL_IOAT_BWD0: |
| 256 | case PCI_DEVICE_ID_INTEL_IOAT_BWD1: |
| 257 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: |
| 258 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: |
| 259 | /* even though not Atom, BDX-DE has same DMA silicon */ |
| 260 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: |
| 261 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: |
| 262 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: |
| 263 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: |
| 264 | return true; |
| 265 | default: |
| 266 | return false; |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | static bool is_bwd_noraid(struct pci_dev *pdev) |
| 271 | { |
| 272 | switch (pdev->device) { |
| 273 | case PCI_DEVICE_ID_INTEL_IOAT_BWD2: |
| 274 | case PCI_DEVICE_ID_INTEL_IOAT_BWD3: |
| 275 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0: |
| 276 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1: |
| 277 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2: |
| 278 | case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3: |
| 279 | return true; |
| 280 | default: |
| 281 | return false; |
| 282 | } |
| 283 | |
| 284 | } |
| 285 | |
| 286 | /* |
| 287 | * Perform a IOAT transaction to verify the HW works. |
| 288 | */ |
| 289 | #define IOAT_TEST_SIZE 2000 |
| 290 | |
| 291 | static void ioat_dma_test_callback(void *dma_async_param) |
| 292 | { |
| 293 | struct completion *cmp = dma_async_param; |
| 294 | |
| 295 | complete(cmp); |
| 296 | } |
| 297 | |
| 298 | /** |
| 299 | * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. |
| 300 | * @ioat_dma: dma device to be tested |
| 301 | */ |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 302 | static int ioat_dma_self_test(struct ioatdma_device *ioat_dma) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 303 | { |
| 304 | int i; |
| 305 | u8 *src; |
| 306 | u8 *dest; |
| 307 | struct dma_device *dma = &ioat_dma->dma_dev; |
| 308 | struct device *dev = &ioat_dma->pdev->dev; |
| 309 | struct dma_chan *dma_chan; |
| 310 | struct dma_async_tx_descriptor *tx; |
| 311 | dma_addr_t dma_dest, dma_src; |
| 312 | dma_cookie_t cookie; |
| 313 | int err = 0; |
| 314 | struct completion cmp; |
| 315 | unsigned long tmo; |
| 316 | unsigned long flags; |
| 317 | |
| 318 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
| 319 | if (!src) |
| 320 | return -ENOMEM; |
| 321 | dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
| 322 | if (!dest) { |
| 323 | kfree(src); |
| 324 | return -ENOMEM; |
| 325 | } |
| 326 | |
| 327 | /* Fill in src buffer */ |
| 328 | for (i = 0; i < IOAT_TEST_SIZE; i++) |
| 329 | src[i] = (u8)i; |
| 330 | |
| 331 | /* Start copy, using first DMA channel */ |
| 332 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
| 333 | device_node); |
| 334 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
| 335 | dev_err(dev, "selftest cannot allocate chan resource\n"); |
| 336 | err = -ENODEV; |
| 337 | goto out; |
| 338 | } |
| 339 | |
| 340 | dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
| 341 | if (dma_mapping_error(dev, dma_src)) { |
| 342 | dev_err(dev, "mapping src buffer failed\n"); |
| 343 | goto free_resources; |
| 344 | } |
| 345 | dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); |
| 346 | if (dma_mapping_error(dev, dma_dest)) { |
| 347 | dev_err(dev, "mapping dest buffer failed\n"); |
| 348 | goto unmap_src; |
| 349 | } |
| 350 | flags = DMA_PREP_INTERRUPT; |
| 351 | tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest, |
| 352 | dma_src, IOAT_TEST_SIZE, |
| 353 | flags); |
| 354 | if (!tx) { |
| 355 | dev_err(dev, "Self-test prep failed, disabling\n"); |
| 356 | err = -ENODEV; |
| 357 | goto unmap_dma; |
| 358 | } |
| 359 | |
| 360 | async_tx_ack(tx); |
| 361 | init_completion(&cmp); |
| 362 | tx->callback = ioat_dma_test_callback; |
| 363 | tx->callback_param = &cmp; |
| 364 | cookie = tx->tx_submit(tx); |
| 365 | if (cookie < 0) { |
| 366 | dev_err(dev, "Self-test setup failed, disabling\n"); |
| 367 | err = -ENODEV; |
| 368 | goto unmap_dma; |
| 369 | } |
| 370 | dma->device_issue_pending(dma_chan); |
| 371 | |
| 372 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 373 | |
| 374 | if (tmo == 0 || |
| 375 | dma->device_tx_status(dma_chan, cookie, NULL) |
| 376 | != DMA_COMPLETE) { |
| 377 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
| 378 | err = -ENODEV; |
| 379 | goto unmap_dma; |
| 380 | } |
| 381 | if (memcmp(src, dest, IOAT_TEST_SIZE)) { |
| 382 | dev_err(dev, "Self-test copy failed compare, disabling\n"); |
| 383 | err = -ENODEV; |
| 384 | goto free_resources; |
| 385 | } |
| 386 | |
| 387 | unmap_dma: |
| 388 | dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); |
| 389 | unmap_src: |
| 390 | dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
| 391 | free_resources: |
| 392 | dma->device_free_chan_resources(dma_chan); |
| 393 | out: |
| 394 | kfree(src); |
| 395 | kfree(dest); |
| 396 | return err; |
| 397 | } |
| 398 | |
| 399 | /** |
| 400 | * ioat_dma_setup_interrupts - setup interrupt handler |
| 401 | * @ioat_dma: ioat dma device |
| 402 | */ |
| 403 | int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma) |
| 404 | { |
| 405 | struct ioatdma_chan *ioat_chan; |
| 406 | struct pci_dev *pdev = ioat_dma->pdev; |
| 407 | struct device *dev = &pdev->dev; |
| 408 | struct msix_entry *msix; |
| 409 | int i, j, msixcnt; |
| 410 | int err = -EINVAL; |
| 411 | u8 intrctrl = 0; |
| 412 | |
| 413 | if (!strcmp(ioat_interrupt_style, "msix")) |
| 414 | goto msix; |
| 415 | if (!strcmp(ioat_interrupt_style, "msi")) |
| 416 | goto msi; |
| 417 | if (!strcmp(ioat_interrupt_style, "intx")) |
| 418 | goto intx; |
| 419 | dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); |
| 420 | goto err_no_irq; |
| 421 | |
| 422 | msix: |
| 423 | /* The number of MSI-X vectors should equal the number of channels */ |
| 424 | msixcnt = ioat_dma->dma_dev.chancnt; |
| 425 | for (i = 0; i < msixcnt; i++) |
| 426 | ioat_dma->msix_entries[i].entry = i; |
| 427 | |
| 428 | err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt); |
| 429 | if (err) |
| 430 | goto msi; |
| 431 | |
| 432 | for (i = 0; i < msixcnt; i++) { |
| 433 | msix = &ioat_dma->msix_entries[i]; |
| 434 | ioat_chan = ioat_chan_by_index(ioat_dma, i); |
| 435 | err = devm_request_irq(dev, msix->vector, |
| 436 | ioat_dma_do_interrupt_msix, 0, |
| 437 | "ioat-msix", ioat_chan); |
| 438 | if (err) { |
| 439 | for (j = 0; j < i; j++) { |
| 440 | msix = &ioat_dma->msix_entries[j]; |
| 441 | ioat_chan = ioat_chan_by_index(ioat_dma, j); |
| 442 | devm_free_irq(dev, msix->vector, ioat_chan); |
| 443 | } |
| 444 | goto msi; |
| 445 | } |
| 446 | } |
| 447 | intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; |
| 448 | ioat_dma->irq_mode = IOAT_MSIX; |
| 449 | goto done; |
| 450 | |
| 451 | msi: |
| 452 | err = pci_enable_msi(pdev); |
| 453 | if (err) |
| 454 | goto intx; |
| 455 | |
| 456 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, |
| 457 | "ioat-msi", ioat_dma); |
| 458 | if (err) { |
| 459 | pci_disable_msi(pdev); |
| 460 | goto intx; |
| 461 | } |
| 462 | ioat_dma->irq_mode = IOAT_MSI; |
| 463 | goto done; |
| 464 | |
| 465 | intx: |
| 466 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, |
| 467 | IRQF_SHARED, "ioat-intx", ioat_dma); |
| 468 | if (err) |
| 469 | goto err_no_irq; |
| 470 | |
| 471 | ioat_dma->irq_mode = IOAT_INTX; |
| 472 | done: |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 473 | if (is_bwd_ioat(pdev)) |
| 474 | ioat_intr_quirk(ioat_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 475 | intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; |
| 476 | writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); |
| 477 | return 0; |
| 478 | |
| 479 | err_no_irq: |
| 480 | /* Disable all interrupt generation */ |
| 481 | writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); |
| 482 | ioat_dma->irq_mode = IOAT_NOIRQ; |
| 483 | dev_err(dev, "no usable interrupts\n"); |
| 484 | return err; |
| 485 | } |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 486 | |
| 487 | static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma) |
| 488 | { |
| 489 | /* Disable all interrupt generation */ |
| 490 | writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); |
| 491 | } |
| 492 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 493 | static int ioat_probe(struct ioatdma_device *ioat_dma) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 494 | { |
| 495 | int err = -ENODEV; |
| 496 | struct dma_device *dma = &ioat_dma->dma_dev; |
| 497 | struct pci_dev *pdev = ioat_dma->pdev; |
| 498 | struct device *dev = &pdev->dev; |
| 499 | |
Dave Jiang | 679cfbf | 2016-02-10 15:00:21 -0700 | [diff] [blame] | 500 | ioat_dma->completion_pool = dma_pool_create("completion_pool", dev, |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 501 | sizeof(u64), |
| 502 | SMP_CACHE_BYTES, |
| 503 | SMP_CACHE_BYTES); |
| 504 | |
| 505 | if (!ioat_dma->completion_pool) { |
| 506 | err = -ENOMEM; |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 507 | goto err_out; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 508 | } |
| 509 | |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 510 | ioat_enumerate_channels(ioat_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 511 | |
| 512 | dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
| 513 | dma->dev = &pdev->dev; |
| 514 | |
| 515 | if (!dma->chancnt) { |
| 516 | dev_err(dev, "channel enumeration error\n"); |
| 517 | goto err_setup_interrupts; |
| 518 | } |
| 519 | |
| 520 | err = ioat_dma_setup_interrupts(ioat_dma); |
| 521 | if (err) |
| 522 | goto err_setup_interrupts; |
| 523 | |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 524 | err = ioat3_dma_self_test(ioat_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 525 | if (err) |
| 526 | goto err_self_test; |
| 527 | |
| 528 | return 0; |
| 529 | |
| 530 | err_self_test: |
| 531 | ioat_disable_interrupts(ioat_dma); |
| 532 | err_setup_interrupts: |
Dave Jiang | 679cfbf | 2016-02-10 15:00:21 -0700 | [diff] [blame] | 533 | dma_pool_destroy(ioat_dma->completion_pool); |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 534 | err_out: |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 535 | return err; |
| 536 | } |
| 537 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 538 | static int ioat_register(struct ioatdma_device *ioat_dma) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 539 | { |
| 540 | int err = dma_async_device_register(&ioat_dma->dma_dev); |
| 541 | |
| 542 | if (err) { |
| 543 | ioat_disable_interrupts(ioat_dma); |
Dave Jiang | 679cfbf | 2016-02-10 15:00:21 -0700 | [diff] [blame] | 544 | dma_pool_destroy(ioat_dma->completion_pool); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | return err; |
| 548 | } |
| 549 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 550 | static void ioat_dma_remove(struct ioatdma_device *ioat_dma) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 551 | { |
| 552 | struct dma_device *dma = &ioat_dma->dma_dev; |
| 553 | |
| 554 | ioat_disable_interrupts(ioat_dma); |
| 555 | |
| 556 | ioat_kobject_del(ioat_dma); |
| 557 | |
| 558 | dma_async_device_unregister(dma); |
| 559 | |
Dave Jiang | 679cfbf | 2016-02-10 15:00:21 -0700 | [diff] [blame] | 560 | dma_pool_destroy(ioat_dma->completion_pool); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 561 | |
| 562 | INIT_LIST_HEAD(&dma->channels); |
| 563 | } |
| 564 | |
| 565 | /** |
| 566 | * ioat_enumerate_channels - find and initialize the device's channels |
| 567 | * @ioat_dma: the ioat dma device to be enumerated |
| 568 | */ |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 569 | static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 570 | { |
| 571 | struct ioatdma_chan *ioat_chan; |
| 572 | struct device *dev = &ioat_dma->pdev->dev; |
| 573 | struct dma_device *dma = &ioat_dma->dma_dev; |
| 574 | u8 xfercap_log; |
| 575 | int i; |
| 576 | |
| 577 | INIT_LIST_HEAD(&dma->channels); |
| 578 | dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); |
| 579 | dma->chancnt &= 0x1f; /* bits [4:0] valid */ |
| 580 | if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) { |
| 581 | dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", |
| 582 | dma->chancnt, ARRAY_SIZE(ioat_dma->idx)); |
| 583 | dma->chancnt = ARRAY_SIZE(ioat_dma->idx); |
| 584 | } |
| 585 | xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); |
| 586 | xfercap_log &= 0x1f; /* bits [4:0] valid */ |
| 587 | if (xfercap_log == 0) |
| 588 | return 0; |
| 589 | dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); |
| 590 | |
| 591 | for (i = 0; i < dma->chancnt; i++) { |
| 592 | ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); |
| 593 | if (!ioat_chan) |
| 594 | break; |
| 595 | |
| 596 | ioat_init_channel(ioat_dma, ioat_chan, i); |
| 597 | ioat_chan->xfercap_log = xfercap_log; |
| 598 | spin_lock_init(&ioat_chan->prep_lock); |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 599 | if (ioat_reset_hw(ioat_chan)) { |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 600 | i = 0; |
| 601 | break; |
| 602 | } |
| 603 | } |
| 604 | dma->chancnt = i; |
| 605 | return i; |
| 606 | } |
| 607 | |
| 608 | /** |
| 609 | * ioat_free_chan_resources - release all the descriptors |
| 610 | * @chan: the channel to be cleaned |
| 611 | */ |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 612 | static void ioat_free_chan_resources(struct dma_chan *c) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 613 | { |
| 614 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
| 615 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
| 616 | struct ioat_ring_ent *desc; |
| 617 | const int total_descs = 1 << ioat_chan->alloc_order; |
| 618 | int descs; |
| 619 | int i; |
| 620 | |
| 621 | /* Before freeing channel resources first check |
| 622 | * if they have been previously allocated for this channel. |
| 623 | */ |
| 624 | if (!ioat_chan->ring) |
| 625 | return; |
| 626 | |
| 627 | ioat_stop(ioat_chan); |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 628 | ioat_reset_hw(ioat_chan); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 629 | |
| 630 | spin_lock_bh(&ioat_chan->cleanup_lock); |
| 631 | spin_lock_bh(&ioat_chan->prep_lock); |
| 632 | descs = ioat_ring_space(ioat_chan); |
| 633 | dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs); |
| 634 | for (i = 0; i < descs; i++) { |
| 635 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i); |
| 636 | ioat_free_ring_ent(desc, c); |
| 637 | } |
| 638 | |
| 639 | if (descs < total_descs) |
| 640 | dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", |
| 641 | total_descs - descs); |
| 642 | |
| 643 | for (i = 0; i < total_descs - descs; i++) { |
| 644 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i); |
| 645 | dump_desc_dbg(ioat_chan, desc); |
| 646 | ioat_free_ring_ent(desc, c); |
| 647 | } |
| 648 | |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 649 | for (i = 0; i < ioat_chan->desc_chunks; i++) { |
| 650 | dma_free_coherent(to_dev(ioat_chan), SZ_2M, |
| 651 | ioat_chan->descs[i].virt, |
| 652 | ioat_chan->descs[i].hw); |
| 653 | ioat_chan->descs[i].virt = NULL; |
| 654 | ioat_chan->descs[i].hw = 0; |
| 655 | } |
| 656 | ioat_chan->desc_chunks = 0; |
| 657 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 658 | kfree(ioat_chan->ring); |
| 659 | ioat_chan->ring = NULL; |
| 660 | ioat_chan->alloc_order = 0; |
Dave Jiang | 679cfbf | 2016-02-10 15:00:21 -0700 | [diff] [blame] | 661 | dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion, |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 662 | ioat_chan->completion_dma); |
| 663 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 664 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 665 | |
| 666 | ioat_chan->last_completion = 0; |
| 667 | ioat_chan->completion_dma = 0; |
| 668 | ioat_chan->dmacount = 0; |
| 669 | } |
| 670 | |
| 671 | /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring |
| 672 | * @chan: channel to be initialized |
| 673 | */ |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 674 | static int ioat_alloc_chan_resources(struct dma_chan *c) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 675 | { |
| 676 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
| 677 | struct ioat_ring_ent **ring; |
| 678 | u64 status; |
| 679 | int order; |
| 680 | int i = 0; |
| 681 | u32 chanerr; |
| 682 | |
| 683 | /* have we already been set up? */ |
| 684 | if (ioat_chan->ring) |
| 685 | return 1 << ioat_chan->alloc_order; |
| 686 | |
| 687 | /* Setup register to interrupt and write completion status on error */ |
| 688 | writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); |
| 689 | |
| 690 | /* allocate a completion writeback area */ |
| 691 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ |
| 692 | ioat_chan->completion = |
Julia Lawall | 305697f | 2016-04-29 22:09:10 +0200 | [diff] [blame] | 693 | dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool, |
Krister Johansen | 2382c14 | 2017-01-04 01:22:52 -0800 | [diff] [blame] | 694 | GFP_NOWAIT, &ioat_chan->completion_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 695 | if (!ioat_chan->completion) |
| 696 | return -ENOMEM; |
| 697 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 698 | writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF, |
| 699 | ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
| 700 | writel(((u64)ioat_chan->completion_dma) >> 32, |
| 701 | ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
| 702 | |
Dave Jiang | cd60cd9 | 2016-02-10 15:00:26 -0700 | [diff] [blame] | 703 | order = IOAT_MAX_ORDER; |
Krister Johansen | 2382c14 | 2017-01-04 01:22:52 -0800 | [diff] [blame] | 704 | ring = ioat_alloc_ring(c, order, GFP_NOWAIT); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 705 | if (!ring) |
| 706 | return -ENOMEM; |
| 707 | |
| 708 | spin_lock_bh(&ioat_chan->cleanup_lock); |
| 709 | spin_lock_bh(&ioat_chan->prep_lock); |
| 710 | ioat_chan->ring = ring; |
| 711 | ioat_chan->head = 0; |
| 712 | ioat_chan->issued = 0; |
| 713 | ioat_chan->tail = 0; |
| 714 | ioat_chan->alloc_order = order; |
| 715 | set_bit(IOAT_RUN, &ioat_chan->state); |
| 716 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 717 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 718 | |
| 719 | ioat_start_null_desc(ioat_chan); |
| 720 | |
| 721 | /* check that we got off the ground */ |
| 722 | do { |
| 723 | udelay(1); |
| 724 | status = ioat_chansts(ioat_chan); |
| 725 | } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status)); |
| 726 | |
| 727 | if (is_ioat_active(status) || is_ioat_idle(status)) |
| 728 | return 1 << ioat_chan->alloc_order; |
| 729 | |
| 730 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 731 | |
| 732 | dev_WARN(to_dev(ioat_chan), |
| 733 | "failed to start channel chanerr: %#x\n", chanerr); |
| 734 | ioat_free_chan_resources(c); |
| 735 | return -EFAULT; |
| 736 | } |
| 737 | |
| 738 | /* common channel initialization */ |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 739 | static void |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 740 | ioat_init_channel(struct ioatdma_device *ioat_dma, |
| 741 | struct ioatdma_chan *ioat_chan, int idx) |
| 742 | { |
| 743 | struct dma_device *dma = &ioat_dma->dma_dev; |
| 744 | struct dma_chan *c = &ioat_chan->dma_chan; |
| 745 | unsigned long data = (unsigned long) c; |
| 746 | |
| 747 | ioat_chan->ioat_dma = ioat_dma; |
| 748 | ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); |
| 749 | spin_lock_init(&ioat_chan->cleanup_lock); |
| 750 | ioat_chan->dma_chan.device = dma; |
| 751 | dma_cookie_init(&ioat_chan->dma_chan); |
| 752 | list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels); |
| 753 | ioat_dma->idx[idx] = ioat_chan; |
| 754 | init_timer(&ioat_chan->timer); |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 755 | ioat_chan->timer.function = ioat_timer_event; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 756 | ioat_chan->timer.data = data; |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 757 | tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 758 | } |
| 759 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 760 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ |
| 761 | static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma) |
| 762 | { |
| 763 | int i, src_idx; |
| 764 | struct page *dest; |
| 765 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; |
| 766 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; |
| 767 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; |
| 768 | dma_addr_t dest_dma; |
| 769 | struct dma_async_tx_descriptor *tx; |
| 770 | struct dma_chan *dma_chan; |
| 771 | dma_cookie_t cookie; |
| 772 | u8 cmp_byte = 0; |
| 773 | u32 cmp_word; |
| 774 | u32 xor_val_result; |
| 775 | int err = 0; |
| 776 | struct completion cmp; |
| 777 | unsigned long tmo; |
| 778 | struct device *dev = &ioat_dma->pdev->dev; |
| 779 | struct dma_device *dma = &ioat_dma->dma_dev; |
| 780 | u8 op = 0; |
| 781 | |
| 782 | dev_dbg(dev, "%s\n", __func__); |
| 783 | |
| 784 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) |
| 785 | return 0; |
| 786 | |
| 787 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { |
| 788 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
| 789 | if (!xor_srcs[src_idx]) { |
| 790 | while (src_idx--) |
| 791 | __free_page(xor_srcs[src_idx]); |
| 792 | return -ENOMEM; |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | dest = alloc_page(GFP_KERNEL); |
| 797 | if (!dest) { |
| 798 | while (src_idx--) |
| 799 | __free_page(xor_srcs[src_idx]); |
| 800 | return -ENOMEM; |
| 801 | } |
| 802 | |
| 803 | /* Fill in src buffers */ |
| 804 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { |
| 805 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 806 | |
| 807 | for (i = 0; i < PAGE_SIZE; i++) |
| 808 | ptr[i] = (1 << src_idx); |
| 809 | } |
| 810 | |
| 811 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) |
| 812 | cmp_byte ^= (u8) (1 << src_idx); |
| 813 | |
| 814 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 815 | (cmp_byte << 8) | cmp_byte; |
| 816 | |
| 817 | memset(page_address(dest), 0, PAGE_SIZE); |
| 818 | |
| 819 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
| 820 | device_node); |
| 821 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
| 822 | err = -ENODEV; |
| 823 | goto out; |
| 824 | } |
| 825 | |
| 826 | /* test xor */ |
| 827 | op = IOAT_OP_XOR; |
| 828 | |
| 829 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
| 830 | if (dma_mapping_error(dev, dest_dma)) |
Dave Jiang | 2eab9b1 | 2016-07-21 12:40:52 -0700 | [diff] [blame] | 831 | goto free_resources; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 832 | |
| 833 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 834 | dma_srcs[i] = DMA_ERROR_CODE; |
| 835 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) { |
| 836 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, |
| 837 | DMA_TO_DEVICE); |
| 838 | if (dma_mapping_error(dev, dma_srcs[i])) |
| 839 | goto dma_unmap; |
| 840 | } |
| 841 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
| 842 | IOAT_NUM_SRC_TEST, PAGE_SIZE, |
| 843 | DMA_PREP_INTERRUPT); |
| 844 | |
| 845 | if (!tx) { |
| 846 | dev_err(dev, "Self-test xor prep failed\n"); |
| 847 | err = -ENODEV; |
| 848 | goto dma_unmap; |
| 849 | } |
| 850 | |
| 851 | async_tx_ack(tx); |
| 852 | init_completion(&cmp); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 853 | tx->callback = ioat_dma_test_callback; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 854 | tx->callback_param = &cmp; |
| 855 | cookie = tx->tx_submit(tx); |
| 856 | if (cookie < 0) { |
| 857 | dev_err(dev, "Self-test xor setup failed\n"); |
| 858 | err = -ENODEV; |
| 859 | goto dma_unmap; |
| 860 | } |
| 861 | dma->device_issue_pending(dma_chan); |
| 862 | |
| 863 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 864 | |
| 865 | if (tmo == 0 || |
| 866 | dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { |
| 867 | dev_err(dev, "Self-test xor timed out\n"); |
| 868 | err = -ENODEV; |
| 869 | goto dma_unmap; |
| 870 | } |
| 871 | |
| 872 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 873 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 874 | |
| 875 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
| 876 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 877 | u32 *ptr = page_address(dest); |
| 878 | |
| 879 | if (ptr[i] != cmp_word) { |
| 880 | dev_err(dev, "Self-test xor failed compare\n"); |
| 881 | err = -ENODEV; |
| 882 | goto free_resources; |
| 883 | } |
| 884 | } |
| 885 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
| 886 | |
| 887 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); |
| 888 | |
| 889 | /* skip validate if the capability is not present */ |
| 890 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) |
| 891 | goto free_resources; |
| 892 | |
| 893 | op = IOAT_OP_XOR_VAL; |
| 894 | |
| 895 | /* validate the sources with the destintation page */ |
| 896 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 897 | xor_val_srcs[i] = xor_srcs[i]; |
| 898 | xor_val_srcs[i] = dest; |
| 899 | |
| 900 | xor_val_result = 1; |
| 901 | |
| 902 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 903 | dma_srcs[i] = DMA_ERROR_CODE; |
| 904 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { |
| 905 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, |
| 906 | DMA_TO_DEVICE); |
| 907 | if (dma_mapping_error(dev, dma_srcs[i])) |
| 908 | goto dma_unmap; |
| 909 | } |
| 910 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, |
| 911 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, |
| 912 | &xor_val_result, DMA_PREP_INTERRUPT); |
| 913 | if (!tx) { |
| 914 | dev_err(dev, "Self-test zero prep failed\n"); |
| 915 | err = -ENODEV; |
| 916 | goto dma_unmap; |
| 917 | } |
| 918 | |
| 919 | async_tx_ack(tx); |
| 920 | init_completion(&cmp); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 921 | tx->callback = ioat_dma_test_callback; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 922 | tx->callback_param = &cmp; |
| 923 | cookie = tx->tx_submit(tx); |
| 924 | if (cookie < 0) { |
| 925 | dev_err(dev, "Self-test zero setup failed\n"); |
| 926 | err = -ENODEV; |
| 927 | goto dma_unmap; |
| 928 | } |
| 929 | dma->device_issue_pending(dma_chan); |
| 930 | |
| 931 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 932 | |
| 933 | if (tmo == 0 || |
| 934 | dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { |
| 935 | dev_err(dev, "Self-test validate timed out\n"); |
| 936 | err = -ENODEV; |
| 937 | goto dma_unmap; |
| 938 | } |
| 939 | |
| 940 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 941 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 942 | |
| 943 | if (xor_val_result != 0) { |
| 944 | dev_err(dev, "Self-test validate failed compare\n"); |
| 945 | err = -ENODEV; |
| 946 | goto free_resources; |
| 947 | } |
| 948 | |
| 949 | memset(page_address(dest), 0, PAGE_SIZE); |
| 950 | |
| 951 | /* test for non-zero parity sum */ |
| 952 | op = IOAT_OP_XOR_VAL; |
| 953 | |
| 954 | xor_val_result = 0; |
| 955 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 956 | dma_srcs[i] = DMA_ERROR_CODE; |
| 957 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) { |
| 958 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, |
| 959 | DMA_TO_DEVICE); |
| 960 | if (dma_mapping_error(dev, dma_srcs[i])) |
| 961 | goto dma_unmap; |
| 962 | } |
| 963 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, |
| 964 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, |
| 965 | &xor_val_result, DMA_PREP_INTERRUPT); |
| 966 | if (!tx) { |
| 967 | dev_err(dev, "Self-test 2nd zero prep failed\n"); |
| 968 | err = -ENODEV; |
| 969 | goto dma_unmap; |
| 970 | } |
| 971 | |
| 972 | async_tx_ack(tx); |
| 973 | init_completion(&cmp); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 974 | tx->callback = ioat_dma_test_callback; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 975 | tx->callback_param = &cmp; |
| 976 | cookie = tx->tx_submit(tx); |
| 977 | if (cookie < 0) { |
| 978 | dev_err(dev, "Self-test 2nd zero setup failed\n"); |
| 979 | err = -ENODEV; |
| 980 | goto dma_unmap; |
| 981 | } |
| 982 | dma->device_issue_pending(dma_chan); |
| 983 | |
| 984 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 985 | |
| 986 | if (tmo == 0 || |
| 987 | dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { |
| 988 | dev_err(dev, "Self-test 2nd validate timed out\n"); |
| 989 | err = -ENODEV; |
| 990 | goto dma_unmap; |
| 991 | } |
| 992 | |
| 993 | if (xor_val_result != SUM_CHECK_P_RESULT) { |
| 994 | dev_err(dev, "Self-test validate failed compare\n"); |
| 995 | err = -ENODEV; |
| 996 | goto dma_unmap; |
| 997 | } |
| 998 | |
| 999 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1000 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE); |
| 1001 | |
| 1002 | goto free_resources; |
| 1003 | dma_unmap: |
| 1004 | if (op == IOAT_OP_XOR) { |
| 1005 | if (dest_dma != DMA_ERROR_CODE) |
| 1006 | dma_unmap_page(dev, dest_dma, PAGE_SIZE, |
| 1007 | DMA_FROM_DEVICE); |
| 1008 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) |
| 1009 | if (dma_srcs[i] != DMA_ERROR_CODE) |
| 1010 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, |
| 1011 | DMA_TO_DEVICE); |
| 1012 | } else if (op == IOAT_OP_XOR_VAL) { |
| 1013 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) |
| 1014 | if (dma_srcs[i] != DMA_ERROR_CODE) |
| 1015 | dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, |
| 1016 | DMA_TO_DEVICE); |
| 1017 | } |
| 1018 | free_resources: |
| 1019 | dma->device_free_chan_resources(dma_chan); |
| 1020 | out: |
| 1021 | src_idx = IOAT_NUM_SRC_TEST; |
| 1022 | while (src_idx--) |
| 1023 | __free_page(xor_srcs[src_idx]); |
| 1024 | __free_page(dest); |
| 1025 | return err; |
| 1026 | } |
| 1027 | |
| 1028 | static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma) |
| 1029 | { |
Dave Jiang | 64f1d0f | 2015-08-20 08:44:14 -0700 | [diff] [blame] | 1030 | int rc; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1031 | |
Dave Jiang | 64f1d0f | 2015-08-20 08:44:14 -0700 | [diff] [blame] | 1032 | rc = ioat_dma_self_test(ioat_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1033 | if (rc) |
| 1034 | return rc; |
| 1035 | |
| 1036 | rc = ioat_xor_val_self_test(ioat_dma); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1037 | |
Dave Jiang | 64f1d0f | 2015-08-20 08:44:14 -0700 | [diff] [blame] | 1038 | return rc; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1039 | } |
| 1040 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 1041 | static void ioat_intr_quirk(struct ioatdma_device *ioat_dma) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1042 | { |
| 1043 | struct dma_device *dma; |
| 1044 | struct dma_chan *c; |
| 1045 | struct ioatdma_chan *ioat_chan; |
| 1046 | u32 errmask; |
| 1047 | |
| 1048 | dma = &ioat_dma->dma_dev; |
| 1049 | |
| 1050 | /* |
| 1051 | * if we have descriptor write back error status, we mask the |
| 1052 | * error interrupts |
| 1053 | */ |
| 1054 | if (ioat_dma->cap & IOAT_CAP_DWBES) { |
| 1055 | list_for_each_entry(c, &dma->channels, device_node) { |
| 1056 | ioat_chan = to_ioat_chan(c); |
| 1057 | errmask = readl(ioat_chan->reg_base + |
| 1058 | IOAT_CHANERR_MASK_OFFSET); |
| 1059 | errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR | |
| 1060 | IOAT_CHANERR_XOR_Q_ERR; |
| 1061 | writel(errmask, ioat_chan->reg_base + |
| 1062 | IOAT_CHANERR_MASK_OFFSET); |
| 1063 | } |
| 1064 | } |
| 1065 | } |
| 1066 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame] | 1067 | static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1068 | { |
| 1069 | struct pci_dev *pdev = ioat_dma->pdev; |
| 1070 | int dca_en = system_has_dca_enabled(pdev); |
| 1071 | struct dma_device *dma; |
| 1072 | struct dma_chan *c; |
| 1073 | struct ioatdma_chan *ioat_chan; |
| 1074 | bool is_raid_device = false; |
| 1075 | int err; |
Dave Jiang | 511deae | 2016-05-11 14:32:49 -0700 | [diff] [blame] | 1076 | u16 val16; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1077 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1078 | dma = &ioat_dma->dma_dev; |
| 1079 | dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock; |
| 1080 | dma->device_issue_pending = ioat_issue_pending; |
| 1081 | dma->device_alloc_chan_resources = ioat_alloc_chan_resources; |
| 1082 | dma->device_free_chan_resources = ioat_free_chan_resources; |
| 1083 | |
| 1084 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); |
| 1085 | dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock; |
| 1086 | |
| 1087 | ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); |
| 1088 | |
| 1089 | if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev)) |
| 1090 | ioat_dma->cap &= |
| 1091 | ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS); |
| 1092 | |
| 1093 | /* dca is incompatible with raid operations */ |
| 1094 | if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) |
| 1095 | ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); |
| 1096 | |
| 1097 | if (ioat_dma->cap & IOAT_CAP_XOR) { |
| 1098 | is_raid_device = true; |
| 1099 | dma->max_xor = 8; |
| 1100 | |
| 1101 | dma_cap_set(DMA_XOR, dma->cap_mask); |
| 1102 | dma->device_prep_dma_xor = ioat_prep_xor; |
| 1103 | |
| 1104 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); |
| 1105 | dma->device_prep_dma_xor_val = ioat_prep_xor_val; |
| 1106 | } |
| 1107 | |
| 1108 | if (ioat_dma->cap & IOAT_CAP_PQ) { |
| 1109 | is_raid_device = true; |
| 1110 | |
| 1111 | dma->device_prep_dma_pq = ioat_prep_pq; |
| 1112 | dma->device_prep_dma_pq_val = ioat_prep_pq_val; |
| 1113 | dma_cap_set(DMA_PQ, dma->cap_mask); |
| 1114 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); |
| 1115 | |
| 1116 | if (ioat_dma->cap & IOAT_CAP_RAID16SS) |
| 1117 | dma_set_maxpq(dma, 16, 0); |
| 1118 | else |
| 1119 | dma_set_maxpq(dma, 8, 0); |
| 1120 | |
| 1121 | if (!(ioat_dma->cap & IOAT_CAP_XOR)) { |
| 1122 | dma->device_prep_dma_xor = ioat_prep_pqxor; |
| 1123 | dma->device_prep_dma_xor_val = ioat_prep_pqxor_val; |
| 1124 | dma_cap_set(DMA_XOR, dma->cap_mask); |
| 1125 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); |
| 1126 | |
| 1127 | if (ioat_dma->cap & IOAT_CAP_RAID16SS) |
| 1128 | dma->max_xor = 16; |
| 1129 | else |
| 1130 | dma->max_xor = 8; |
| 1131 | } |
| 1132 | } |
| 1133 | |
| 1134 | dma->device_tx_status = ioat_tx_status; |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1135 | |
| 1136 | /* starting with CB3.3 super extended descriptors are supported */ |
| 1137 | if (ioat_dma->cap & IOAT_CAP_RAID16SS) { |
| 1138 | char pool_name[14]; |
| 1139 | int i; |
| 1140 | |
| 1141 | for (i = 0; i < MAX_SED_POOLS; i++) { |
| 1142 | snprintf(pool_name, 14, "ioat_hw%d_sed", i); |
| 1143 | |
| 1144 | /* allocate SED DMA pool */ |
| 1145 | ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name, |
| 1146 | &pdev->dev, |
| 1147 | SED_SIZE * (i + 1), 64, 0); |
| 1148 | if (!ioat_dma->sed_hw_pool[i]) |
| 1149 | return -ENOMEM; |
| 1150 | |
| 1151 | } |
| 1152 | } |
| 1153 | |
| 1154 | if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ))) |
| 1155 | dma_cap_set(DMA_PRIVATE, dma->cap_mask); |
| 1156 | |
| 1157 | err = ioat_probe(ioat_dma); |
| 1158 | if (err) |
| 1159 | return err; |
| 1160 | |
| 1161 | list_for_each_entry(c, &dma->channels, device_node) { |
| 1162 | ioat_chan = to_ioat_chan(c); |
| 1163 | writel(IOAT_DMA_DCA_ANY_CPU, |
| 1164 | ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); |
| 1165 | } |
| 1166 | |
| 1167 | err = ioat_register(ioat_dma); |
| 1168 | if (err) |
| 1169 | return err; |
| 1170 | |
| 1171 | ioat_kobject_add(ioat_dma, &ioat_ktype); |
| 1172 | |
| 1173 | if (dca) |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 1174 | ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1175 | |
Dave Jiang | 511deae | 2016-05-11 14:32:49 -0700 | [diff] [blame] | 1176 | /* disable relaxed ordering */ |
| 1177 | err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16); |
| 1178 | if (err) |
| 1179 | return err; |
| 1180 | |
| 1181 | /* clear relaxed ordering enable */ |
| 1182 | val16 &= ~IOAT_DEVCTRL_ROE; |
| 1183 | err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16); |
| 1184 | if (err) |
| 1185 | return err; |
| 1186 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1187 | return 0; |
| 1188 | } |
| 1189 | |
Dave Jiang | ad4a7b5 | 2015-08-26 13:17:24 -0700 | [diff] [blame] | 1190 | static void ioat_shutdown(struct pci_dev *pdev) |
| 1191 | { |
| 1192 | struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); |
| 1193 | struct ioatdma_chan *ioat_chan; |
| 1194 | int i; |
| 1195 | |
| 1196 | if (!ioat_dma) |
| 1197 | return; |
| 1198 | |
| 1199 | for (i = 0; i < IOAT_MAX_CHANS; i++) { |
| 1200 | ioat_chan = ioat_dma->idx[i]; |
| 1201 | if (!ioat_chan) |
| 1202 | continue; |
| 1203 | |
| 1204 | spin_lock_bh(&ioat_chan->prep_lock); |
| 1205 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
| 1206 | del_timer_sync(&ioat_chan->timer); |
| 1207 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 1208 | /* this should quiesce then reset */ |
| 1209 | ioat_reset_hw(ioat_chan); |
| 1210 | } |
| 1211 | |
| 1212 | ioat_disable_interrupts(ioat_dma); |
| 1213 | } |
| 1214 | |
Vinod Koul | 184ff2a | 2016-07-16 19:56:21 +0530 | [diff] [blame] | 1215 | static void ioat_resume(struct ioatdma_device *ioat_dma) |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1216 | { |
| 1217 | struct ioatdma_chan *ioat_chan; |
| 1218 | u32 chanerr; |
| 1219 | int i; |
| 1220 | |
| 1221 | for (i = 0; i < IOAT_MAX_CHANS; i++) { |
| 1222 | ioat_chan = ioat_dma->idx[i]; |
| 1223 | if (!ioat_chan) |
| 1224 | continue; |
| 1225 | |
| 1226 | spin_lock_bh(&ioat_chan->prep_lock); |
| 1227 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
| 1228 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 1229 | |
| 1230 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 1231 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 1232 | |
| 1233 | /* no need to reset as shutdown already did that */ |
| 1234 | } |
| 1235 | } |
| 1236 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1237 | #define DRV_NAME "ioatdma" |
| 1238 | |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1239 | static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, |
| 1240 | enum pci_channel_state error) |
| 1241 | { |
| 1242 | dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); |
| 1243 | |
| 1244 | /* quiesce and block I/O */ |
| 1245 | ioat_shutdown(pdev); |
| 1246 | |
| 1247 | return PCI_ERS_RESULT_NEED_RESET; |
| 1248 | } |
| 1249 | |
| 1250 | static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) |
| 1251 | { |
| 1252 | pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; |
| 1253 | int err; |
| 1254 | |
| 1255 | dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); |
| 1256 | |
| 1257 | if (pci_enable_device_mem(pdev) < 0) { |
| 1258 | dev_err(&pdev->dev, |
| 1259 | "Failed to enable PCIe device after reset.\n"); |
| 1260 | result = PCI_ERS_RESULT_DISCONNECT; |
| 1261 | } else { |
| 1262 | pci_set_master(pdev); |
| 1263 | pci_restore_state(pdev); |
| 1264 | pci_save_state(pdev); |
| 1265 | pci_wake_from_d3(pdev, false); |
| 1266 | } |
| 1267 | |
| 1268 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
| 1269 | if (err) { |
| 1270 | dev_err(&pdev->dev, |
| 1271 | "AER uncorrect error status clear failed: %#x\n", err); |
| 1272 | } |
| 1273 | |
| 1274 | return result; |
| 1275 | } |
| 1276 | |
| 1277 | static void ioat_pcie_error_resume(struct pci_dev *pdev) |
| 1278 | { |
| 1279 | struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); |
| 1280 | |
| 1281 | dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); |
| 1282 | |
| 1283 | /* initialize and bring everything back */ |
| 1284 | ioat_resume(ioat_dma); |
| 1285 | } |
| 1286 | |
| 1287 | static const struct pci_error_handlers ioat_err_handler = { |
| 1288 | .error_detected = ioat_pcie_error_detected, |
| 1289 | .slot_reset = ioat_pcie_error_slot_reset, |
| 1290 | .resume = ioat_pcie_error_resume, |
| 1291 | }; |
| 1292 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1293 | static struct pci_driver ioat_pci_driver = { |
| 1294 | .name = DRV_NAME, |
| 1295 | .id_table = ioat_pci_tbl, |
| 1296 | .probe = ioat_pci_probe, |
| 1297 | .remove = ioat_remove, |
Dave Jiang | ad4a7b5 | 2015-08-26 13:17:24 -0700 | [diff] [blame] | 1298 | .shutdown = ioat_shutdown, |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1299 | .err_handler = &ioat_err_handler, |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1300 | }; |
| 1301 | |
| 1302 | static struct ioatdma_device * |
| 1303 | alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) |
| 1304 | { |
| 1305 | struct device *dev = &pdev->dev; |
| 1306 | struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); |
| 1307 | |
| 1308 | if (!d) |
| 1309 | return NULL; |
| 1310 | d->pdev = pdev; |
| 1311 | d->reg_base = iobase; |
| 1312 | return d; |
| 1313 | } |
| 1314 | |
| 1315 | static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 1316 | { |
| 1317 | void __iomem * const *iomap; |
| 1318 | struct device *dev = &pdev->dev; |
| 1319 | struct ioatdma_device *device; |
| 1320 | int err; |
| 1321 | |
| 1322 | err = pcim_enable_device(pdev); |
| 1323 | if (err) |
| 1324 | return err; |
| 1325 | |
| 1326 | err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); |
| 1327 | if (err) |
| 1328 | return err; |
| 1329 | iomap = pcim_iomap_table(pdev); |
| 1330 | if (!iomap) |
| 1331 | return -ENOMEM; |
| 1332 | |
| 1333 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
| 1334 | if (err) |
| 1335 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 1336 | if (err) |
| 1337 | return err; |
| 1338 | |
| 1339 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
| 1340 | if (err) |
| 1341 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 1342 | if (err) |
| 1343 | return err; |
| 1344 | |
| 1345 | device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); |
| 1346 | if (!device) |
| 1347 | return -ENOMEM; |
| 1348 | pci_set_master(pdev); |
| 1349 | pci_set_drvdata(pdev, device); |
| 1350 | |
| 1351 | device->version = readb(device->reg_base + IOAT_VER_OFFSET); |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1352 | if (device->version >= IOAT_VER_3_0) { |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1353 | err = ioat3_dma_probe(device, ioat_dca_enabled); |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1354 | |
| 1355 | if (device->version >= IOAT_VER_3_3) |
| 1356 | pci_enable_pcie_error_reporting(pdev); |
| 1357 | } else |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1358 | return -ENODEV; |
| 1359 | |
| 1360 | if (err) { |
| 1361 | dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1362 | pci_disable_pcie_error_reporting(pdev); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1363 | return -ENODEV; |
| 1364 | } |
| 1365 | |
| 1366 | return 0; |
| 1367 | } |
| 1368 | |
| 1369 | static void ioat_remove(struct pci_dev *pdev) |
| 1370 | { |
| 1371 | struct ioatdma_device *device = pci_get_drvdata(pdev); |
| 1372 | |
| 1373 | if (!device) |
| 1374 | return; |
| 1375 | |
| 1376 | dev_err(&pdev->dev, "Removing dma and dca services\n"); |
| 1377 | if (device->dca) { |
| 1378 | unregister_dca_provider(device->dca, &pdev->dev); |
| 1379 | free_dca_provider(device->dca); |
| 1380 | device->dca = NULL; |
| 1381 | } |
Dave Jiang | 4222a90 | 2015-08-26 13:17:30 -0700 | [diff] [blame] | 1382 | |
| 1383 | pci_disable_pcie_error_reporting(pdev); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 1384 | ioat_dma_remove(device); |
| 1385 | } |
| 1386 | |
| 1387 | static int __init ioat_init_module(void) |
| 1388 | { |
| 1389 | int err = -ENOMEM; |
| 1390 | |
| 1391 | pr_info("%s: Intel(R) QuickData Technology Driver %s\n", |
| 1392 | DRV_NAME, IOAT_DMA_VERSION); |
| 1393 | |
| 1394 | ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent), |
| 1395 | 0, SLAB_HWCACHE_ALIGN, NULL); |
| 1396 | if (!ioat_cache) |
| 1397 | return -ENOMEM; |
| 1398 | |
| 1399 | ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0); |
| 1400 | if (!ioat_sed_cache) |
| 1401 | goto err_ioat_cache; |
| 1402 | |
| 1403 | err = pci_register_driver(&ioat_pci_driver); |
| 1404 | if (err) |
| 1405 | goto err_ioat3_cache; |
| 1406 | |
| 1407 | return 0; |
| 1408 | |
| 1409 | err_ioat3_cache: |
| 1410 | kmem_cache_destroy(ioat_sed_cache); |
| 1411 | |
| 1412 | err_ioat_cache: |
| 1413 | kmem_cache_destroy(ioat_cache); |
| 1414 | |
| 1415 | return err; |
| 1416 | } |
| 1417 | module_init(ioat_init_module); |
| 1418 | |
| 1419 | static void __exit ioat_exit_module(void) |
| 1420 | { |
| 1421 | pci_unregister_driver(&ioat_pci_driver); |
| 1422 | kmem_cache_destroy(ioat_cache); |
| 1423 | } |
| 1424 | module_exit(ioat_exit_module); |