Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2008-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __ADRENO_H |
| 14 | #define __ADRENO_H |
| 15 | |
| 16 | #include "kgsl_device.h" |
| 17 | #include "kgsl_sharedmem.h" |
| 18 | #include "adreno_drawctxt.h" |
| 19 | #include "adreno_ringbuffer.h" |
| 20 | #include "adreno_profile.h" |
| 21 | #include "adreno_dispatch.h" |
| 22 | #include "kgsl_iommu.h" |
| 23 | #include "adreno_perfcounter.h" |
| 24 | #include <linux/stat.h> |
| 25 | #include <linux/delay.h> |
Carter Cooper | 05f2a6b | 2017-03-20 11:43:11 -0600 | [diff] [blame] | 26 | #include "kgsl_gmu.h" |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 27 | |
| 28 | #include "a4xx_reg.h" |
| 29 | |
| 30 | #ifdef CONFIG_QCOM_OCMEM |
| 31 | #include <soc/qcom/ocmem.h> |
| 32 | #endif |
| 33 | |
| 34 | #define DEVICE_3D_NAME "kgsl-3d" |
| 35 | #define DEVICE_3D0_NAME "kgsl-3d0" |
| 36 | |
| 37 | /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ |
| 38 | #define ADRENO_DEVICE(device) \ |
| 39 | container_of(device, struct adreno_device, dev) |
| 40 | |
| 41 | /* KGSL_DEVICE - given an adreno_device, return the KGSL device struct */ |
| 42 | #define KGSL_DEVICE(_dev) (&((_dev)->dev)) |
| 43 | |
| 44 | /* ADRENO_CONTEXT - Given a context return the adreno context struct */ |
| 45 | #define ADRENO_CONTEXT(context) \ |
| 46 | container_of(context, struct adreno_context, base) |
| 47 | |
| 48 | /* ADRENO_GPU_DEVICE - Given an adreno device return the GPU specific struct */ |
| 49 | #define ADRENO_GPU_DEVICE(_a) ((_a)->gpucore->gpudev) |
| 50 | |
| 51 | #define ADRENO_CHIPID_CORE(_id) (((_id) >> 24) & 0xFF) |
| 52 | #define ADRENO_CHIPID_MAJOR(_id) (((_id) >> 16) & 0xFF) |
| 53 | #define ADRENO_CHIPID_MINOR(_id) (((_id) >> 8) & 0xFF) |
| 54 | #define ADRENO_CHIPID_PATCH(_id) ((_id) & 0xFF) |
| 55 | |
| 56 | /* ADRENO_GPUREV - Return the GPU ID for the given adreno_device */ |
| 57 | #define ADRENO_GPUREV(_a) ((_a)->gpucore->gpurev) |
| 58 | |
| 59 | /* |
| 60 | * ADRENO_FEATURE - return true if the specified feature is supported by the GPU |
| 61 | * core |
| 62 | */ |
| 63 | #define ADRENO_FEATURE(_dev, _bit) \ |
| 64 | ((_dev)->gpucore->features & (_bit)) |
| 65 | |
| 66 | /** |
| 67 | * ADRENO_QUIRK - return true if the specified quirk is required by the GPU |
| 68 | */ |
| 69 | #define ADRENO_QUIRK(_dev, _bit) \ |
| 70 | ((_dev)->quirks & (_bit)) |
| 71 | |
| 72 | /* |
| 73 | * ADRENO_PREEMPT_STYLE - return preemption style |
| 74 | */ |
| 75 | #define ADRENO_PREEMPT_STYLE(flags) \ |
| 76 | ((flags & KGSL_CONTEXT_PREEMPT_STYLE_MASK) >> \ |
| 77 | KGSL_CONTEXT_PREEMPT_STYLE_SHIFT) |
| 78 | |
| 79 | /* |
| 80 | * return the dispatcher drawqueue in which the given drawobj should |
| 81 | * be submitted |
| 82 | */ |
| 83 | #define ADRENO_DRAWOBJ_DISPATCH_DRAWQUEUE(c) \ |
| 84 | (&((ADRENO_CONTEXT(c->context))->rb->dispatch_q)) |
| 85 | |
| 86 | #define ADRENO_DRAWOBJ_RB(c) \ |
| 87 | ((ADRENO_CONTEXT(c->context))->rb) |
| 88 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 89 | #define ADRENO_FW(a, f) (&(a->fw[f])) |
| 90 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 91 | /* Adreno core features */ |
| 92 | /* The core uses OCMEM for GMEM/binning memory */ |
| 93 | #define ADRENO_USES_OCMEM BIT(0) |
| 94 | /* The core supports an accelerated warm start */ |
| 95 | #define ADRENO_WARM_START BIT(1) |
| 96 | /* The core supports the microcode bootstrap functionality */ |
| 97 | #define ADRENO_USE_BOOTSTRAP BIT(2) |
| 98 | /* The core supports SP/TP hw controlled power collapse */ |
| 99 | #define ADRENO_SPTP_PC BIT(3) |
| 100 | /* The core supports Peak Power Detection(PPD)*/ |
| 101 | #define ADRENO_PPD BIT(4) |
| 102 | /* The GPU supports content protection */ |
| 103 | #define ADRENO_CONTENT_PROTECTION BIT(5) |
| 104 | /* The GPU supports preemption */ |
| 105 | #define ADRENO_PREEMPTION BIT(6) |
| 106 | /* The core uses GPMU for power and limit management */ |
| 107 | #define ADRENO_GPMU BIT(7) |
| 108 | /* The GPMU supports Limits Management */ |
| 109 | #define ADRENO_LM BIT(8) |
| 110 | /* The core uses 64 bit GPU addresses */ |
| 111 | #define ADRENO_64BIT BIT(9) |
| 112 | /* The GPU supports retention for cpz registers */ |
| 113 | #define ADRENO_CPZ_RETENTION BIT(10) |
Shrenuj Bansal | ae67281 | 2016-02-24 14:17:30 -0800 | [diff] [blame] | 114 | /* The core has soft fault detection available */ |
| 115 | #define ADRENO_SOFT_FAULT_DETECT BIT(11) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 116 | /* The GMU supports RPMh for power management*/ |
| 117 | #define ADRENO_RPMH BIT(12) |
| 118 | /* The GMU supports IFPC power management*/ |
| 119 | #define ADRENO_IFPC BIT(13) |
| 120 | /* The GMU supports HW based NAP */ |
| 121 | #define ADRENO_HW_NAP BIT(14) |
| 122 | /* The GMU supports min voltage*/ |
| 123 | #define ADRENO_MIN_VOLT BIT(15) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 124 | |
| 125 | /* |
| 126 | * Adreno GPU quirks - control bits for various workarounds |
| 127 | */ |
| 128 | |
Lynus Vaz | 85c8cee | 2017-03-07 11:31:02 +0530 | [diff] [blame] | 129 | /* Set TWOPASSUSEWFI in PC_DBG_ECO_CNTL (5XX/6XX) */ |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 130 | #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) |
| 131 | /* Lock/unlock mutex to sync with the IOMMU */ |
| 132 | #define ADRENO_QUIRK_IOMMU_SYNC BIT(1) |
| 133 | /* Submit critical packets at GPU wake up */ |
| 134 | #define ADRENO_QUIRK_CRITICAL_PACKETS BIT(2) |
| 135 | /* Mask out RB1-3 activity signals from HW hang detection logic */ |
| 136 | #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(3) |
| 137 | /* Disable RB sampler datapath clock gating optimization */ |
| 138 | #define ADRENO_QUIRK_DISABLE_RB_DP2CLOCKGATING BIT(4) |
| 139 | /* Disable local memory(LM) feature to avoid corner case error */ |
| 140 | #define ADRENO_QUIRK_DISABLE_LMLOADKILL BIT(5) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 141 | /* Allow HFI to use registers to send message to GMU */ |
| 142 | #define ADRENO_QUIRK_HFI_USE_REG BIT(6) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 143 | |
| 144 | /* Flags to control command packet settings */ |
| 145 | #define KGSL_CMD_FLAGS_NONE 0 |
| 146 | #define KGSL_CMD_FLAGS_PMODE BIT(0) |
| 147 | #define KGSL_CMD_FLAGS_INTERNAL_ISSUE BIT(1) |
| 148 | #define KGSL_CMD_FLAGS_WFI BIT(2) |
| 149 | #define KGSL_CMD_FLAGS_PROFILE BIT(3) |
| 150 | #define KGSL_CMD_FLAGS_PWRON_FIXUP BIT(4) |
| 151 | |
| 152 | /* Command identifiers */ |
| 153 | #define KGSL_CONTEXT_TO_MEM_IDENTIFIER 0x2EADBEEF |
| 154 | #define KGSL_CMD_IDENTIFIER 0x2EEDFACE |
| 155 | #define KGSL_CMD_INTERNAL_IDENTIFIER 0x2EEDD00D |
| 156 | #define KGSL_START_OF_IB_IDENTIFIER 0x2EADEABE |
| 157 | #define KGSL_END_OF_IB_IDENTIFIER 0x2ABEDEAD |
| 158 | #define KGSL_START_OF_PROFILE_IDENTIFIER 0x2DEFADE1 |
| 159 | #define KGSL_END_OF_PROFILE_IDENTIFIER 0x2DEFADE2 |
| 160 | #define KGSL_PWRON_FIXUP_IDENTIFIER 0x2AFAFAFA |
| 161 | |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 162 | /* Number of times to try hard reset */ |
| 163 | #define NUM_TIMES_RESET_RETRY 5 |
| 164 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 165 | /* One cannot wait forever for the core to idle, so set an upper limit to the |
| 166 | * amount of time to wait for the core to go idle |
| 167 | */ |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 168 | #define ADRENO_IDLE_TIMEOUT (20 * 1000) |
| 169 | |
| 170 | #define ADRENO_UCHE_GMEM_BASE 0x100000 |
| 171 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 172 | #define ADRENO_FW_PFP 0 |
| 173 | #define ADRENO_FW_SQE 0 |
| 174 | #define ADRENO_FW_PM4 1 |
| 175 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 176 | enum adreno_gpurev { |
| 177 | ADRENO_REV_UNKNOWN = 0, |
| 178 | ADRENO_REV_A304 = 304, |
| 179 | ADRENO_REV_A305 = 305, |
| 180 | ADRENO_REV_A305C = 306, |
| 181 | ADRENO_REV_A306 = 307, |
| 182 | ADRENO_REV_A306A = 308, |
| 183 | ADRENO_REV_A310 = 310, |
| 184 | ADRENO_REV_A320 = 320, |
| 185 | ADRENO_REV_A330 = 330, |
| 186 | ADRENO_REV_A305B = 335, |
| 187 | ADRENO_REV_A405 = 405, |
| 188 | ADRENO_REV_A418 = 418, |
| 189 | ADRENO_REV_A420 = 420, |
| 190 | ADRENO_REV_A430 = 430, |
| 191 | ADRENO_REV_A505 = 505, |
| 192 | ADRENO_REV_A506 = 506, |
Rajesh Kemisetti | aed6ec7 | 2017-02-06 09:37:00 +0530 | [diff] [blame] | 193 | ADRENO_REV_A508 = 508, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 194 | ADRENO_REV_A510 = 510, |
| 195 | ADRENO_REV_A512 = 512, |
| 196 | ADRENO_REV_A530 = 530, |
| 197 | ADRENO_REV_A540 = 540, |
Rajesh Kemisetti | 8d5cc6e | 2017-06-06 16:44:17 +0530 | [diff] [blame] | 198 | ADRENO_REV_A615 = 615, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 199 | ADRENO_REV_A630 = 630, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | #define ADRENO_START_WARM 0 |
| 203 | #define ADRENO_START_COLD 1 |
| 204 | |
| 205 | #define ADRENO_SOFT_FAULT BIT(0) |
| 206 | #define ADRENO_HARD_FAULT BIT(1) |
| 207 | #define ADRENO_TIMEOUT_FAULT BIT(2) |
| 208 | #define ADRENO_IOMMU_PAGE_FAULT BIT(3) |
| 209 | #define ADRENO_PREEMPT_FAULT BIT(4) |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 210 | #define ADRENO_GMU_FAULT BIT(5) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 211 | |
| 212 | #define ADRENO_SPTP_PC_CTRL 0 |
| 213 | #define ADRENO_PPD_CTRL 1 |
| 214 | #define ADRENO_LM_CTRL 2 |
| 215 | #define ADRENO_HWCG_CTRL 3 |
| 216 | #define ADRENO_THROTTLING_CTRL 4 |
| 217 | |
| 218 | |
| 219 | /* number of throttle counters for DCVS adjustment */ |
| 220 | #define ADRENO_GPMU_THROTTLE_COUNTERS 4 |
| 221 | /* base for throttle counters */ |
| 222 | #define ADRENO_GPMU_THROTTLE_COUNTERS_BASE_REG 43 |
| 223 | |
| 224 | struct adreno_gpudev; |
| 225 | |
| 226 | /* Time to allow preemption to complete (in ms) */ |
| 227 | #define ADRENO_PREEMPT_TIMEOUT 10000 |
| 228 | |
| 229 | #define ADRENO_INT_BIT(a, _bit) (((a)->gpucore->gpudev->int_bits) ? \ |
| 230 | (adreno_get_int(a, _bit) < 0 ? 0 : \ |
| 231 | BIT(adreno_get_int(a, _bit))) : 0) |
| 232 | |
| 233 | /** |
| 234 | * enum adreno_preempt_states |
| 235 | * ADRENO_PREEMPT_NONE: No preemption is scheduled |
| 236 | * ADRENO_PREEMPT_START: The S/W has started |
| 237 | * ADRENO_PREEMPT_TRIGGERED: A preeempt has been triggered in the HW |
| 238 | * ADRENO_PREEMPT_FAULTED: The preempt timer has fired |
| 239 | * ADRENO_PREEMPT_PENDING: The H/W has signaled preemption complete |
| 240 | * ADRENO_PREEMPT_COMPLETE: Preemption could not be finished in the IRQ handler, |
| 241 | * worker has been scheduled |
| 242 | */ |
| 243 | enum adreno_preempt_states { |
| 244 | ADRENO_PREEMPT_NONE = 0, |
| 245 | ADRENO_PREEMPT_START, |
| 246 | ADRENO_PREEMPT_TRIGGERED, |
| 247 | ADRENO_PREEMPT_FAULTED, |
| 248 | ADRENO_PREEMPT_PENDING, |
| 249 | ADRENO_PREEMPT_COMPLETE, |
| 250 | }; |
| 251 | |
| 252 | /** |
| 253 | * struct adreno_preemption |
| 254 | * @state: The current state of preemption |
| 255 | * @counters: Memory descriptor for the memory where the GPU writes the |
| 256 | * preemption counters on switch |
| 257 | * @timer: A timer to make sure preemption doesn't stall |
| 258 | * @work: A work struct for the preemption worker (for 5XX) |
| 259 | * @token_submit: Indicates if a preempt token has been submitted in |
| 260 | * current ringbuffer (for 4XX) |
| 261 | */ |
| 262 | struct adreno_preemption { |
| 263 | atomic_t state; |
| 264 | struct kgsl_memdesc counters; |
| 265 | struct timer_list timer; |
| 266 | struct work_struct work; |
| 267 | bool token_submit; |
| 268 | }; |
| 269 | |
| 270 | |
| 271 | struct adreno_busy_data { |
| 272 | unsigned int gpu_busy; |
| 273 | unsigned int vbif_ram_cycles; |
| 274 | unsigned int vbif_starved_ram; |
| 275 | unsigned int throttle_cycles[ADRENO_GPMU_THROTTLE_COUNTERS]; |
| 276 | }; |
| 277 | |
| 278 | /** |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 279 | * struct adreno_firmware - Struct holding fw details |
| 280 | * @fwvirt: Buffer which holds the ucode |
| 281 | * @size: Size of ucode buffer |
| 282 | * @version: Version of ucode |
| 283 | * @memdesc: Memory descriptor which holds ucode buffer info |
| 284 | */ |
| 285 | struct adreno_firmware { |
| 286 | unsigned int *fwvirt; |
| 287 | size_t size; |
| 288 | unsigned int version; |
| 289 | struct kgsl_memdesc memdesc; |
| 290 | }; |
| 291 | |
| 292 | /** |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 293 | * struct adreno_gpu_core - A specific GPU core definition |
| 294 | * @gpurev: Unique GPU revision identifier |
| 295 | * @core: Match for the core version of the GPU |
| 296 | * @major: Match for the major version of the GPU |
| 297 | * @minor: Match for the minor version of the GPU |
| 298 | * @patchid: Match for the patch revision of the GPU |
| 299 | * @features: Common adreno features supported by this core |
| 300 | * @pm4fw_name: Filename for th PM4 firmware |
| 301 | * @pfpfw_name: Filename for the PFP firmware |
| 302 | * @zap_name: Filename for the Zap Shader ucode |
| 303 | * @gpudev: Pointer to the GPU family specific functions for this core |
| 304 | * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core |
| 305 | * @pm4_jt_idx: Index of the jump table in the PM4 microcode |
| 306 | * @pm4_jt_addr: Address offset to load the jump table for the PM4 microcode |
| 307 | * @pfp_jt_idx: Index of the jump table in the PFP microcode |
| 308 | * @pfp_jt_addr: Address offset to load the jump table for the PFP microcode |
| 309 | * @pm4_bstrp_size: Size of the bootstrap loader for PM4 microcode |
| 310 | * @pfp_bstrp_size: Size of the bootstrap loader for PFP microcde |
| 311 | * @pfp_bstrp_ver: Version of the PFP microcode that supports bootstraping |
| 312 | * @shader_offset: Offset of shader from gpu reg base |
| 313 | * @shader_size: Shader size |
| 314 | * @num_protected_regs: number of protected registers |
| 315 | * @gpmufw_name: Filename for the GPMU firmware |
| 316 | * @gpmu_major: Match for the GPMU & firmware, major revision |
| 317 | * @gpmu_minor: Match for the GPMU & firmware, minor revision |
| 318 | * @gpmu_features: Supported features for any given GPMU version |
| 319 | * @busy_mask: mask to check if GPU is busy in RBBM_STATUS |
| 320 | * @lm_major: Limits Management register sequence, major revision |
| 321 | * @lm_minor: LM register sequence, minor revision |
| 322 | * @regfw_name: Filename for the register sequence firmware |
| 323 | * @gpmu_tsens: ID for the temporature sensor used by the GPMU |
| 324 | * @max_power: Max possible power draw of a core, units elephant tail hairs |
| 325 | */ |
| 326 | struct adreno_gpu_core { |
| 327 | enum adreno_gpurev gpurev; |
| 328 | unsigned int core, major, minor, patchid; |
| 329 | unsigned long features; |
| 330 | const char *pm4fw_name; |
| 331 | const char *pfpfw_name; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 332 | const char *sqefw_name; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 333 | const char *zap_name; |
| 334 | struct adreno_gpudev *gpudev; |
| 335 | size_t gmem_size; |
| 336 | unsigned int pm4_jt_idx; |
| 337 | unsigned int pm4_jt_addr; |
| 338 | unsigned int pfp_jt_idx; |
| 339 | unsigned int pfp_jt_addr; |
| 340 | unsigned int pm4_bstrp_size; |
| 341 | unsigned int pfp_bstrp_size; |
| 342 | unsigned int pfp_bstrp_ver; |
| 343 | unsigned long shader_offset; |
| 344 | unsigned int shader_size; |
| 345 | unsigned int num_protected_regs; |
| 346 | const char *gpmufw_name; |
| 347 | unsigned int gpmu_major; |
| 348 | unsigned int gpmu_minor; |
| 349 | unsigned int gpmu_features; |
| 350 | unsigned int busy_mask; |
| 351 | unsigned int lm_major, lm_minor; |
| 352 | const char *regfw_name; |
| 353 | unsigned int gpmu_tsens; |
| 354 | unsigned int max_power; |
| 355 | }; |
| 356 | |
| 357 | /** |
| 358 | * struct adreno_device - The mothership structure for all adreno related info |
| 359 | * @dev: Reference to struct kgsl_device |
| 360 | * @priv: Holds the private flags specific to the adreno_device |
| 361 | * @chipid: Chip ID specific to the GPU |
| 362 | * @gmem_base: Base physical address of GMEM |
| 363 | * @gmem_size: GMEM size |
| 364 | * @gpucore: Pointer to the adreno_gpu_core structure |
| 365 | * @pfp_fw: Buffer which holds the pfp ucode |
| 366 | * @pfp_fw_size: Size of pfp ucode buffer |
| 367 | * @pfp_fw_version: Version of pfp ucode |
| 368 | * @pfp: Memory descriptor which holds pfp ucode buffer info |
| 369 | * @pm4_fw: Buffer which holds the pm4 ucode |
| 370 | * @pm4_fw_size: Size of pm4 ucode buffer |
| 371 | * @pm4_fw_version: Version of pm4 ucode |
| 372 | * @pm4: Memory descriptor which holds pm4 ucode buffer info |
| 373 | * @gpmu_cmds_size: Length of gpmu cmd stream |
| 374 | * @gpmu_cmds: gpmu cmd stream |
| 375 | * @ringbuffers: Array of pointers to adreno_ringbuffers |
| 376 | * @num_ringbuffers: Number of ringbuffers for the GPU |
| 377 | * @cur_rb: Pointer to the current ringbuffer |
| 378 | * @next_rb: Ringbuffer we are switching to during preemption |
| 379 | * @prev_rb: Ringbuffer we are switching from during preemption |
| 380 | * @fast_hang_detect: Software fault detection availability |
| 381 | * @ft_policy: Defines the fault tolerance policy |
| 382 | * @long_ib_detect: Long IB detection availability |
| 383 | * @ft_pf_policy: Defines the fault policy for page faults |
| 384 | * @ocmem_hdl: Handle to the ocmem allocated buffer |
| 385 | * @profile: Container for adreno profiler information |
| 386 | * @dispatcher: Container for adreno GPU dispatcher |
| 387 | * @pwron_fixup: Command buffer to run a post-power collapse shader workaround |
| 388 | * @pwron_fixup_dwords: Number of dwords in the command buffer |
| 389 | * @input_work: Work struct for turning on the GPU after a touch event |
| 390 | * @busy_data: Struct holding GPU VBIF busy stats |
| 391 | * @ram_cycles_lo: Number of DDR clock cycles for the monitor session |
| 392 | * @perfctr_pwr_lo: Number of cycles VBIF is stalled by DDR |
| 393 | * @halt: Atomic variable to check whether the GPU is currently halted |
Deepak Kumar | 273c571 | 2017-01-03 21:49:03 +0530 | [diff] [blame] | 394 | * @pending_irq_refcnt: Atomic variable to keep track of running IRQ handlers |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 395 | * @ctx_d_debugfs: Context debugfs node |
| 396 | * @pwrctrl_flag: Flag to hold adreno specific power attributes |
| 397 | * @profile_buffer: Memdesc holding the drawobj profiling buffer |
| 398 | * @profile_index: Index to store the start/stop ticks in the profiling |
| 399 | * buffer |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 400 | * @pwrup_reglist: Memdesc holding the power up register list |
| 401 | * which is used by CP during preemption and IFPC |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 402 | * @sp_local_gpuaddr: Base GPU virtual address for SP local memory |
| 403 | * @sp_pvt_gpuaddr: Base GPU virtual address for SP private memory |
| 404 | * @lm_fw: The LM firmware handle |
| 405 | * @lm_sequence: Pointer to the start of the register write sequence for LM |
| 406 | * @lm_size: The dword size of the LM sequence |
| 407 | * @lm_limit: limiting value for LM |
| 408 | * @lm_threshold_count: register value for counter for lm threshold breakin |
| 409 | * @lm_threshold_cross: number of current peaks exceeding threshold |
| 410 | * @speed_bin: Indicate which power level set to use |
| 411 | * @csdev: Pointer to a coresight device (if applicable) |
| 412 | * @gpmu_throttle_counters - counteers for number of throttled clocks |
| 413 | * @irq_storm_work: Worker to handle possible interrupt storms |
| 414 | * @active_list: List to track active contexts |
| 415 | * @active_list_lock: Lock to protect active_list |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 416 | * @gpu_llc_slice: GPU system cache slice descriptor |
Sushmita Susheelendra | b197668 | 2016-11-07 14:21:11 -0700 | [diff] [blame] | 417 | * @gpu_llc_slice_enable: To enable the GPU system cache slice or not |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 418 | * @gpuhtw_llc_slice: GPU pagetables system cache slice descriptor |
Sushmita Susheelendra | d3756c0 | 2017-01-11 15:05:40 -0700 | [diff] [blame] | 419 | * @gpuhtw_llc_slice_enable: To enable the GPUHTW system cache slice or not |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 420 | * @zap_loaded: Used to track if zap was successfully loaded or not |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 421 | */ |
| 422 | struct adreno_device { |
| 423 | struct kgsl_device dev; /* Must be first field in this struct */ |
| 424 | unsigned long priv; |
| 425 | unsigned int chipid; |
| 426 | unsigned long gmem_base; |
| 427 | unsigned long gmem_size; |
| 428 | const struct adreno_gpu_core *gpucore; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 429 | struct adreno_firmware fw[2]; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 430 | size_t gpmu_cmds_size; |
| 431 | unsigned int *gpmu_cmds; |
| 432 | struct adreno_ringbuffer ringbuffers[KGSL_PRIORITY_MAX_RB_LEVELS]; |
| 433 | int num_ringbuffers; |
| 434 | struct adreno_ringbuffer *cur_rb; |
| 435 | struct adreno_ringbuffer *next_rb; |
| 436 | struct adreno_ringbuffer *prev_rb; |
| 437 | unsigned int fast_hang_detect; |
| 438 | unsigned long ft_policy; |
| 439 | unsigned int long_ib_detect; |
| 440 | unsigned long ft_pf_policy; |
| 441 | struct ocmem_buf *ocmem_hdl; |
| 442 | struct adreno_profile profile; |
| 443 | struct adreno_dispatcher dispatcher; |
| 444 | struct kgsl_memdesc pwron_fixup; |
| 445 | unsigned int pwron_fixup_dwords; |
| 446 | struct work_struct input_work; |
| 447 | struct adreno_busy_data busy_data; |
| 448 | unsigned int ram_cycles_lo; |
| 449 | unsigned int starved_ram_lo; |
| 450 | unsigned int perfctr_pwr_lo; |
| 451 | atomic_t halt; |
Deepak Kumar | 273c571 | 2017-01-03 21:49:03 +0530 | [diff] [blame] | 452 | atomic_t pending_irq_refcnt; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 453 | struct dentry *ctx_d_debugfs; |
| 454 | unsigned long pwrctrl_flag; |
| 455 | |
| 456 | struct kgsl_memdesc profile_buffer; |
| 457 | unsigned int profile_index; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 458 | struct kgsl_memdesc pwrup_reglist; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 459 | uint64_t sp_local_gpuaddr; |
| 460 | uint64_t sp_pvt_gpuaddr; |
| 461 | const struct firmware *lm_fw; |
| 462 | uint32_t *lm_sequence; |
| 463 | uint32_t lm_size; |
| 464 | struct adreno_preemption preempt; |
| 465 | struct work_struct gpmu_work; |
| 466 | uint32_t lm_leakage; |
| 467 | uint32_t lm_limit; |
| 468 | uint32_t lm_threshold_count; |
| 469 | uint32_t lm_threshold_cross; |
| 470 | |
| 471 | unsigned int speed_bin; |
| 472 | unsigned int quirks; |
| 473 | |
| 474 | struct coresight_device *csdev; |
| 475 | uint32_t gpmu_throttle_counters[ADRENO_GPMU_THROTTLE_COUNTERS]; |
| 476 | struct work_struct irq_storm_work; |
| 477 | |
| 478 | struct list_head active_list; |
| 479 | spinlock_t active_list_lock; |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 480 | |
| 481 | void *gpu_llc_slice; |
Sushmita Susheelendra | b197668 | 2016-11-07 14:21:11 -0700 | [diff] [blame] | 482 | bool gpu_llc_slice_enable; |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 483 | void *gpuhtw_llc_slice; |
Sushmita Susheelendra | d3756c0 | 2017-01-11 15:05:40 -0700 | [diff] [blame] | 484 | bool gpuhtw_llc_slice_enable; |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 485 | unsigned int zap_loaded; |
Harshdeep Dhatt | 26c54f2 | 2017-08-30 17:37:39 -0600 | [diff] [blame] | 486 | unsigned int preempt_level; |
| 487 | bool usesgmem; |
| 488 | bool skipsaverestore; |
| 489 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 490 | }; |
| 491 | |
| 492 | /** |
| 493 | * enum adreno_device_flags - Private flags for the adreno_device |
| 494 | * @ADRENO_DEVICE_PWRON - Set during init after a power collapse |
| 495 | * @ADRENO_DEVICE_PWRON_FIXUP - Set if the target requires the shader fixup |
| 496 | * after power collapse |
| 497 | * @ADRENO_DEVICE_CORESIGHT - Set if the coresight (trace bus) registers should |
| 498 | * be restored after power collapse |
| 499 | * @ADRENO_DEVICE_HANG_INTR - Set if the hang interrupt should be enabled for |
| 500 | * this target |
| 501 | * @ADRENO_DEVICE_STARTED - Set if the device start sequence is in progress |
| 502 | * @ADRENO_DEVICE_FAULT - Set if the device is currently in fault (and shouldn't |
| 503 | * send any more commands to the ringbuffer) |
| 504 | * @ADRENO_DEVICE_DRAWOBJ_PROFILE - Set if the device supports drawobj |
| 505 | * profiling via the ALWAYSON counter |
| 506 | * @ADRENO_DEVICE_PREEMPTION - Turn on/off preemption |
| 507 | * @ADRENO_DEVICE_SOFT_FAULT_DETECT - Set if soft fault detect is enabled |
| 508 | * @ADRENO_DEVICE_GPMU_INITIALIZED - Set if GPMU firmware initialization succeed |
| 509 | * @ADRENO_DEVICE_ISDB_ENABLED - Set if the Integrated Shader DeBugger is |
| 510 | * attached and enabled |
| 511 | * @ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED - Set if a CACHE_FLUSH_TS irq storm |
| 512 | * is in progress |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 513 | * @ADRENO_DEVICE_HARD_RESET - Set if soft reset fails and hard reset is needed |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 514 | */ |
| 515 | enum adreno_device_flags { |
| 516 | ADRENO_DEVICE_PWRON = 0, |
| 517 | ADRENO_DEVICE_PWRON_FIXUP = 1, |
| 518 | ADRENO_DEVICE_INITIALIZED = 2, |
| 519 | ADRENO_DEVICE_CORESIGHT = 3, |
| 520 | ADRENO_DEVICE_HANG_INTR = 4, |
| 521 | ADRENO_DEVICE_STARTED = 5, |
| 522 | ADRENO_DEVICE_FAULT = 6, |
| 523 | ADRENO_DEVICE_DRAWOBJ_PROFILE = 7, |
| 524 | ADRENO_DEVICE_GPU_REGULATOR_ENABLED = 8, |
| 525 | ADRENO_DEVICE_PREEMPTION = 9, |
| 526 | ADRENO_DEVICE_SOFT_FAULT_DETECT = 10, |
| 527 | ADRENO_DEVICE_GPMU_INITIALIZED = 11, |
| 528 | ADRENO_DEVICE_ISDB_ENABLED = 12, |
| 529 | ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED = 13, |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 530 | ADRENO_DEVICE_HARD_RESET = 14, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 531 | }; |
| 532 | |
| 533 | /** |
| 534 | * struct adreno_drawobj_profile_entry - a single drawobj entry in the |
| 535 | * kernel profiling buffer |
| 536 | * @started: Number of GPU ticks at start of the drawobj |
| 537 | * @retired: Number of GPU ticks at the end of the drawobj |
| 538 | */ |
| 539 | struct adreno_drawobj_profile_entry { |
| 540 | uint64_t started; |
| 541 | uint64_t retired; |
| 542 | }; |
| 543 | |
| 544 | #define ADRENO_DRAWOBJ_PROFILE_COUNT \ |
| 545 | (PAGE_SIZE / sizeof(struct adreno_drawobj_profile_entry)) |
| 546 | |
| 547 | #define ADRENO_DRAWOBJ_PROFILE_OFFSET(_index, _member) \ |
| 548 | ((_index) * sizeof(struct adreno_drawobj_profile_entry) \ |
| 549 | + offsetof(struct adreno_drawobj_profile_entry, _member)) |
| 550 | |
| 551 | |
| 552 | /** |
| 553 | * adreno_regs: List of registers that are used in kgsl driver for all |
| 554 | * 3D devices. Each device type has different offset value for the same |
| 555 | * register, so an array of register offsets are declared for every device |
| 556 | * and are indexed by the enumeration values defined in this enum |
| 557 | */ |
| 558 | enum adreno_regs { |
| 559 | ADRENO_REG_CP_ME_RAM_WADDR, |
| 560 | ADRENO_REG_CP_ME_RAM_DATA, |
| 561 | ADRENO_REG_CP_PFP_UCODE_DATA, |
| 562 | ADRENO_REG_CP_PFP_UCODE_ADDR, |
| 563 | ADRENO_REG_CP_WFI_PEND_CTR, |
| 564 | ADRENO_REG_CP_RB_BASE, |
| 565 | ADRENO_REG_CP_RB_BASE_HI, |
| 566 | ADRENO_REG_CP_RB_RPTR_ADDR_LO, |
| 567 | ADRENO_REG_CP_RB_RPTR_ADDR_HI, |
| 568 | ADRENO_REG_CP_RB_RPTR, |
| 569 | ADRENO_REG_CP_RB_WPTR, |
| 570 | ADRENO_REG_CP_CNTL, |
| 571 | ADRENO_REG_CP_ME_CNTL, |
| 572 | ADRENO_REG_CP_RB_CNTL, |
| 573 | ADRENO_REG_CP_IB1_BASE, |
| 574 | ADRENO_REG_CP_IB1_BASE_HI, |
| 575 | ADRENO_REG_CP_IB1_BUFSZ, |
| 576 | ADRENO_REG_CP_IB2_BASE, |
| 577 | ADRENO_REG_CP_IB2_BASE_HI, |
| 578 | ADRENO_REG_CP_IB2_BUFSZ, |
| 579 | ADRENO_REG_CP_TIMESTAMP, |
| 580 | ADRENO_REG_CP_SCRATCH_REG6, |
| 581 | ADRENO_REG_CP_SCRATCH_REG7, |
| 582 | ADRENO_REG_CP_ME_RAM_RADDR, |
| 583 | ADRENO_REG_CP_ROQ_ADDR, |
| 584 | ADRENO_REG_CP_ROQ_DATA, |
| 585 | ADRENO_REG_CP_MERCIU_ADDR, |
| 586 | ADRENO_REG_CP_MERCIU_DATA, |
| 587 | ADRENO_REG_CP_MERCIU_DATA2, |
| 588 | ADRENO_REG_CP_MEQ_ADDR, |
| 589 | ADRENO_REG_CP_MEQ_DATA, |
| 590 | ADRENO_REG_CP_HW_FAULT, |
| 591 | ADRENO_REG_CP_PROTECT_STATUS, |
| 592 | ADRENO_REG_CP_PREEMPT, |
| 593 | ADRENO_REG_CP_PREEMPT_DEBUG, |
| 594 | ADRENO_REG_CP_PREEMPT_DISABLE, |
| 595 | ADRENO_REG_CP_PROTECT_REG_0, |
| 596 | ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO, |
| 597 | ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI, |
| 598 | ADRENO_REG_RBBM_STATUS, |
| 599 | ADRENO_REG_RBBM_STATUS3, |
| 600 | ADRENO_REG_RBBM_PERFCTR_CTL, |
| 601 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0, |
| 602 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD1, |
| 603 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD2, |
| 604 | ADRENO_REG_RBBM_PERFCTR_LOAD_CMD3, |
| 605 | ADRENO_REG_RBBM_PERFCTR_PWR_1_LO, |
| 606 | ADRENO_REG_RBBM_INT_0_MASK, |
| 607 | ADRENO_REG_RBBM_INT_0_STATUS, |
| 608 | ADRENO_REG_RBBM_PM_OVERRIDE2, |
| 609 | ADRENO_REG_RBBM_INT_CLEAR_CMD, |
| 610 | ADRENO_REG_RBBM_SW_RESET_CMD, |
| 611 | ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD, |
| 612 | ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2, |
| 613 | ADRENO_REG_RBBM_CLOCK_CTL, |
| 614 | ADRENO_REG_VPC_DEBUG_RAM_SEL, |
| 615 | ADRENO_REG_VPC_DEBUG_RAM_READ, |
| 616 | ADRENO_REG_PA_SC_AA_CONFIG, |
| 617 | ADRENO_REG_SQ_GPR_MANAGEMENT, |
| 618 | ADRENO_REG_SQ_INST_STORE_MANAGEMENT, |
| 619 | ADRENO_REG_TP0_CHICKEN, |
| 620 | ADRENO_REG_RBBM_RBBM_CTL, |
| 621 | ADRENO_REG_UCHE_INVALIDATE0, |
| 622 | ADRENO_REG_UCHE_INVALIDATE1, |
| 623 | ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO, |
| 624 | ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI, |
| 625 | ADRENO_REG_RBBM_SECVID_TRUST_CONTROL, |
| 626 | ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO, |
| 627 | ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI, |
| 628 | ADRENO_REG_RBBM_SECVID_TRUST_CONFIG, |
| 629 | ADRENO_REG_RBBM_SECVID_TSB_CONTROL, |
| 630 | ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE, |
| 631 | ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI, |
| 632 | ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE, |
| 633 | ADRENO_REG_VBIF_XIN_HALT_CTRL0, |
| 634 | ADRENO_REG_VBIF_XIN_HALT_CTRL1, |
| 635 | ADRENO_REG_VBIF_VERSION, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 636 | ADRENO_REG_GMU_AO_INTERRUPT_EN, |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 637 | ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, |
| 638 | ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS, |
| 639 | ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 640 | ADRENO_REG_GMU_PWR_COL_KEEPALIVE, |
| 641 | ADRENO_REG_GMU_AHB_FENCE_STATUS, |
| 642 | ADRENO_REG_GMU_RPMH_POWER_STATE, |
| 643 | ADRENO_REG_GMU_HFI_CTRL_STATUS, |
| 644 | ADRENO_REG_GMU_HFI_VERSION_INFO, |
| 645 | ADRENO_REG_GMU_HFI_SFR_ADDR, |
| 646 | ADRENO_REG_GMU_GMU2HOST_INTR_CLR, |
| 647 | ADRENO_REG_GMU_GMU2HOST_INTR_INFO, |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 648 | ADRENO_REG_GMU_GMU2HOST_INTR_MASK, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 649 | ADRENO_REG_GMU_HOST2GMU_INTR_SET, |
| 650 | ADRENO_REG_GMU_HOST2GMU_INTR_CLR, |
| 651 | ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO, |
George Shen | 6927d8f | 2017-07-19 11:38:10 -0700 | [diff] [blame] | 652 | ADRENO_REG_GMU_NMI_CONTROL_STATUS, |
| 653 | ADRENO_REG_GMU_CM3_CFG, |
Lynus Vaz | 76ecd06 | 2017-06-01 20:00:53 +0530 | [diff] [blame] | 654 | ADRENO_REG_GPMU_POWER_COUNTER_ENABLE, |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 655 | ADRENO_REG_REGISTER_MAX, |
| 656 | }; |
| 657 | |
| 658 | enum adreno_int_bits { |
| 659 | ADRENO_INT_RBBM_AHB_ERROR, |
| 660 | ADRENO_INT_BITS_MAX, |
| 661 | }; |
| 662 | |
| 663 | /** |
| 664 | * adreno_reg_offsets: Holds array of register offsets |
| 665 | * @offsets: Offset array of size defined by enum adreno_regs |
| 666 | * @offset_0: This is the index of the register in offset array whose value |
| 667 | * is 0. 0 is a valid register offset and during initialization of the |
| 668 | * offset array we need to know if an offset value is correctly defined to 0 |
| 669 | */ |
| 670 | struct adreno_reg_offsets { |
| 671 | unsigned int *const offsets; |
| 672 | enum adreno_regs offset_0; |
| 673 | }; |
| 674 | |
| 675 | #define ADRENO_REG_UNUSED 0xFFFFFFFF |
| 676 | #define ADRENO_REG_SKIP 0xFFFFFFFE |
| 677 | #define ADRENO_REG_DEFINE(_offset, _reg) [_offset] = _reg |
| 678 | #define ADRENO_INT_DEFINE(_offset, _val) ADRENO_REG_DEFINE(_offset, _val) |
| 679 | |
| 680 | /* |
| 681 | * struct adreno_vbif_data - Describes vbif register value pair |
| 682 | * @reg: Offset to vbif register |
| 683 | * @val: The value that should be programmed in the register at reg |
| 684 | */ |
| 685 | struct adreno_vbif_data { |
| 686 | unsigned int reg; |
| 687 | unsigned int val; |
| 688 | }; |
| 689 | |
| 690 | /* |
| 691 | * struct adreno_vbif_platform - Holds an array of vbif reg value pairs |
| 692 | * for a particular core |
| 693 | * @devfunc: Pointer to platform/core identification function |
| 694 | * @vbif: Array of reg value pairs for vbif registers |
| 695 | */ |
| 696 | struct adreno_vbif_platform { |
| 697 | int (*devfunc)(struct adreno_device *); |
| 698 | const struct adreno_vbif_data *vbif; |
| 699 | }; |
| 700 | |
| 701 | /* |
| 702 | * struct adreno_vbif_snapshot_registers - Holds an array of vbif registers |
| 703 | * listed for snapshot dump for a particular core |
| 704 | * @version: vbif version |
| 705 | * @mask: vbif revision mask |
| 706 | * @registers: vbif registers listed for snapshot dump |
| 707 | * @count: count of vbif registers listed for snapshot |
| 708 | */ |
| 709 | struct adreno_vbif_snapshot_registers { |
| 710 | const unsigned int version; |
| 711 | const unsigned int mask; |
| 712 | const unsigned int *registers; |
| 713 | const int count; |
| 714 | }; |
| 715 | |
| 716 | /** |
| 717 | * struct adreno_coresight_register - Definition for a coresight (tracebus) |
| 718 | * debug register |
| 719 | * @offset: Offset of the debug register in the KGSL mmio region |
| 720 | * @initial: Default value to write when coresight is enabled |
| 721 | * @value: Current shadow value of the register (to be reprogrammed after power |
| 722 | * collapse) |
| 723 | */ |
| 724 | struct adreno_coresight_register { |
| 725 | unsigned int offset; |
| 726 | unsigned int initial; |
| 727 | unsigned int value; |
| 728 | }; |
| 729 | |
| 730 | struct adreno_coresight_attr { |
| 731 | struct device_attribute attr; |
| 732 | struct adreno_coresight_register *reg; |
| 733 | }; |
| 734 | |
| 735 | ssize_t adreno_coresight_show_register(struct device *device, |
| 736 | struct device_attribute *attr, char *buf); |
| 737 | |
| 738 | ssize_t adreno_coresight_store_register(struct device *dev, |
| 739 | struct device_attribute *attr, const char *buf, size_t size); |
| 740 | |
| 741 | #define ADRENO_CORESIGHT_ATTR(_attrname, _reg) \ |
| 742 | struct adreno_coresight_attr coresight_attr_##_attrname = { \ |
| 743 | __ATTR(_attrname, 0644, \ |
| 744 | adreno_coresight_show_register, \ |
| 745 | adreno_coresight_store_register), \ |
| 746 | (_reg), } |
| 747 | |
| 748 | /** |
| 749 | * struct adreno_coresight - GPU specific coresight definition |
| 750 | * @registers - Array of GPU specific registers to configure trace bus output |
| 751 | * @count - Number of registers in the array |
| 752 | * @groups - Pointer to an attribute list of control files |
| 753 | * @atid - The unique ATID value of the coresight device |
| 754 | */ |
| 755 | struct adreno_coresight { |
| 756 | struct adreno_coresight_register *registers; |
| 757 | unsigned int count; |
| 758 | const struct attribute_group **groups; |
| 759 | unsigned int atid; |
| 760 | }; |
| 761 | |
| 762 | |
| 763 | struct adreno_irq_funcs { |
| 764 | void (*func)(struct adreno_device *, int); |
| 765 | }; |
| 766 | #define ADRENO_IRQ_CALLBACK(_c) { .func = _c } |
| 767 | |
| 768 | struct adreno_irq { |
| 769 | unsigned int mask; |
| 770 | struct adreno_irq_funcs *funcs; |
| 771 | }; |
| 772 | |
| 773 | /* |
| 774 | * struct adreno_debugbus_block - Holds info about debug buses of a chip |
| 775 | * @block_id: Bus identifier |
| 776 | * @dwords: Number of dwords of data that this block holds |
| 777 | */ |
| 778 | struct adreno_debugbus_block { |
| 779 | unsigned int block_id; |
| 780 | unsigned int dwords; |
| 781 | }; |
| 782 | |
| 783 | /* |
| 784 | * struct adreno_snapshot_section_sizes - Structure holding the size of |
| 785 | * different sections dumped during device snapshot |
| 786 | * @cp_pfp: CP PFP data section size |
| 787 | * @cp_me: CP ME data section size |
| 788 | * @vpc_mem: VPC memory section size |
| 789 | * @cp_meq: CP MEQ size |
| 790 | * @shader_mem: Size of shader memory of 1 shader section |
| 791 | * @cp_merciu: CP MERCIU size |
| 792 | * @roq: ROQ size |
| 793 | */ |
| 794 | struct adreno_snapshot_sizes { |
| 795 | int cp_pfp; |
| 796 | int cp_me; |
| 797 | int vpc_mem; |
| 798 | int cp_meq; |
| 799 | int shader_mem; |
| 800 | int cp_merciu; |
| 801 | int roq; |
| 802 | }; |
| 803 | |
| 804 | /* |
| 805 | * struct adreno_snapshot_data - Holds data used in snapshot |
| 806 | * @sect_sizes: Has sections sizes |
| 807 | */ |
| 808 | struct adreno_snapshot_data { |
| 809 | struct adreno_snapshot_sizes *sect_sizes; |
| 810 | }; |
| 811 | |
| 812 | struct adreno_gpudev { |
| 813 | /* |
| 814 | * These registers are in a different location on different devices, |
| 815 | * so define them in the structure and use them as variables. |
| 816 | */ |
| 817 | const struct adreno_reg_offsets *reg_offsets; |
| 818 | unsigned int *const int_bits; |
| 819 | const struct adreno_ft_perf_counters *ft_perf_counters; |
| 820 | unsigned int ft_perf_counters_count; |
| 821 | |
| 822 | struct adreno_perfcounters *perfcounters; |
| 823 | const struct adreno_invalid_countables *invalid_countables; |
| 824 | struct adreno_snapshot_data *snapshot_data; |
| 825 | |
| 826 | struct adreno_coresight *coresight; |
| 827 | |
| 828 | struct adreno_irq *irq; |
| 829 | int num_prio_levels; |
| 830 | unsigned int vbif_xin_halt_ctrl0_mask; |
| 831 | /* GPU specific function hooks */ |
| 832 | void (*irq_trace)(struct adreno_device *, unsigned int status); |
| 833 | void (*snapshot)(struct adreno_device *, struct kgsl_snapshot *); |
| 834 | void (*platform_setup)(struct adreno_device *); |
| 835 | void (*init)(struct adreno_device *); |
| 836 | void (*remove)(struct adreno_device *); |
| 837 | int (*rb_start)(struct adreno_device *, unsigned int start_type); |
| 838 | int (*microcode_read)(struct adreno_device *); |
| 839 | void (*perfcounter_init)(struct adreno_device *); |
| 840 | void (*perfcounter_close)(struct adreno_device *); |
| 841 | void (*start)(struct adreno_device *); |
| 842 | bool (*is_sptp_idle)(struct adreno_device *); |
| 843 | int (*regulator_enable)(struct adreno_device *); |
| 844 | void (*regulator_disable)(struct adreno_device *); |
| 845 | void (*pwrlevel_change_settings)(struct adreno_device *, |
| 846 | unsigned int prelevel, unsigned int postlevel, |
| 847 | bool post); |
| 848 | uint64_t (*read_throttling_counters)(struct adreno_device *); |
| 849 | void (*count_throttles)(struct adreno_device *, uint64_t adj); |
| 850 | int (*enable_pwr_counters)(struct adreno_device *, |
| 851 | unsigned int counter); |
| 852 | unsigned int (*preemption_pre_ibsubmit)( |
| 853 | struct adreno_device *adreno_dev, |
| 854 | struct adreno_ringbuffer *rb, |
| 855 | unsigned int *cmds, |
| 856 | struct kgsl_context *context); |
| 857 | int (*preemption_yield_enable)(unsigned int *); |
Harshdeep Dhatt | aae850c | 2017-08-21 17:19:26 -0600 | [diff] [blame] | 858 | unsigned int (*set_marker)(unsigned int *cmds, int start); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 859 | unsigned int (*preemption_post_ibsubmit)( |
| 860 | struct adreno_device *adreno_dev, |
| 861 | unsigned int *cmds); |
| 862 | int (*preemption_init)(struct adreno_device *); |
| 863 | void (*preemption_schedule)(struct adreno_device *); |
Harshdeep Dhatt | 2e42f12 | 2017-05-31 17:27:19 -0600 | [diff] [blame] | 864 | int (*preemption_context_init)(struct kgsl_context *); |
| 865 | void (*preemption_context_destroy)(struct kgsl_context *); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 866 | void (*enable_64bit)(struct adreno_device *); |
| 867 | void (*clk_set_options)(struct adreno_device *, |
Deepak Kumar | a309e0e | 2017-03-17 17:27:42 +0530 | [diff] [blame] | 868 | const char *, struct clk *, bool on); |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 869 | void (*llc_configure_gpu_scid)(struct adreno_device *adreno_dev); |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 870 | void (*llc_configure_gpuhtw_scid)(struct adreno_device *adreno_dev); |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 871 | void (*llc_enable_overrides)(struct adreno_device *adreno_dev); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 872 | void (*pre_reset)(struct adreno_device *); |
| 873 | int (*oob_set)(struct adreno_device *adreno_dev, unsigned int set_mask, |
| 874 | unsigned int check_mask, |
| 875 | unsigned int clear_mask); |
| 876 | void (*oob_clear)(struct adreno_device *adreno_dev, |
| 877 | unsigned int clear_mask); |
Carter Cooper | df7ba70 | 2017-03-20 11:28:04 -0600 | [diff] [blame] | 878 | void (*gpu_keepalive)(struct adreno_device *adreno_dev, |
| 879 | bool state); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 880 | int (*rpmh_gpu_pwrctrl)(struct adreno_device *, unsigned int ops, |
| 881 | unsigned int arg1, unsigned int arg2); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 882 | bool (*hw_isidle)(struct adreno_device *); |
| 883 | int (*wait_for_gmu_idle)(struct adreno_device *); |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 884 | const char *(*iommu_fault_block)(struct adreno_device *adreno_dev, |
| 885 | unsigned int fsynr1); |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 886 | int (*reset)(struct kgsl_device *, int fault); |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 887 | int (*soft_reset)(struct adreno_device *); |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 888 | bool (*gx_is_on)(struct adreno_device *); |
| 889 | bool (*sptprac_is_on)(struct adreno_device *); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 890 | }; |
| 891 | |
| 892 | /** |
| 893 | * enum kgsl_ft_policy_bits - KGSL fault tolerance policy bits |
| 894 | * @KGSL_FT_OFF: Disable fault detection (not used) |
| 895 | * @KGSL_FT_REPLAY: Replay the faulting command |
| 896 | * @KGSL_FT_SKIPIB: Skip the faulting indirect buffer |
| 897 | * @KGSL_FT_SKIPFRAME: Skip the frame containing the faulting IB |
| 898 | * @KGSL_FT_DISABLE: Tells the dispatcher to disable FT for the command obj |
| 899 | * @KGSL_FT_TEMP_DISABLE: Disables FT for all commands |
| 900 | * @KGSL_FT_THROTTLE: Disable the context if it faults too often |
| 901 | * @KGSL_FT_SKIPCMD: Skip the command containing the faulting IB |
| 902 | */ |
| 903 | enum kgsl_ft_policy_bits { |
| 904 | KGSL_FT_OFF = 0, |
| 905 | KGSL_FT_REPLAY = 1, |
| 906 | KGSL_FT_SKIPIB = 2, |
| 907 | KGSL_FT_SKIPFRAME = 3, |
| 908 | KGSL_FT_DISABLE = 4, |
| 909 | KGSL_FT_TEMP_DISABLE = 5, |
| 910 | KGSL_FT_THROTTLE = 6, |
| 911 | KGSL_FT_SKIPCMD = 7, |
| 912 | /* KGSL_FT_MAX_BITS is used to calculate the mask */ |
| 913 | KGSL_FT_MAX_BITS, |
| 914 | /* Internal bits - set during GFT */ |
| 915 | /* Skip the PM dump on replayed command obj's */ |
| 916 | KGSL_FT_SKIP_PMDUMP = 31, |
| 917 | }; |
| 918 | |
| 919 | #define KGSL_FT_POLICY_MASK GENMASK(KGSL_FT_MAX_BITS - 1, 0) |
| 920 | |
| 921 | #define KGSL_FT_DEFAULT_POLICY \ |
| 922 | (BIT(KGSL_FT_REPLAY) | \ |
| 923 | BIT(KGSL_FT_SKIPCMD) | \ |
| 924 | BIT(KGSL_FT_THROTTLE)) |
| 925 | |
| 926 | #define ADRENO_FT_TYPES \ |
| 927 | { BIT(KGSL_FT_OFF), "off" }, \ |
| 928 | { BIT(KGSL_FT_REPLAY), "replay" }, \ |
| 929 | { BIT(KGSL_FT_SKIPIB), "skipib" }, \ |
| 930 | { BIT(KGSL_FT_SKIPFRAME), "skipframe" }, \ |
| 931 | { BIT(KGSL_FT_DISABLE), "disable" }, \ |
| 932 | { BIT(KGSL_FT_TEMP_DISABLE), "temp" }, \ |
| 933 | { BIT(KGSL_FT_THROTTLE), "throttle"}, \ |
| 934 | { BIT(KGSL_FT_SKIPCMD), "skipcmd" } |
| 935 | |
| 936 | /** |
| 937 | * enum kgsl_ft_pagefault_policy_bits - KGSL pagefault policy bits |
| 938 | * @KGSL_FT_PAGEFAULT_INT_ENABLE: No longer used, but retained for compatibility |
| 939 | * @KGSL_FT_PAGEFAULT_GPUHALT_ENABLE: enable GPU halt on pagefaults |
| 940 | * @KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE: log one pagefault per page |
| 941 | * @KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT: log one pagefault per interrupt |
| 942 | */ |
| 943 | enum { |
| 944 | KGSL_FT_PAGEFAULT_INT_ENABLE = 0, |
| 945 | KGSL_FT_PAGEFAULT_GPUHALT_ENABLE = 1, |
| 946 | KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE = 2, |
| 947 | KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT = 3, |
| 948 | /* KGSL_FT_PAGEFAULT_MAX_BITS is used to calculate the mask */ |
| 949 | KGSL_FT_PAGEFAULT_MAX_BITS, |
| 950 | }; |
| 951 | |
| 952 | #define KGSL_FT_PAGEFAULT_MASK GENMASK(KGSL_FT_PAGEFAULT_MAX_BITS - 1, 0) |
| 953 | |
| 954 | #define KGSL_FT_PAGEFAULT_DEFAULT_POLICY 0 |
| 955 | |
| 956 | #define FOR_EACH_RINGBUFFER(_dev, _rb, _i) \ |
| 957 | for ((_i) = 0, (_rb) = &((_dev)->ringbuffers[0]); \ |
| 958 | (_i) < (_dev)->num_ringbuffers; \ |
| 959 | (_i)++, (_rb)++) |
| 960 | |
| 961 | struct adreno_ft_perf_counters { |
| 962 | unsigned int counter; |
| 963 | unsigned int countable; |
| 964 | }; |
| 965 | |
| 966 | extern unsigned int *adreno_ft_regs; |
| 967 | extern unsigned int adreno_ft_regs_num; |
| 968 | extern unsigned int *adreno_ft_regs_val; |
| 969 | |
| 970 | extern struct adreno_gpudev adreno_a3xx_gpudev; |
| 971 | extern struct adreno_gpudev adreno_a4xx_gpudev; |
| 972 | extern struct adreno_gpudev adreno_a5xx_gpudev; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 973 | extern struct adreno_gpudev adreno_a6xx_gpudev; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 974 | |
| 975 | extern int adreno_wake_nice; |
| 976 | extern unsigned int adreno_wake_timeout; |
| 977 | |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 978 | int adreno_start(struct kgsl_device *device, int priority); |
| 979 | int adreno_soft_reset(struct kgsl_device *device); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 980 | long adreno_ioctl(struct kgsl_device_private *dev_priv, |
| 981 | unsigned int cmd, unsigned long arg); |
| 982 | |
| 983 | long adreno_ioctl_helper(struct kgsl_device_private *dev_priv, |
| 984 | unsigned int cmd, unsigned long arg, |
| 985 | const struct kgsl_ioctl *cmds, int len); |
| 986 | |
Carter Cooper | 1d8f547 | 2017-03-15 15:01:09 -0600 | [diff] [blame] | 987 | int a5xx_critical_packet_submit(struct adreno_device *adreno_dev, |
| 988 | struct adreno_ringbuffer *rb); |
| 989 | int adreno_set_unsecured_mode(struct adreno_device *adreno_dev, |
| 990 | struct adreno_ringbuffer *rb); |
Carter Cooper | 8567af0 | 2017-03-15 14:22:03 -0600 | [diff] [blame] | 991 | void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str); |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 992 | int adreno_spin_idle(struct adreno_device *device, unsigned int timeout); |
| 993 | int adreno_idle(struct kgsl_device *device); |
| 994 | bool adreno_isidle(struct kgsl_device *device); |
| 995 | |
| 996 | int adreno_set_constraint(struct kgsl_device *device, |
| 997 | struct kgsl_context *context, |
| 998 | struct kgsl_device_constraint *constraint); |
| 999 | |
| 1000 | void adreno_shadermem_regread(struct kgsl_device *device, |
| 1001 | unsigned int offsetwords, |
| 1002 | unsigned int *value); |
| 1003 | |
| 1004 | void adreno_snapshot(struct kgsl_device *device, |
| 1005 | struct kgsl_snapshot *snapshot, |
| 1006 | struct kgsl_context *context); |
| 1007 | |
| 1008 | int adreno_reset(struct kgsl_device *device, int fault); |
| 1009 | |
| 1010 | void adreno_fault_skipcmd_detached(struct adreno_device *adreno_dev, |
| 1011 | struct adreno_context *drawctxt, |
| 1012 | struct kgsl_drawobj *drawobj); |
| 1013 | |
| 1014 | int adreno_coresight_init(struct adreno_device *adreno_dev); |
| 1015 | |
| 1016 | void adreno_coresight_start(struct adreno_device *adreno_dev); |
| 1017 | void adreno_coresight_stop(struct adreno_device *adreno_dev); |
| 1018 | |
| 1019 | void adreno_coresight_remove(struct adreno_device *adreno_dev); |
| 1020 | |
| 1021 | bool adreno_hw_isidle(struct adreno_device *adreno_dev); |
| 1022 | |
| 1023 | void adreno_fault_detect_start(struct adreno_device *adreno_dev); |
| 1024 | void adreno_fault_detect_stop(struct adreno_device *adreno_dev); |
| 1025 | |
| 1026 | void adreno_hang_int_callback(struct adreno_device *adreno_dev, int bit); |
| 1027 | void adreno_cp_callback(struct adreno_device *adreno_dev, int bit); |
| 1028 | |
| 1029 | int adreno_sysfs_init(struct adreno_device *adreno_dev); |
| 1030 | void adreno_sysfs_close(struct adreno_device *adreno_dev); |
| 1031 | |
| 1032 | void adreno_irqctrl(struct adreno_device *adreno_dev, int state); |
| 1033 | |
| 1034 | long adreno_ioctl_perfcounter_get(struct kgsl_device_private *dev_priv, |
| 1035 | unsigned int cmd, void *data); |
| 1036 | |
| 1037 | long adreno_ioctl_perfcounter_put(struct kgsl_device_private *dev_priv, |
| 1038 | unsigned int cmd, void *data); |
| 1039 | |
| 1040 | int adreno_efuse_map(struct adreno_device *adreno_dev); |
| 1041 | int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset, |
| 1042 | unsigned int *val); |
| 1043 | void adreno_efuse_unmap(struct adreno_device *adreno_dev); |
| 1044 | |
| 1045 | #define ADRENO_TARGET(_name, _id) \ |
| 1046 | static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \ |
| 1047 | { \ |
| 1048 | return (ADRENO_GPUREV(adreno_dev) == (_id)); \ |
| 1049 | } |
| 1050 | |
| 1051 | static inline int adreno_is_a3xx(struct adreno_device *adreno_dev) |
| 1052 | { |
| 1053 | return ((ADRENO_GPUREV(adreno_dev) >= 300) && |
| 1054 | (ADRENO_GPUREV(adreno_dev) < 400)); |
| 1055 | } |
| 1056 | |
| 1057 | ADRENO_TARGET(a304, ADRENO_REV_A304) |
| 1058 | ADRENO_TARGET(a305, ADRENO_REV_A305) |
| 1059 | ADRENO_TARGET(a305b, ADRENO_REV_A305B) |
| 1060 | ADRENO_TARGET(a305c, ADRENO_REV_A305C) |
| 1061 | ADRENO_TARGET(a306, ADRENO_REV_A306) |
| 1062 | ADRENO_TARGET(a306a, ADRENO_REV_A306A) |
| 1063 | ADRENO_TARGET(a310, ADRENO_REV_A310) |
| 1064 | ADRENO_TARGET(a320, ADRENO_REV_A320) |
| 1065 | ADRENO_TARGET(a330, ADRENO_REV_A330) |
| 1066 | |
| 1067 | static inline int adreno_is_a330v2(struct adreno_device *adreno_dev) |
| 1068 | { |
| 1069 | return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330) && |
| 1070 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0)); |
| 1071 | } |
| 1072 | |
| 1073 | static inline int adreno_is_a330v21(struct adreno_device *adreno_dev) |
| 1074 | { |
| 1075 | return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330) && |
| 1076 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0xF)); |
| 1077 | } |
| 1078 | |
| 1079 | static inline int adreno_is_a4xx(struct adreno_device *adreno_dev) |
| 1080 | { |
| 1081 | return ADRENO_GPUREV(adreno_dev) >= 400 && |
| 1082 | ADRENO_GPUREV(adreno_dev) < 500; |
| 1083 | } |
| 1084 | |
| 1085 | ADRENO_TARGET(a405, ADRENO_REV_A405); |
| 1086 | |
| 1087 | static inline int adreno_is_a405v2(struct adreno_device *adreno_dev) |
| 1088 | { |
| 1089 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A405) && |
| 1090 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0x10); |
| 1091 | } |
| 1092 | |
| 1093 | ADRENO_TARGET(a418, ADRENO_REV_A418) |
| 1094 | ADRENO_TARGET(a420, ADRENO_REV_A420) |
| 1095 | ADRENO_TARGET(a430, ADRENO_REV_A430) |
| 1096 | |
| 1097 | static inline int adreno_is_a430v2(struct adreno_device *adreno_dev) |
| 1098 | { |
| 1099 | return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A430) && |
| 1100 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1)); |
| 1101 | } |
| 1102 | |
| 1103 | static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) |
| 1104 | { |
| 1105 | return ADRENO_GPUREV(adreno_dev) >= 500 && |
| 1106 | ADRENO_GPUREV(adreno_dev) < 600; |
| 1107 | } |
| 1108 | |
| 1109 | ADRENO_TARGET(a505, ADRENO_REV_A505) |
| 1110 | ADRENO_TARGET(a506, ADRENO_REV_A506) |
Rajesh Kemisetti | aed6ec7 | 2017-02-06 09:37:00 +0530 | [diff] [blame] | 1111 | ADRENO_TARGET(a508, ADRENO_REV_A508) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1112 | ADRENO_TARGET(a510, ADRENO_REV_A510) |
| 1113 | ADRENO_TARGET(a512, ADRENO_REV_A512) |
| 1114 | ADRENO_TARGET(a530, ADRENO_REV_A530) |
| 1115 | ADRENO_TARGET(a540, ADRENO_REV_A540) |
| 1116 | |
| 1117 | static inline int adreno_is_a530v1(struct adreno_device *adreno_dev) |
| 1118 | { |
| 1119 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) && |
| 1120 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); |
| 1121 | } |
| 1122 | |
| 1123 | static inline int adreno_is_a530v2(struct adreno_device *adreno_dev) |
| 1124 | { |
| 1125 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) && |
| 1126 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); |
| 1127 | } |
| 1128 | |
| 1129 | static inline int adreno_is_a530v3(struct adreno_device *adreno_dev) |
| 1130 | { |
| 1131 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) && |
| 1132 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 2); |
| 1133 | } |
| 1134 | |
| 1135 | static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev) |
| 1136 | { |
| 1137 | return ADRENO_GPUREV(adreno_dev) >= 505 && |
| 1138 | ADRENO_GPUREV(adreno_dev) <= 506; |
| 1139 | } |
| 1140 | |
| 1141 | static inline int adreno_is_a540v1(struct adreno_device *adreno_dev) |
| 1142 | { |
| 1143 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) && |
| 1144 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); |
| 1145 | } |
| 1146 | |
| 1147 | static inline int adreno_is_a540v2(struct adreno_device *adreno_dev) |
| 1148 | { |
| 1149 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) && |
| 1150 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); |
| 1151 | } |
| 1152 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1153 | static inline int adreno_is_a6xx(struct adreno_device *adreno_dev) |
| 1154 | { |
| 1155 | return ADRENO_GPUREV(adreno_dev) >= 600 && |
| 1156 | ADRENO_GPUREV(adreno_dev) < 700; |
| 1157 | } |
| 1158 | |
Rajesh Kemisetti | 8d5cc6e | 2017-06-06 16:44:17 +0530 | [diff] [blame] | 1159 | ADRENO_TARGET(a615, ADRENO_REV_A615) |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1160 | ADRENO_TARGET(a630, ADRENO_REV_A630) |
| 1161 | |
Shrenuj Bansal | 397e589 | 2017-03-13 13:38:47 -0700 | [diff] [blame] | 1162 | static inline int adreno_is_a630v1(struct adreno_device *adreno_dev) |
| 1163 | { |
| 1164 | return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A630) && |
| 1165 | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); |
| 1166 | } |
| 1167 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1168 | /* |
| 1169 | * adreno_checkreg_off() - Checks the validity of a register enum |
| 1170 | * @adreno_dev: Pointer to adreno device |
| 1171 | * @offset_name: The register enum that is checked |
| 1172 | */ |
| 1173 | static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev, |
| 1174 | enum adreno_regs offset_name) |
| 1175 | { |
| 1176 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1177 | |
| 1178 | if (offset_name >= ADRENO_REG_REGISTER_MAX || |
| 1179 | gpudev->reg_offsets->offsets[offset_name] == ADRENO_REG_UNUSED) |
| 1180 | return false; |
| 1181 | |
| 1182 | /* |
| 1183 | * GPU register programming is kept common as much as possible |
| 1184 | * across the cores, Use ADRENO_REG_SKIP when certain register |
| 1185 | * programming needs to be skipped for certain GPU cores. |
| 1186 | * Example: Certain registers on a5xx like IB1_BASE are 64 bit. |
| 1187 | * Common programming programs 64bit register but upper 32 bits |
| 1188 | * are skipped in a4xx and a3xx using ADRENO_REG_SKIP. |
| 1189 | */ |
| 1190 | if (gpudev->reg_offsets->offsets[offset_name] == ADRENO_REG_SKIP) |
| 1191 | return false; |
| 1192 | |
| 1193 | return true; |
| 1194 | } |
| 1195 | |
| 1196 | /* |
| 1197 | * adreno_readreg() - Read a register by getting its offset from the |
| 1198 | * offset array defined in gpudev node |
| 1199 | * @adreno_dev: Pointer to the the adreno device |
| 1200 | * @offset_name: The register enum that is to be read |
| 1201 | * @val: Register value read is placed here |
| 1202 | */ |
| 1203 | static inline void adreno_readreg(struct adreno_device *adreno_dev, |
| 1204 | enum adreno_regs offset_name, unsigned int *val) |
| 1205 | { |
| 1206 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1207 | |
| 1208 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1209 | kgsl_regread(KGSL_DEVICE(adreno_dev), |
| 1210 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1211 | else |
| 1212 | *val = 0; |
| 1213 | } |
| 1214 | |
| 1215 | /* |
| 1216 | * adreno_writereg() - Write a register by getting its offset from the |
| 1217 | * offset array defined in gpudev node |
| 1218 | * @adreno_dev: Pointer to the the adreno device |
| 1219 | * @offset_name: The register enum that is to be written |
| 1220 | * @val: Value to write |
| 1221 | */ |
| 1222 | static inline void adreno_writereg(struct adreno_device *adreno_dev, |
| 1223 | enum adreno_regs offset_name, unsigned int val) |
| 1224 | { |
| 1225 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1226 | |
| 1227 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1228 | kgsl_regwrite(KGSL_DEVICE(adreno_dev), |
| 1229 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1230 | } |
| 1231 | |
| 1232 | /* |
| 1233 | * adreno_getreg() - Returns the offset value of a register from the |
| 1234 | * register offset array in the gpudev node |
| 1235 | * @adreno_dev: Pointer to the the adreno device |
| 1236 | * @offset_name: The register enum whore offset is returned |
| 1237 | */ |
| 1238 | static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev, |
| 1239 | enum adreno_regs offset_name) |
| 1240 | { |
| 1241 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1242 | |
| 1243 | if (!adreno_checkreg_off(adreno_dev, offset_name)) |
| 1244 | return ADRENO_REG_REGISTER_MAX; |
| 1245 | return gpudev->reg_offsets->offsets[offset_name]; |
| 1246 | } |
| 1247 | |
| 1248 | /* |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1249 | * adreno_read_gmureg() - Read a GMU register by getting its offset from the |
| 1250 | * offset array defined in gpudev node |
| 1251 | * @adreno_dev: Pointer to the the adreno device |
| 1252 | * @offset_name: The register enum that is to be read |
| 1253 | * @val: Register value read is placed here |
| 1254 | */ |
| 1255 | static inline void adreno_read_gmureg(struct adreno_device *adreno_dev, |
| 1256 | enum adreno_regs offset_name, unsigned int *val) |
| 1257 | { |
| 1258 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1259 | |
| 1260 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1261 | kgsl_gmu_regread(KGSL_DEVICE(adreno_dev), |
| 1262 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1263 | else |
Carter Cooper | 83454bf | 2017-03-20 11:26:04 -0600 | [diff] [blame] | 1264 | *val = 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1265 | } |
| 1266 | |
| 1267 | /* |
| 1268 | * adreno_write_gmureg() - Write a GMU register by getting its offset from the |
| 1269 | * offset array defined in gpudev node |
| 1270 | * @adreno_dev: Pointer to the the adreno device |
| 1271 | * @offset_name: The register enum that is to be written |
| 1272 | * @val: Value to write |
| 1273 | */ |
| 1274 | static inline void adreno_write_gmureg(struct adreno_device *adreno_dev, |
| 1275 | enum adreno_regs offset_name, unsigned int val) |
| 1276 | { |
| 1277 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1278 | |
| 1279 | if (adreno_checkreg_off(adreno_dev, offset_name)) |
| 1280 | kgsl_gmu_regwrite(KGSL_DEVICE(adreno_dev), |
| 1281 | gpudev->reg_offsets->offsets[offset_name], val); |
| 1282 | } |
| 1283 | |
| 1284 | /* |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1285 | * adreno_get_int() - Returns the offset value of an interrupt bit from |
| 1286 | * the interrupt bit array in the gpudev node |
| 1287 | * @adreno_dev: Pointer to the the adreno device |
| 1288 | * @bit_name: The interrupt bit enum whose bit is returned |
| 1289 | */ |
| 1290 | static inline unsigned int adreno_get_int(struct adreno_device *adreno_dev, |
| 1291 | enum adreno_int_bits bit_name) |
| 1292 | { |
| 1293 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1294 | |
| 1295 | if (bit_name >= ADRENO_INT_BITS_MAX) |
| 1296 | return -ERANGE; |
| 1297 | |
| 1298 | return gpudev->int_bits[bit_name]; |
| 1299 | } |
| 1300 | |
| 1301 | /** |
| 1302 | * adreno_gpu_fault() - Return the current state of the GPU |
| 1303 | * @adreno_dev: A pointer to the adreno_device to query |
| 1304 | * |
| 1305 | * Return 0 if there is no fault or positive with the last type of fault that |
| 1306 | * occurred |
| 1307 | */ |
| 1308 | static inline unsigned int adreno_gpu_fault(struct adreno_device *adreno_dev) |
| 1309 | { |
| 1310 | /* make sure we're reading the latest value */ |
| 1311 | smp_rmb(); |
| 1312 | return atomic_read(&adreno_dev->dispatcher.fault); |
| 1313 | } |
| 1314 | |
| 1315 | /** |
| 1316 | * adreno_set_gpu_fault() - Set the current fault status of the GPU |
| 1317 | * @adreno_dev: A pointer to the adreno_device to set |
| 1318 | * @state: fault state to set |
| 1319 | * |
| 1320 | */ |
| 1321 | static inline void adreno_set_gpu_fault(struct adreno_device *adreno_dev, |
| 1322 | int state) |
| 1323 | { |
| 1324 | /* only set the fault bit w/o overwriting other bits */ |
| 1325 | atomic_add(state, &adreno_dev->dispatcher.fault); |
| 1326 | |
| 1327 | /* make sure other CPUs see the update */ |
| 1328 | smp_wmb(); |
| 1329 | } |
| 1330 | |
| 1331 | |
| 1332 | /** |
| 1333 | * adreno_clear_gpu_fault() - Clear the GPU fault register |
| 1334 | * @adreno_dev: A pointer to an adreno_device structure |
| 1335 | * |
| 1336 | * Clear the GPU fault status for the adreno device |
| 1337 | */ |
| 1338 | |
| 1339 | static inline void adreno_clear_gpu_fault(struct adreno_device *adreno_dev) |
| 1340 | { |
| 1341 | atomic_set(&adreno_dev->dispatcher.fault, 0); |
| 1342 | |
| 1343 | /* make sure other CPUs see the update */ |
| 1344 | smp_wmb(); |
| 1345 | } |
| 1346 | |
| 1347 | /** |
| 1348 | * adreno_gpu_halt() - Return the GPU halt refcount |
| 1349 | * @adreno_dev: A pointer to the adreno_device |
| 1350 | */ |
| 1351 | static inline int adreno_gpu_halt(struct adreno_device *adreno_dev) |
| 1352 | { |
| 1353 | /* make sure we're reading the latest value */ |
| 1354 | smp_rmb(); |
| 1355 | return atomic_read(&adreno_dev->halt); |
| 1356 | } |
| 1357 | |
| 1358 | |
| 1359 | /** |
| 1360 | * adreno_clear_gpu_halt() - Clear the GPU halt refcount |
| 1361 | * @adreno_dev: A pointer to the adreno_device |
| 1362 | */ |
| 1363 | static inline void adreno_clear_gpu_halt(struct adreno_device *adreno_dev) |
| 1364 | { |
| 1365 | atomic_set(&adreno_dev->halt, 0); |
| 1366 | |
| 1367 | /* make sure other CPUs see the update */ |
| 1368 | smp_wmb(); |
| 1369 | } |
| 1370 | |
| 1371 | /** |
| 1372 | * adreno_get_gpu_halt() - Increment GPU halt refcount |
| 1373 | * @adreno_dev: A pointer to the adreno_device |
| 1374 | */ |
| 1375 | static inline void adreno_get_gpu_halt(struct adreno_device *adreno_dev) |
| 1376 | { |
| 1377 | atomic_inc(&adreno_dev->halt); |
| 1378 | } |
| 1379 | |
| 1380 | /** |
| 1381 | * adreno_put_gpu_halt() - Decrement GPU halt refcount |
| 1382 | * @adreno_dev: A pointer to the adreno_device |
| 1383 | */ |
| 1384 | static inline void adreno_put_gpu_halt(struct adreno_device *adreno_dev) |
| 1385 | { |
| 1386 | /* Make sure the refcount is good */ |
| 1387 | int ret = atomic_dec_if_positive(&adreno_dev->halt); |
| 1388 | |
| 1389 | WARN(ret < 0, "GPU halt refcount unbalanced\n"); |
| 1390 | } |
| 1391 | |
| 1392 | |
| 1393 | /* |
| 1394 | * adreno_vbif_start() - Program VBIF registers, called in device start |
| 1395 | * @adreno_dev: Pointer to device whose vbif data is to be programmed |
| 1396 | * @vbif_platforms: list register value pair of vbif for a family |
| 1397 | * of adreno cores |
| 1398 | * @num_platforms: Number of platforms contained in vbif_platforms |
| 1399 | */ |
| 1400 | static inline void adreno_vbif_start(struct adreno_device *adreno_dev, |
| 1401 | const struct adreno_vbif_platform *vbif_platforms, |
| 1402 | int num_platforms) |
| 1403 | { |
| 1404 | int i; |
| 1405 | const struct adreno_vbif_data *vbif = NULL; |
| 1406 | |
| 1407 | for (i = 0; i < num_platforms; i++) { |
| 1408 | if (vbif_platforms[i].devfunc(adreno_dev)) { |
| 1409 | vbif = vbif_platforms[i].vbif; |
| 1410 | break; |
| 1411 | } |
| 1412 | } |
| 1413 | |
| 1414 | while ((vbif != NULL) && (vbif->reg != 0)) { |
| 1415 | kgsl_regwrite(KGSL_DEVICE(adreno_dev), vbif->reg, vbif->val); |
| 1416 | vbif++; |
| 1417 | } |
| 1418 | } |
| 1419 | |
| 1420 | /** |
| 1421 | * adreno_set_protected_registers() - Protect the specified range of registers |
| 1422 | * from being accessed by the GPU |
| 1423 | * @adreno_dev: pointer to the Adreno device |
| 1424 | * @index: Pointer to the index of the protect mode register to write to |
| 1425 | * @reg: Starting dword register to write |
| 1426 | * @mask_len: Size of the mask to protect (# of registers = 2 ** mask_len) |
| 1427 | * |
| 1428 | * Add the range of registers to the list of protected mode registers that will |
| 1429 | * cause an exception if the GPU accesses them. There are 16 available |
| 1430 | * protected mode registers. Index is used to specify which register to write |
| 1431 | * to - the intent is to call this function multiple times with the same index |
| 1432 | * pointer for each range and the registers will be magically programmed in |
| 1433 | * incremental fashion |
| 1434 | */ |
| 1435 | static inline void adreno_set_protected_registers( |
| 1436 | struct adreno_device *adreno_dev, unsigned int *index, |
| 1437 | unsigned int reg, int mask_len) |
| 1438 | { |
| 1439 | unsigned int val; |
| 1440 | unsigned int base = |
| 1441 | adreno_getreg(adreno_dev, ADRENO_REG_CP_PROTECT_REG_0); |
| 1442 | unsigned int offset = *index; |
| 1443 | unsigned int max_slots = adreno_dev->gpucore->num_protected_regs ? |
| 1444 | adreno_dev->gpucore->num_protected_regs : 16; |
| 1445 | |
| 1446 | /* Do we have a free slot? */ |
| 1447 | if (WARN(*index >= max_slots, "Protected register slots full: %d/%d\n", |
| 1448 | *index, max_slots)) |
| 1449 | return; |
| 1450 | |
| 1451 | /* |
| 1452 | * On A4XX targets with more than 16 protected mode registers |
| 1453 | * the upper registers are not contiguous with the lower 16 |
| 1454 | * registers so we have to adjust the base and offset accordingly |
| 1455 | */ |
| 1456 | |
| 1457 | if (adreno_is_a4xx(adreno_dev) && *index >= 0x10) { |
| 1458 | base = A4XX_CP_PROTECT_REG_10; |
| 1459 | offset = *index - 0x10; |
| 1460 | } |
| 1461 | |
| 1462 | val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0xFFFFF); |
| 1463 | |
| 1464 | kgsl_regwrite(KGSL_DEVICE(adreno_dev), base + offset, val); |
| 1465 | *index = *index + 1; |
| 1466 | } |
| 1467 | |
| 1468 | #ifdef CONFIG_DEBUG_FS |
| 1469 | void adreno_debugfs_init(struct adreno_device *adreno_dev); |
| 1470 | void adreno_context_debugfs_init(struct adreno_device *adreno_dev, |
| 1471 | struct adreno_context *ctx); |
| 1472 | #else |
| 1473 | static inline void adreno_debugfs_init(struct adreno_device *adreno_dev) { } |
| 1474 | static inline void adreno_context_debugfs_init(struct adreno_device *device, |
| 1475 | struct adreno_context *context) |
| 1476 | { } |
| 1477 | #endif |
| 1478 | |
| 1479 | /** |
| 1480 | * adreno_compare_pm4_version() - Compare the PM4 microcode version |
| 1481 | * @adreno_dev: Pointer to the adreno_device struct |
| 1482 | * @version: Version number to compare again |
| 1483 | * |
| 1484 | * Compare the current version against the specified version and return -1 if |
| 1485 | * the current code is older, 0 if equal or 1 if newer. |
| 1486 | */ |
| 1487 | static inline int adreno_compare_pm4_version(struct adreno_device *adreno_dev, |
| 1488 | unsigned int version) |
| 1489 | { |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1490 | if (adreno_dev->fw[ADRENO_FW_PM4].version == version) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1491 | return 0; |
| 1492 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1493 | return (adreno_dev->fw[ADRENO_FW_PM4].version > version) ? 1 : -1; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1494 | } |
| 1495 | |
| 1496 | /** |
| 1497 | * adreno_compare_pfp_version() - Compare the PFP microcode version |
| 1498 | * @adreno_dev: Pointer to the adreno_device struct |
| 1499 | * @version: Version number to compare against |
| 1500 | * |
| 1501 | * Compare the current version against the specified version and return -1 if |
| 1502 | * the current code is older, 0 if equal or 1 if newer. |
| 1503 | */ |
| 1504 | static inline int adreno_compare_pfp_version(struct adreno_device *adreno_dev, |
| 1505 | unsigned int version) |
| 1506 | { |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1507 | if (adreno_dev->fw[ADRENO_FW_PFP].version == version) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1508 | return 0; |
| 1509 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1510 | return (adreno_dev->fw[ADRENO_FW_PFP].version > version) ? 1 : -1; |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1511 | } |
| 1512 | |
| 1513 | /* |
| 1514 | * adreno_bootstrap_ucode() - Checks if Ucode bootstrapping is supported |
| 1515 | * @adreno_dev: Pointer to the the adreno device |
| 1516 | */ |
| 1517 | static inline int adreno_bootstrap_ucode(struct adreno_device *adreno_dev) |
| 1518 | { |
| 1519 | return (ADRENO_FEATURE(adreno_dev, ADRENO_USE_BOOTSTRAP) && |
| 1520 | adreno_compare_pfp_version(adreno_dev, |
| 1521 | adreno_dev->gpucore->pfp_bstrp_ver) >= 0) ? 1 : 0; |
| 1522 | } |
| 1523 | |
| 1524 | /** |
| 1525 | * adreno_in_preempt_state() - Check if preemption state is equal to given state |
| 1526 | * @adreno_dev: Device whose preemption state is checked |
| 1527 | * @state: State to compare against |
| 1528 | */ |
| 1529 | static inline bool adreno_in_preempt_state(struct adreno_device *adreno_dev, |
| 1530 | enum adreno_preempt_states state) |
| 1531 | { |
| 1532 | return atomic_read(&adreno_dev->preempt.state) == state; |
| 1533 | } |
| 1534 | /** |
| 1535 | * adreno_set_preempt_state() - Set the specified preemption state |
| 1536 | * @adreno_dev: Device to change preemption state |
| 1537 | * @state: State to set |
| 1538 | */ |
| 1539 | static inline void adreno_set_preempt_state(struct adreno_device *adreno_dev, |
| 1540 | enum adreno_preempt_states state) |
| 1541 | { |
| 1542 | /* |
| 1543 | * atomic_set doesn't use barriers, so we need to do it ourselves. One |
| 1544 | * before... |
| 1545 | */ |
| 1546 | smp_wmb(); |
| 1547 | atomic_set(&adreno_dev->preempt.state, state); |
| 1548 | |
| 1549 | /* ... and one after */ |
| 1550 | smp_wmb(); |
| 1551 | } |
| 1552 | |
| 1553 | static inline bool adreno_is_preemption_enabled( |
| 1554 | struct adreno_device *adreno_dev) |
| 1555 | { |
| 1556 | return test_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv); |
| 1557 | } |
| 1558 | /** |
| 1559 | * adreno_ctx_get_rb() - Return the ringbuffer that a context should |
| 1560 | * use based on priority |
| 1561 | * @adreno_dev: The adreno device that context is using |
| 1562 | * @drawctxt: The context pointer |
| 1563 | */ |
| 1564 | static inline struct adreno_ringbuffer *adreno_ctx_get_rb( |
| 1565 | struct adreno_device *adreno_dev, |
| 1566 | struct adreno_context *drawctxt) |
| 1567 | { |
| 1568 | struct kgsl_context *context; |
| 1569 | int level; |
| 1570 | |
| 1571 | if (!drawctxt) |
| 1572 | return NULL; |
| 1573 | |
| 1574 | context = &(drawctxt->base); |
| 1575 | |
| 1576 | /* |
| 1577 | * If preemption is disabled then everybody needs to go on the same |
| 1578 | * ringbuffer |
| 1579 | */ |
| 1580 | |
| 1581 | if (!adreno_is_preemption_enabled(adreno_dev)) |
| 1582 | return &(adreno_dev->ringbuffers[0]); |
| 1583 | |
| 1584 | /* |
| 1585 | * Math to convert the priority field in context structure to an RB ID. |
| 1586 | * Divide up the context priority based on number of ringbuffer levels. |
| 1587 | */ |
| 1588 | level = context->priority / adreno_dev->num_ringbuffers; |
| 1589 | if (level < adreno_dev->num_ringbuffers) |
| 1590 | return &(adreno_dev->ringbuffers[level]); |
| 1591 | else |
| 1592 | return &(adreno_dev->ringbuffers[ |
| 1593 | adreno_dev->num_ringbuffers - 1]); |
| 1594 | } |
| 1595 | |
| 1596 | /* |
| 1597 | * adreno_compare_prio_level() - Compares 2 priority levels based on enum values |
| 1598 | * @p1: First priority level |
| 1599 | * @p2: Second priority level |
| 1600 | * |
| 1601 | * Returns greater than 0 if p1 is higher priority, 0 if levels are equal else |
| 1602 | * less than 0 |
| 1603 | */ |
| 1604 | static inline int adreno_compare_prio_level(int p1, int p2) |
| 1605 | { |
| 1606 | return p2 - p1; |
| 1607 | } |
| 1608 | |
| 1609 | void adreno_readreg64(struct adreno_device *adreno_dev, |
| 1610 | enum adreno_regs lo, enum adreno_regs hi, uint64_t *val); |
| 1611 | |
| 1612 | void adreno_writereg64(struct adreno_device *adreno_dev, |
| 1613 | enum adreno_regs lo, enum adreno_regs hi, uint64_t val); |
| 1614 | |
| 1615 | unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb); |
| 1616 | |
| 1617 | static inline bool adreno_rb_empty(struct adreno_ringbuffer *rb) |
| 1618 | { |
| 1619 | return (adreno_get_rptr(rb) == rb->wptr); |
| 1620 | } |
| 1621 | |
| 1622 | static inline bool adreno_soft_fault_detect(struct adreno_device *adreno_dev) |
| 1623 | { |
| 1624 | return adreno_dev->fast_hang_detect && |
| 1625 | !test_bit(ADRENO_DEVICE_ISDB_ENABLED, &adreno_dev->priv); |
| 1626 | } |
| 1627 | |
| 1628 | static inline bool adreno_long_ib_detect(struct adreno_device *adreno_dev) |
| 1629 | { |
| 1630 | return adreno_dev->long_ib_detect && |
| 1631 | !test_bit(ADRENO_DEVICE_ISDB_ENABLED, &adreno_dev->priv); |
| 1632 | } |
| 1633 | |
| 1634 | /* |
| 1635 | * adreno_support_64bit() - Check the feature flag only if it is in |
| 1636 | * 64bit kernel otherwise return false |
| 1637 | * adreno_dev: The adreno device |
| 1638 | */ |
| 1639 | #if BITS_PER_LONG == 64 |
| 1640 | static inline bool adreno_support_64bit(struct adreno_device *adreno_dev) |
| 1641 | { |
| 1642 | return ADRENO_FEATURE(adreno_dev, ADRENO_64BIT); |
| 1643 | } |
| 1644 | #else |
| 1645 | static inline bool adreno_support_64bit(struct adreno_device *adreno_dev) |
| 1646 | { |
| 1647 | return false; |
| 1648 | } |
| 1649 | #endif /*BITS_PER_LONG*/ |
| 1650 | |
| 1651 | static inline void adreno_ringbuffer_set_global( |
| 1652 | struct adreno_device *adreno_dev, int name) |
| 1653 | { |
| 1654 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1655 | |
| 1656 | kgsl_sharedmem_writel(device, |
| 1657 | &adreno_dev->ringbuffers[0].pagetable_desc, |
| 1658 | PT_INFO_OFFSET(current_global_ptname), name); |
| 1659 | } |
| 1660 | |
| 1661 | static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb, |
| 1662 | struct kgsl_pagetable *pt) |
| 1663 | { |
| 1664 | struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb); |
| 1665 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1666 | unsigned long flags; |
| 1667 | |
| 1668 | spin_lock_irqsave(&rb->preempt_lock, flags); |
| 1669 | |
| 1670 | kgsl_sharedmem_writel(device, &rb->pagetable_desc, |
| 1671 | PT_INFO_OFFSET(current_rb_ptname), pt->name); |
| 1672 | |
| 1673 | kgsl_sharedmem_writeq(device, &rb->pagetable_desc, |
| 1674 | PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt)); |
| 1675 | |
| 1676 | kgsl_sharedmem_writel(device, &rb->pagetable_desc, |
| 1677 | PT_INFO_OFFSET(contextidr), |
| 1678 | kgsl_mmu_pagetable_get_contextidr(pt)); |
| 1679 | |
| 1680 | spin_unlock_irqrestore(&rb->preempt_lock, flags); |
| 1681 | } |
| 1682 | |
| 1683 | static inline unsigned int counter_delta(struct kgsl_device *device, |
| 1684 | unsigned int reg, unsigned int *counter) |
| 1685 | { |
| 1686 | unsigned int val; |
| 1687 | unsigned int ret = 0; |
| 1688 | |
| 1689 | /* Read the value */ |
| 1690 | kgsl_regread(device, reg, &val); |
| 1691 | |
| 1692 | /* Return 0 for the first read */ |
| 1693 | if (*counter != 0) { |
| 1694 | if (val < *counter) |
| 1695 | ret = (0xFFFFFFFF - *counter) + val; |
| 1696 | else |
| 1697 | ret = val - *counter; |
| 1698 | } |
| 1699 | |
| 1700 | *counter = val; |
| 1701 | return ret; |
| 1702 | } |
Carter Cooper | 05f2a6b | 2017-03-20 11:43:11 -0600 | [diff] [blame] | 1703 | |
| 1704 | static inline int adreno_perfcntr_active_oob_get( |
| 1705 | struct adreno_device *adreno_dev) |
| 1706 | { |
| 1707 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1708 | int ret; |
| 1709 | |
| 1710 | ret = kgsl_active_count_get(KGSL_DEVICE(adreno_dev)); |
| 1711 | if (ret) |
| 1712 | return ret; |
| 1713 | |
| 1714 | if (gpudev->oob_set) { |
| 1715 | ret = gpudev->oob_set(adreno_dev, OOB_PERFCNTR_SET_MASK, |
| 1716 | OOB_PERFCNTR_CHECK_MASK, |
| 1717 | OOB_PERFCNTR_CLEAR_MASK); |
| 1718 | if (ret) |
| 1719 | kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); |
| 1720 | } |
| 1721 | |
| 1722 | return ret; |
| 1723 | } |
| 1724 | |
| 1725 | static inline void adreno_perfcntr_active_oob_put( |
| 1726 | struct adreno_device *adreno_dev) |
| 1727 | { |
| 1728 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1729 | |
| 1730 | if (gpudev->oob_clear) |
| 1731 | gpudev->oob_clear(adreno_dev, OOB_PERFCNTR_CLEAR_MASK); |
| 1732 | |
| 1733 | kgsl_active_count_put(KGSL_DEVICE(adreno_dev)); |
| 1734 | } |
| 1735 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1736 | /** |
| 1737 | * adreno_vbif_clear_pending_transactions() - Clear transactions in VBIF pipe |
| 1738 | * @device: Pointer to the device whose VBIF pipe is to be cleared |
| 1739 | */ |
| 1740 | static inline int adreno_vbif_clear_pending_transactions( |
| 1741 | struct kgsl_device *device) |
| 1742 | { |
| 1743 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1744 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 1745 | unsigned int mask = gpudev->vbif_xin_halt_ctrl0_mask; |
| 1746 | unsigned int val; |
| 1747 | unsigned long wait_for_vbif; |
| 1748 | int ret = 0; |
| 1749 | |
| 1750 | adreno_writereg(adreno_dev, ADRENO_REG_VBIF_XIN_HALT_CTRL0, mask); |
| 1751 | /* wait for the transactions to clear */ |
| 1752 | wait_for_vbif = jiffies + msecs_to_jiffies(100); |
| 1753 | while (1) { |
| 1754 | adreno_readreg(adreno_dev, |
| 1755 | ADRENO_REG_VBIF_XIN_HALT_CTRL1, &val); |
| 1756 | if ((val & mask) == mask) |
| 1757 | break; |
| 1758 | if (time_after(jiffies, wait_for_vbif)) { |
| 1759 | KGSL_DRV_ERR(device, |
| 1760 | "Wait limit reached for VBIF XIN Halt\n"); |
| 1761 | ret = -ETIMEDOUT; |
| 1762 | break; |
| 1763 | } |
| 1764 | } |
| 1765 | adreno_writereg(adreno_dev, ADRENO_REG_VBIF_XIN_HALT_CTRL0, 0); |
| 1766 | return ret; |
| 1767 | } |
| 1768 | |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1769 | #endif /*__ADRENO_H */ |