blob: b08b9e2c6a762da87530c5c6dfc736df4558a701 [file] [log] [blame]
Or Gerlitz69697b62016-07-01 14:50:55 +03001/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
37#include <linux/mlx5/fs.h>
38#include "mlx5_core.h"
39#include "eswitch.h"
40
Or Gerlitz10336652016-07-14 10:32:40 +030041enum {
42 FDB_FAST_PATH = 0,
43 FDB_SLOW_PATH
44};
45
Or Gerlitz3d80d1a2016-07-14 10:32:41 +030046struct mlx5_flow_rule *
47mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
48 struct mlx5_flow_spec *spec,
Or Gerlitz776b12b2016-09-22 20:01:45 +030049 struct mlx5_esw_flow_attr *attr)
Or Gerlitz3d80d1a2016-07-14 10:32:41 +030050{
51 struct mlx5_flow_destination dest = { 0 };
52 struct mlx5_fc *counter = NULL;
53 struct mlx5_flow_rule *rule;
54 void *misc;
Or Gerlitz776b12b2016-09-22 20:01:45 +030055 int action;
Or Gerlitz3d80d1a2016-07-14 10:32:41 +030056
57 if (esw->mode != SRIOV_OFFLOADS)
58 return ERR_PTR(-EOPNOTSUPP);
59
Or Gerlitzee39fbc2016-11-04 01:48:46 +020060 /* per flow vlan pop/push is emulated, don't set that into the firmware */
61 action = attr->action & ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH | MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
Or Gerlitz776b12b2016-09-22 20:01:45 +030062
Or Gerlitz3d80d1a2016-07-14 10:32:41 +030063 if (action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
64 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
Or Gerlitz776b12b2016-09-22 20:01:45 +030065 dest.vport_num = attr->out_rep->vport;
Or Gerlitz3d80d1a2016-07-14 10:32:41 +030066 action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
67 } else if (action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
68 counter = mlx5_fc_create(esw->dev, true);
69 if (IS_ERR(counter))
70 return ERR_CAST(counter);
71 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
72 dest.counter = counter;
73 }
74
75 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
Or Gerlitz776b12b2016-09-22 20:01:45 +030076 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
Or Gerlitz3d80d1a2016-07-14 10:32:41 +030077
78 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
79 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
80
81 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS |
82 MLX5_MATCH_MISC_PARAMETERS;
83
84 rule = mlx5_add_flow_rule((struct mlx5_flow_table *)esw->fdb_table.fdb,
85 spec, action, 0, &dest);
86
87 if (IS_ERR(rule))
88 mlx5_fc_destroy(esw->dev, counter);
89
90 return rule;
91}
92
Or Gerlitzf5f82472016-09-22 20:01:47 +030093static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
94{
95 struct mlx5_eswitch_rep *rep;
96 int vf_vport, err = 0;
97
98 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
99 for (vf_vport = 1; vf_vport < esw->enabled_vports; vf_vport++) {
100 rep = &esw->offloads.vport_reps[vf_vport];
101 if (!rep->valid)
102 continue;
103
104 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
105 if (err)
106 goto out;
107 }
108
109out:
110 return err;
111}
112
113static struct mlx5_eswitch_rep *
114esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
115{
116 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
117
118 in_rep = attr->in_rep;
119 out_rep = attr->out_rep;
120
121 if (push)
122 vport = in_rep;
123 else if (pop)
124 vport = out_rep;
125 else
126 vport = in_rep;
127
128 return vport;
129}
130
131static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
132 bool push, bool pop, bool fwd)
133{
134 struct mlx5_eswitch_rep *in_rep, *out_rep;
135
136 if ((push || pop) && !fwd)
137 goto out_notsupp;
138
139 in_rep = attr->in_rep;
140 out_rep = attr->out_rep;
141
142 if (push && in_rep->vport == FDB_UPLINK_VPORT)
143 goto out_notsupp;
144
145 if (pop && out_rep->vport == FDB_UPLINK_VPORT)
146 goto out_notsupp;
147
148 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
149 if (!push && !pop && fwd)
150 if (in_rep->vlan && out_rep->vport == FDB_UPLINK_VPORT)
151 goto out_notsupp;
152
153 /* protects against (1) setting rules with different vlans to push and
154 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
155 */
156 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan))
157 goto out_notsupp;
158
159 return 0;
160
161out_notsupp:
162 return -ENOTSUPP;
163}
164
165int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
166 struct mlx5_esw_flow_attr *attr)
167{
168 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
169 struct mlx5_eswitch_rep *vport = NULL;
170 bool push, pop, fwd;
171 int err = 0;
172
173 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
174 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
175 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
176
177 err = esw_add_vlan_action_check(attr, push, pop, fwd);
178 if (err)
179 return err;
180
181 attr->vlan_handled = false;
182
183 vport = esw_vlan_action_get_vport(attr, push, pop);
184
185 if (!push && !pop && fwd) {
186 /* tracks VF --> wire rules without vlan push action */
187 if (attr->out_rep->vport == FDB_UPLINK_VPORT) {
188 vport->vlan_refcount++;
189 attr->vlan_handled = true;
190 }
191
192 return 0;
193 }
194
195 if (!push && !pop)
196 return 0;
197
198 if (!(offloads->vlan_push_pop_refcount)) {
199 /* it's the 1st vlan rule, apply global vlan pop policy */
200 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
201 if (err)
202 goto out;
203 }
204 offloads->vlan_push_pop_refcount++;
205
206 if (push) {
207 if (vport->vlan_refcount)
208 goto skip_set_push;
209
210 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan, 0,
211 SET_VLAN_INSERT | SET_VLAN_STRIP);
212 if (err)
213 goto out;
214 vport->vlan = attr->vlan;
215skip_set_push:
216 vport->vlan_refcount++;
217 }
218out:
219 if (!err)
220 attr->vlan_handled = true;
221 return err;
222}
223
224int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
225 struct mlx5_esw_flow_attr *attr)
226{
227 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
228 struct mlx5_eswitch_rep *vport = NULL;
229 bool push, pop, fwd;
230 int err = 0;
231
232 if (!attr->vlan_handled)
233 return 0;
234
235 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
236 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
237 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
238
239 vport = esw_vlan_action_get_vport(attr, push, pop);
240
241 if (!push && !pop && fwd) {
242 /* tracks VF --> wire rules without vlan push action */
243 if (attr->out_rep->vport == FDB_UPLINK_VPORT)
244 vport->vlan_refcount--;
245
246 return 0;
247 }
248
249 if (push) {
250 vport->vlan_refcount--;
251 if (vport->vlan_refcount)
252 goto skip_unset_push;
253
254 vport->vlan = 0;
255 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
256 0, 0, SET_VLAN_STRIP);
257 if (err)
258 goto out;
259 }
260
261skip_unset_push:
262 offloads->vlan_push_pop_refcount--;
263 if (offloads->vlan_push_pop_refcount)
264 return 0;
265
266 /* no more vlan rules, stop global vlan pop policy */
267 err = esw_set_global_vlan_pop(esw, 0);
268
269out:
270 return err;
271}
272
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300273static struct mlx5_flow_rule *
Or Gerlitzab22be92016-07-01 14:50:57 +0300274mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, u32 sqn)
275{
276 struct mlx5_flow_destination dest;
277 struct mlx5_flow_rule *flow_rule;
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300278 struct mlx5_flow_spec *spec;
Or Gerlitzab22be92016-07-01 14:50:57 +0300279 void *misc;
280
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300281 spec = mlx5_vzalloc(sizeof(*spec));
282 if (!spec) {
Or Gerlitzab22be92016-07-01 14:50:57 +0300283 esw_warn(esw->dev, "FDB: Failed to alloc match parameters\n");
284 flow_rule = ERR_PTR(-ENOMEM);
285 goto out;
286 }
287
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300288 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
Or Gerlitzab22be92016-07-01 14:50:57 +0300289 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
290 MLX5_SET(fte_match_set_misc, misc, source_port, 0x0); /* source vport is 0 */
291
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300292 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
Or Gerlitzab22be92016-07-01 14:50:57 +0300293 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
294 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
295
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300296 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
Or Gerlitzab22be92016-07-01 14:50:57 +0300297 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
298 dest.vport_num = vport;
299
Or Gerlitz1a8ee6f2016-08-18 21:09:10 +0300300 flow_rule = mlx5_add_flow_rule(esw->fdb_table.offloads.fdb, spec,
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300301 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
Or Gerlitzab22be92016-07-01 14:50:57 +0300302 0, &dest);
303 if (IS_ERR(flow_rule))
304 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
305out:
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300306 kvfree(spec);
Or Gerlitzab22be92016-07-01 14:50:57 +0300307 return flow_rule;
308}
309
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300310void mlx5_eswitch_sqs2vport_stop(struct mlx5_eswitch *esw,
311 struct mlx5_eswitch_rep *rep)
312{
313 struct mlx5_esw_sq *esw_sq, *tmp;
314
315 if (esw->mode != SRIOV_OFFLOADS)
316 return;
317
318 list_for_each_entry_safe(esw_sq, tmp, &rep->vport_sqs_list, list) {
319 mlx5_del_flow_rule(esw_sq->send_to_vport_rule);
320 list_del(&esw_sq->list);
321 kfree(esw_sq);
322 }
323}
324
325int mlx5_eswitch_sqs2vport_start(struct mlx5_eswitch *esw,
326 struct mlx5_eswitch_rep *rep,
327 u16 *sqns_array, int sqns_num)
328{
329 struct mlx5_flow_rule *flow_rule;
330 struct mlx5_esw_sq *esw_sq;
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300331 int err;
332 int i;
333
334 if (esw->mode != SRIOV_OFFLOADS)
335 return 0;
336
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300337 for (i = 0; i < sqns_num; i++) {
338 esw_sq = kzalloc(sizeof(*esw_sq), GFP_KERNEL);
339 if (!esw_sq) {
340 err = -ENOMEM;
341 goto out_err;
342 }
343
344 /* Add re-inject rule to the PF/representor sqs */
345 flow_rule = mlx5_eswitch_add_send_to_vport_rule(esw,
Or Gerlitz9deb2242016-09-22 20:01:42 +0300346 rep->vport,
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300347 sqns_array[i]);
348 if (IS_ERR(flow_rule)) {
349 err = PTR_ERR(flow_rule);
350 kfree(esw_sq);
351 goto out_err;
352 }
353 esw_sq->send_to_vport_rule = flow_rule;
354 list_add(&esw_sq->list, &rep->vport_sqs_list);
355 }
356 return 0;
357
358out_err:
359 mlx5_eswitch_sqs2vport_stop(esw, rep);
360 return err;
361}
362
Or Gerlitz3aa33572016-07-01 14:50:56 +0300363static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
364{
365 struct mlx5_flow_destination dest;
366 struct mlx5_flow_rule *flow_rule = NULL;
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300367 struct mlx5_flow_spec *spec;
Or Gerlitz3aa33572016-07-01 14:50:56 +0300368 int err = 0;
369
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300370 spec = mlx5_vzalloc(sizeof(*spec));
371 if (!spec) {
Or Gerlitz3aa33572016-07-01 14:50:56 +0300372 esw_warn(esw->dev, "FDB: Failed to alloc match parameters\n");
373 err = -ENOMEM;
374 goto out;
375 }
376
377 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
378 dest.vport_num = 0;
379
Or Gerlitz10336652016-07-14 10:32:40 +0300380 flow_rule = mlx5_add_flow_rule(esw->fdb_table.offloads.fdb, spec,
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300381 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
382 0, &dest);
Or Gerlitz3aa33572016-07-01 14:50:56 +0300383 if (IS_ERR(flow_rule)) {
384 err = PTR_ERR(flow_rule);
385 esw_warn(esw->dev, "FDB: Failed to add miss flow rule err %d\n", err);
386 goto out;
387 }
388
389 esw->fdb_table.offloads.miss_rule = flow_rule;
390out:
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300391 kvfree(spec);
Or Gerlitz3aa33572016-07-01 14:50:56 +0300392 return err;
393}
394
Or Gerlitz69697b62016-07-01 14:50:55 +0300395#define MAX_PF_SQ 256
Or Gerlitz10336652016-07-14 10:32:40 +0300396#define ESW_OFFLOADS_NUM_ENTRIES (1 << 13) /* 8K */
397#define ESW_OFFLOADS_NUM_GROUPS 4
Or Gerlitz69697b62016-07-01 14:50:55 +0300398
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300399static int esw_create_offloads_fdb_table(struct mlx5_eswitch *esw, int nvports)
Or Gerlitz69697b62016-07-01 14:50:55 +0300400{
401 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
402 struct mlx5_core_dev *dev = esw->dev;
403 struct mlx5_flow_namespace *root_ns;
404 struct mlx5_flow_table *fdb = NULL;
405 struct mlx5_flow_group *g;
406 u32 *flow_group_in;
407 void *match_criteria;
408 int table_size, ix, err = 0;
409
410 flow_group_in = mlx5_vzalloc(inlen);
411 if (!flow_group_in)
412 return -ENOMEM;
413
414 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
415 if (!root_ns) {
416 esw_warn(dev, "Failed to get FDB flow namespace\n");
Or Gerlitzb445ecb2017-01-11 19:39:42 +0200417 err = -EOPNOTSUPP;
Or Gerlitz69697b62016-07-01 14:50:55 +0300418 goto ns_err;
419 }
420
421 esw_debug(dev, "Create offloads FDB table, log_max_size(%d)\n",
422 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
423
Or Gerlitz10336652016-07-14 10:32:40 +0300424 fdb = mlx5_create_auto_grouped_flow_table(root_ns, FDB_FAST_PATH,
425 ESW_OFFLOADS_NUM_ENTRIES,
426 ESW_OFFLOADS_NUM_GROUPS, 0);
Or Gerlitz69697b62016-07-01 14:50:55 +0300427 if (IS_ERR(fdb)) {
428 err = PTR_ERR(fdb);
Or Gerlitz10336652016-07-14 10:32:40 +0300429 esw_warn(dev, "Failed to create Fast path FDB Table err %d\n", err);
430 goto fast_fdb_err;
Or Gerlitz69697b62016-07-01 14:50:55 +0300431 }
432 esw->fdb_table.fdb = fdb;
433
Or Gerlitz10336652016-07-14 10:32:40 +0300434 table_size = nvports + MAX_PF_SQ + 1;
435 fdb = mlx5_create_flow_table(root_ns, FDB_SLOW_PATH, table_size, 0);
436 if (IS_ERR(fdb)) {
437 err = PTR_ERR(fdb);
438 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
439 goto slow_fdb_err;
440 }
441 esw->fdb_table.offloads.fdb = fdb;
442
Or Gerlitz69697b62016-07-01 14:50:55 +0300443 /* create send-to-vport group */
444 memset(flow_group_in, 0, inlen);
445 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
446 MLX5_MATCH_MISC_PARAMETERS);
447
448 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
449
450 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
451 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
452
453 ix = nvports + MAX_PF_SQ;
454 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
455 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
456
457 g = mlx5_create_flow_group(fdb, flow_group_in);
458 if (IS_ERR(g)) {
459 err = PTR_ERR(g);
460 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
461 goto send_vport_err;
462 }
463 esw->fdb_table.offloads.send_to_vport_grp = g;
464
465 /* create miss group */
466 memset(flow_group_in, 0, inlen);
467 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, 0);
468
469 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
470 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix + 1);
471
472 g = mlx5_create_flow_group(fdb, flow_group_in);
473 if (IS_ERR(g)) {
474 err = PTR_ERR(g);
475 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
476 goto miss_err;
477 }
478 esw->fdb_table.offloads.miss_grp = g;
479
Or Gerlitz3aa33572016-07-01 14:50:56 +0300480 err = esw_add_fdb_miss_rule(esw);
481 if (err)
482 goto miss_rule_err;
483
Or Gerlitz69697b62016-07-01 14:50:55 +0300484 return 0;
485
Or Gerlitz3aa33572016-07-01 14:50:56 +0300486miss_rule_err:
487 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
Or Gerlitz69697b62016-07-01 14:50:55 +0300488miss_err:
489 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
490send_vport_err:
Or Gerlitz10336652016-07-14 10:32:40 +0300491 mlx5_destroy_flow_table(esw->fdb_table.offloads.fdb);
492slow_fdb_err:
493 mlx5_destroy_flow_table(esw->fdb_table.fdb);
494fast_fdb_err:
Or Gerlitz69697b62016-07-01 14:50:55 +0300495ns_err:
496 kvfree(flow_group_in);
497 return err;
498}
499
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300500static void esw_destroy_offloads_fdb_table(struct mlx5_eswitch *esw)
Or Gerlitz69697b62016-07-01 14:50:55 +0300501{
502 if (!esw->fdb_table.fdb)
503 return;
504
505 esw_debug(esw->dev, "Destroy offloads FDB Table\n");
Or Gerlitz3aa33572016-07-01 14:50:56 +0300506 mlx5_del_flow_rule(esw->fdb_table.offloads.miss_rule);
Or Gerlitz69697b62016-07-01 14:50:55 +0300507 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
508 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
509
Or Gerlitz10336652016-07-14 10:32:40 +0300510 mlx5_destroy_flow_table(esw->fdb_table.offloads.fdb);
Or Gerlitz69697b62016-07-01 14:50:55 +0300511 mlx5_destroy_flow_table(esw->fdb_table.fdb);
512}
Or Gerlitzc116c6e2016-07-01 14:50:59 +0300513
514static int esw_create_offloads_table(struct mlx5_eswitch *esw)
515{
516 struct mlx5_flow_namespace *ns;
517 struct mlx5_flow_table *ft_offloads;
518 struct mlx5_core_dev *dev = esw->dev;
519 int err = 0;
520
521 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
522 if (!ns) {
523 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
Or Gerlitz40385242017-01-12 13:04:01 +0200524 return -EOPNOTSUPP;
Or Gerlitzc116c6e2016-07-01 14:50:59 +0300525 }
526
527 ft_offloads = mlx5_create_flow_table(ns, 0, dev->priv.sriov.num_vfs + 2, 0);
528 if (IS_ERR(ft_offloads)) {
529 err = PTR_ERR(ft_offloads);
530 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
531 return err;
532 }
533
534 esw->offloads.ft_offloads = ft_offloads;
535 return 0;
536}
537
538static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
539{
540 struct mlx5_esw_offload *offloads = &esw->offloads;
541
542 mlx5_destroy_flow_table(offloads->ft_offloads);
543}
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300544
545static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
546{
547 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
548 struct mlx5_flow_group *g;
549 struct mlx5_priv *priv = &esw->dev->priv;
550 u32 *flow_group_in;
551 void *match_criteria, *misc;
552 int err = 0;
553 int nvports = priv->sriov.num_vfs + 2;
554
555 flow_group_in = mlx5_vzalloc(inlen);
556 if (!flow_group_in)
557 return -ENOMEM;
558
559 /* create vport rx group */
560 memset(flow_group_in, 0, inlen);
561 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
562 MLX5_MATCH_MISC_PARAMETERS);
563
564 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
565 misc = MLX5_ADDR_OF(fte_match_param, match_criteria, misc_parameters);
566 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
567
568 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
569 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
570
571 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
572
573 if (IS_ERR(g)) {
574 err = PTR_ERR(g);
575 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
576 goto out;
577 }
578
579 esw->offloads.vport_rx_group = g;
580out:
581 kfree(flow_group_in);
582 return err;
583}
584
585static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
586{
587 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
588}
589
590struct mlx5_flow_rule *
591mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn)
592{
593 struct mlx5_flow_destination dest;
594 struct mlx5_flow_rule *flow_rule;
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300595 struct mlx5_flow_spec *spec;
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300596 void *misc;
597
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300598 spec = mlx5_vzalloc(sizeof(*spec));
599 if (!spec) {
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300600 esw_warn(esw->dev, "Failed to alloc match parameters\n");
601 flow_rule = ERR_PTR(-ENOMEM);
602 goto out;
603 }
604
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300605 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300606 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
607
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300608 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300609 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
610
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300611 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300612 dest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
613 dest.tir_num = tirn;
614
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300615 flow_rule = mlx5_add_flow_rule(esw->offloads.ft_offloads, spec,
616 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300617 0, &dest);
618 if (IS_ERR(flow_rule)) {
619 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
620 goto out;
621 }
622
623out:
Maor Gottliebc5bb1732016-07-04 17:23:05 +0300624 kvfree(spec);
Or Gerlitzfed9ce22016-07-01 14:51:00 +0300625 return flow_rule;
626}
Or Gerlitzfeae9082016-07-01 14:51:02 +0300627
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300628static int esw_offloads_start(struct mlx5_eswitch *esw)
629{
Or Gerlitz6c419ba2016-09-18 18:20:29 +0300630 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300631
632 if (esw->mode != SRIOV_LEGACY) {
633 esw_warn(esw->dev, "Can't set offloads mode, SRIOV legacy not enabled\n");
634 return -EINVAL;
635 }
636
637 mlx5_eswitch_disable_sriov(esw);
638 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
Or Gerlitz6c419ba2016-09-18 18:20:29 +0300639 if (err) {
640 esw_warn(esw->dev, "Failed setting eswitch to offloads, err %d\n", err);
641 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
642 if (err1)
Or Gerlitzb445ecb2017-01-11 19:39:42 +0200643 esw_warn(esw->dev, "Failed setting eswitch back to legacy, err %d\n", err1);
Or Gerlitz6c419ba2016-09-18 18:20:29 +0300644 }
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300645 return err;
646}
647
648int esw_offloads_init(struct mlx5_eswitch *esw, int nvports)
649{
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300650 struct mlx5_eswitch_rep *rep;
651 int vport;
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300652 int err;
653
654 err = esw_create_offloads_fdb_table(esw, nvports);
655 if (err)
656 return err;
657
658 err = esw_create_offloads_table(esw);
659 if (err)
660 goto create_ft_err;
661
662 err = esw_create_vport_rx_group(esw);
663 if (err)
664 goto create_fg_err;
665
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300666 for (vport = 0; vport < nvports; vport++) {
667 rep = &esw->offloads.vport_reps[vport];
668 if (!rep->valid)
669 continue;
670
671 err = rep->load(esw, rep);
672 if (err)
673 goto err_reps;
674 }
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300675 return 0;
676
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300677err_reps:
678 for (vport--; vport >= 0; vport--) {
679 rep = &esw->offloads.vport_reps[vport];
680 if (!rep->valid)
681 continue;
682 rep->unload(esw, rep);
683 }
684 esw_destroy_vport_rx_group(esw);
685
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300686create_fg_err:
687 esw_destroy_offloads_table(esw);
688
689create_ft_err:
690 esw_destroy_offloads_fdb_table(esw);
691 return err;
692}
693
694static int esw_offloads_stop(struct mlx5_eswitch *esw)
695{
Or Gerlitz6c419ba2016-09-18 18:20:29 +0300696 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300697
698 mlx5_eswitch_disable_sriov(esw);
699 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
Or Gerlitz6c419ba2016-09-18 18:20:29 +0300700 if (err) {
701 esw_warn(esw->dev, "Failed setting eswitch to legacy, err %d\n", err);
702 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
703 if (err1)
704 esw_warn(esw->dev, "Failed setting eswitch back to offloads, err %d\n", err);
705 }
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300706
707 return err;
708}
709
710void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports)
711{
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300712 struct mlx5_eswitch_rep *rep;
713 int vport;
714
715 for (vport = 0; vport < nvports; vport++) {
716 rep = &esw->offloads.vport_reps[vport];
717 if (!rep->valid)
718 continue;
719 rep->unload(esw, rep);
720 }
721
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300722 esw_destroy_vport_rx_group(esw);
723 esw_destroy_offloads_table(esw);
724 esw_destroy_offloads_fdb_table(esw);
725}
726
Or Gerlitzef786182016-08-18 21:09:09 +0300727static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300728{
729 switch (mode) {
730 case DEVLINK_ESWITCH_MODE_LEGACY:
731 *mlx5_mode = SRIOV_LEGACY;
732 break;
733 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
734 *mlx5_mode = SRIOV_OFFLOADS;
735 break;
736 default:
737 return -EINVAL;
738 }
739
740 return 0;
741}
742
Or Gerlitzef786182016-08-18 21:09:09 +0300743static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
744{
745 switch (mlx5_mode) {
746 case SRIOV_LEGACY:
747 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
748 break;
749 case SRIOV_OFFLOADS:
750 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
751 break;
752 default:
753 return -EINVAL;
754 }
755
756 return 0;
757}
758
Or Gerlitzfeae9082016-07-01 14:51:02 +0300759int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode)
760{
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300761 struct mlx5_core_dev *dev;
762 u16 cur_mlx5_mode, mlx5_mode = 0;
763
764 dev = devlink_priv(devlink);
765
766 if (!MLX5_CAP_GEN(dev, vport_group_manager))
767 return -EOPNOTSUPP;
768
769 cur_mlx5_mode = dev->priv.eswitch->mode;
770
771 if (cur_mlx5_mode == SRIOV_NONE)
772 return -EOPNOTSUPP;
773
Or Gerlitzef786182016-08-18 21:09:09 +0300774 if (esw_mode_from_devlink(mode, &mlx5_mode))
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300775 return -EINVAL;
776
777 if (cur_mlx5_mode == mlx5_mode)
778 return 0;
779
780 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
781 return esw_offloads_start(dev->priv.eswitch);
782 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
783 return esw_offloads_stop(dev->priv.eswitch);
784 else
785 return -EINVAL;
Or Gerlitzfeae9082016-07-01 14:51:02 +0300786}
787
788int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
789{
Or Gerlitzc930a3a2016-07-01 14:51:03 +0300790 struct mlx5_core_dev *dev;
791
792 dev = devlink_priv(devlink);
793
794 if (!MLX5_CAP_GEN(dev, vport_group_manager))
795 return -EOPNOTSUPP;
796
797 if (dev->priv.eswitch->mode == SRIOV_NONE)
798 return -EOPNOTSUPP;
799
Or Gerlitzef786182016-08-18 21:09:09 +0300800 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
Or Gerlitzfeae9082016-07-01 14:51:02 +0300801}
Hadar Hen Zion127ea382016-07-01 14:51:08 +0300802
803void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
Or Gerlitz9deb2242016-09-22 20:01:42 +0300804 int vport_index,
805 struct mlx5_eswitch_rep *__rep)
Hadar Hen Zion127ea382016-07-01 14:51:08 +0300806{
807 struct mlx5_esw_offload *offloads = &esw->offloads;
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300808 struct mlx5_eswitch_rep *rep;
809
Or Gerlitz9deb2242016-09-22 20:01:42 +0300810 rep = &offloads->vport_reps[vport_index];
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300811
Or Gerlitzbac9b6a2016-09-22 20:01:43 +0300812 memset(rep, 0, sizeof(*rep));
813
814 rep->load = __rep->load;
815 rep->unload = __rep->unload;
816 rep->vport = __rep->vport;
817 rep->priv_data = __rep->priv_data;
818 ether_addr_copy(rep->hw_id, __rep->hw_id);
Or Gerlitz9deb2242016-09-22 20:01:42 +0300819
820 INIT_LIST_HEAD(&rep->vport_sqs_list);
821 rep->valid = true;
822}
823
824void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
825 int vport_index)
826{
827 struct mlx5_esw_offload *offloads = &esw->offloads;
828 struct mlx5_eswitch_rep *rep;
829
830 rep = &offloads->vport_reps[vport_index];
831
832 if (esw->mode == SRIOV_OFFLOADS && esw->vports[vport_index].enabled)
Hadar Hen Zioncb67b832016-07-01 14:51:09 +0300833 rep->unload(esw, rep);
Hadar Hen Zion127ea382016-07-01 14:51:08 +0300834
Or Gerlitz9deb2242016-09-22 20:01:42 +0300835 rep->valid = false;
Hadar Hen Zion127ea382016-07-01 14:51:08 +0300836}