blob: 20f84bbaa9bbc7c1f5cfe1fbadf532c8f10947d1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/tlb-v6.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ARM architecture version 6 TLB handling functions.
11 * These assume a split I/D TLB.
12 */
13#include <linux/linkage.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020014#include <asm/asm-offsets.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <asm/page.h>
16#include <asm/tlbflush.h>
17#include "proc-macros.S"
18
19#define HARVARD_TLB
20
21/*
22 * v6wbi_flush_user_tlb_range(start, end, vma)
23 *
24 * Invalidate a range of TLB entries in the specified address space.
25 *
26 * - start - start address (may not be aligned)
27 * - end - end address (exclusive, may not be aligned)
28 * - vma - vma_struct describing address range
29 *
30 * It is assumed that:
31 * - the "Invalidate single entry" instruction will invalidate
32 * both the I and the D TLBs on Harvard-style TLBs
33 */
34ENTRY(v6wbi_flush_user_tlb_range)
35 vma_vm_mm r3, r2 @ get vma->vm_mm
36 mov ip, #0
37 mmid r3, r3 @ get vm_mm->context.id
38 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
39 mov r0, r0, lsr #PAGE_SHIFT @ align address
40 mov r1, r1, lsr #PAGE_SHIFT
41 asid r3, r3 @ mask ASID
42 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
43 mov r1, r1, lsl #PAGE_SHIFT
44 vma_vm_flags r2, r2 @ get vma->vm_flags
451:
46#ifdef HARVARD_TLB
47 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
48 tst r2, #VM_EXEC @ Executable area ?
49 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
50#else
51 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
52#endif
53 add r0, r0, #PAGE_SZ
54 cmp r0, r1
55 blo 1b
Catalin Marinase6a5d662007-02-05 14:47:51 +010056 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 mov pc, lr
59
60/*
61 * v6wbi_flush_kern_tlb_range(start,end)
62 *
63 * Invalidate a range of kernel TLB entries
64 *
65 * - start - start address (may not be aligned)
66 * - end - end address (exclusive, may not be aligned)
67 */
68ENTRY(v6wbi_flush_kern_tlb_range)
69 mov r2, #0
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
71 mov r0, r0, lsr #PAGE_SHIFT @ align address
72 mov r1, r1, lsr #PAGE_SHIFT
73 mov r0, r0, lsl #PAGE_SHIFT
74 mov r1, r1, lsl #PAGE_SHIFT
751:
76#ifdef HARVARD_TLB
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
79#else
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
81#endif
82 add r0, r0, #PAGE_SZ
83 cmp r0, r1
84 blo 1b
Catalin Marinase6a5d662007-02-05 14:47:51 +010085 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
Catalin Marinas6a0e2432006-03-07 14:42:27 +000086 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
Catalin Marinase6a5d662007-02-05 14:47:51 +010087 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 mov pc, lr
89
90 .section ".text.init", #alloc, #execinstr
91
92 .type v6wbi_tlb_fns, #object
93ENTRY(v6wbi_tlb_fns)
94 .long v6wbi_flush_user_tlb_range
95 .long v6wbi_flush_kern_tlb_range
96 .long v6wbi_tlb_flags
97 .size v6wbi_tlb_fns, . - v6wbi_tlb_fns