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Catalin Marinas2ccdd1e2007-05-18 11:25:31 +01001/*
2 * linux/arch/arm/mm/tlb-v7.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 * Modified for ARMv7 by Catalin Marinas
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * ARM architecture version 6 TLB handling functions.
12 * These assume a split I/D TLB.
13 */
14#include <linux/linkage.h>
15#include <asm/asm-offsets.h>
16#include <asm/page.h>
17#include <asm/tlbflush.h>
18#include "proc-macros.S"
19
20/*
21 * v7wbi_flush_user_tlb_range(start, end, vma)
22 *
23 * Invalidate a range of TLB entries in the specified address space.
24 *
25 * - start - start address (may not be aligned)
26 * - end - end address (exclusive, may not be aligned)
27 * - vma - vma_struct describing address range
28 *
29 * It is assumed that:
30 * - the "Invalidate single entry" instruction will invalidate
31 * both the I and the D TLBs on Harvard-style TLBs
32 */
33ENTRY(v7wbi_flush_user_tlb_range)
34 vma_vm_mm r3, r2 @ get vma->vm_mm
35 mmid r3, r3 @ get vm_mm->context.id
36 dsb
37 mov r0, r0, lsr #PAGE_SHIFT @ align address
38 mov r1, r1, lsr #PAGE_SHIFT
39 asid r3, r3 @ mask ASID
40 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
41 mov r1, r1, lsl #PAGE_SHIFT
42 vma_vm_flags r2, r2 @ get vma->vm_flags
431:
44 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
45 tst r2, #VM_EXEC @ Executable area ?
46 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
47 add r0, r0, #PAGE_SZ
48 cmp r0, r1
49 blo 1b
50 mov ip, #0
51 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
52 dsb
53 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +010054ENDPROC(v7wbi_flush_user_tlb_range)
Catalin Marinas2ccdd1e2007-05-18 11:25:31 +010055
56/*
57 * v7wbi_flush_kern_tlb_range(start,end)
58 *
59 * Invalidate a range of kernel TLB entries
60 *
61 * - start - start address (may not be aligned)
62 * - end - end address (exclusive, may not be aligned)
63 */
64ENTRY(v7wbi_flush_kern_tlb_range)
65 dsb
66 mov r0, r0, lsr #PAGE_SHIFT @ align address
67 mov r1, r1, lsr #PAGE_SHIFT
68 mov r0, r0, lsl #PAGE_SHIFT
69 mov r1, r1, lsl #PAGE_SHIFT
701:
71 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
72 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
73 add r0, r0, #PAGE_SZ
74 cmp r0, r1
75 blo 1b
76 mov r2, #0
77 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
78 dsb
79 isb
80 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +010081ENDPROC(v7wbi_flush_kern_tlb_range)
Catalin Marinas2ccdd1e2007-05-18 11:25:31 +010082
83 .section ".text.init", #alloc, #execinstr
84
85 .type v7wbi_tlb_fns, #object
86ENTRY(v7wbi_tlb_fns)
87 .long v7wbi_flush_user_tlb_range
88 .long v7wbi_flush_kern_tlb_range
89 .long v6wbi_tlb_flags
90 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns