Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #include <linux/types.h> |
| 2 | #include <linux/errno.h> |
| 3 | #include <asm/uaccess.h> |
| 4 | |
Kumar Gala | d2b194e | 2008-06-04 02:59:29 -0500 | [diff] [blame] | 5 | #include <asm/sfp-machine.h> |
| 6 | #include <math-emu/soft-fp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | |
| 8 | int |
| 9 | mtfsf(unsigned int FM, u32 *frB) |
| 10 | { |
| 11 | u32 mask; |
Kumar Gala | d2b194e | 2008-06-04 02:59:29 -0500 | [diff] [blame] | 12 | u32 fpscr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 14 | if (likely(FM == 1)) |
| 15 | mask = 0x0f; |
| 16 | else if (likely(FM == 0xff)) |
| 17 | mask = ~0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | else { |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 19 | mask = ((FM & 1) | |
| 20 | ((FM << 3) & 0x10) | |
| 21 | ((FM << 6) & 0x100) | |
| 22 | ((FM << 9) & 0x1000) | |
| 23 | ((FM << 12) & 0x10000) | |
| 24 | ((FM << 15) & 0x100000) | |
| 25 | ((FM << 18) & 0x1000000) | |
| 26 | ((FM << 21) & 0x10000000)) * 15; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | } |
| 28 | |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 29 | fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) & |
| 30 | ~(FPSCR_VX | FPSCR_FEX | 0x800); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 32 | if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI | |
Kumar Gala | d2b194e | 2008-06-04 02:59:29 -0500 | [diff] [blame] | 33 | FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC | |
| 34 | FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI)) |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 35 | fpscr |= FPSCR_VX; |
Kumar Gala | d2b194e | 2008-06-04 02:59:29 -0500 | [diff] [blame] | 36 | |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 37 | /* The bit order of exception enables and exception status |
| 38 | * is the same. Simply shift and mask to check for enabled |
| 39 | * exceptions. |
| 40 | */ |
| 41 | if (fpscr & (fpscr >> 22) & 0xf8) |
Kumar Gala | d2b194e | 2008-06-04 02:59:29 -0500 | [diff] [blame] | 42 | fpscr |= FPSCR_FEX; |
Stephen Chivers | c59c015 | 2014-02-21 12:29:48 +1100 | [diff] [blame] | 43 | |
Kumar Gala | d2b194e | 2008-06-04 02:59:29 -0500 | [diff] [blame] | 44 | __FPU_FPSCR = fpscr; |
| 45 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #ifdef DEBUG |
Harvey Harrison | e48b1b4 | 2008-03-29 08:21:07 +1100 | [diff] [blame] | 47 | printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | #endif |
| 49 | |
| 50 | return 0; |
| 51 | } |