| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can distribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License (Version 2) as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 12 | * for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 17 | * |
| 18 | * Defines of the MIPS boards specific address-MAP, registers, etc. |
| 19 | */ |
| 20 | #ifndef __ASM_MIPS_BOARDS_GENERIC_H |
| 21 | #define __ASM_MIPS_BOARDS_GENERIC_H |
| 22 | |
| 23 | #include <linux/config.h> |
| 24 | #include <asm/addrspace.h> |
| 25 | #include <asm/byteorder.h> |
| 26 | #include <asm/mips-boards/bonito64.h> |
| 27 | |
| 28 | /* |
| 29 | * Display register base. |
| 30 | */ |
| 31 | #ifdef CONFIG_MIPS_SEAD |
| 32 | #define ASCII_DISPLAY_POS_BASE 0x1f0005c0 |
| 33 | #else |
| 34 | #define ASCII_DISPLAY_WORD_BASE 0x1f000410 |
| 35 | #define ASCII_DISPLAY_POS_BASE 0x1f000418 |
| 36 | #endif |
| 37 | |
| 38 | |
| 39 | /* |
| 40 | * Yamon Prom print address. |
| 41 | */ |
| 42 | #define YAMON_PROM_PRINT_ADDR 0x1fc00504 |
| 43 | |
| 44 | |
| 45 | /* |
| 46 | * Reset register. |
| 47 | */ |
| 48 | #ifdef CONFIG_MIPS_SEAD |
| 49 | #define SOFTRES_REG 0x1e800050 |
| 50 | #define GORESET 0x4d |
| 51 | #else |
| 52 | #define SOFTRES_REG 0x1f000500 |
| 53 | #define GORESET 0x42 |
| 54 | #endif |
| 55 | |
| 56 | /* |
| 57 | * Revision register. |
| 58 | */ |
| 59 | #define MIPS_REVISION_REG 0x1fc00010 |
| 60 | #define MIPS_REVISION_CORID_QED_RM5261 0 |
| 61 | #define MIPS_REVISION_CORID_CORE_LV 1 |
| 62 | #define MIPS_REVISION_CORID_BONITO64 2 |
| 63 | #define MIPS_REVISION_CORID_CORE_20K 3 |
| 64 | #define MIPS_REVISION_CORID_CORE_FPGA 4 |
| 65 | #define MIPS_REVISION_CORID_CORE_MSC 5 |
| 66 | #define MIPS_REVISION_CORID_CORE_EMUL 6 |
| 67 | #define MIPS_REVISION_CORID_CORE_FPGA2 7 |
| 68 | #define MIPS_REVISION_CORID_CORE_FPGAR2 8 |
| 69 | |
| 70 | /**** Artificial corid defines ****/ |
| 71 | /* |
| 72 | * CoreEMUL with Bonito System Controller is treated like a Core20K |
| 73 | * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC |
| 74 | */ |
| 75 | #define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 |
| 76 | #define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 |
| 77 | |
| 78 | #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) |
| 79 | |
| 80 | extern unsigned int mips_revision_corid; |
| 81 | |
| 82 | #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ |