blob: 7993b3d8720325480cc95fc2b06b77140265fc03 [file] [log] [blame]
John W. Linville0aec00a2007-06-12 22:11:42 -04001/*
2 * Definitions for RTL8187 hardware
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Michael Wu605bebe2007-05-14 01:41:02 -040015#ifndef RTL8187_H
16#define RTL8187_H
17
18#include "rtl818x.h"
19
20#define RTL8187_EEPROM_TXPWR_BASE 0x05
21#define RTL8187_EEPROM_MAC_ADDR 0x07
22#define RTL8187_EEPROM_TXPWR_CHAN_1 0x16 /* 3 channels */
23#define RTL8187_EEPROM_TXPWR_CHAN_6 0x1B /* 2 channels */
24#define RTL8187_EEPROM_TXPWR_CHAN_4 0x3D /* 2 channels */
25
26#define RTL8187_REQT_READ 0xC0
27#define RTL8187_REQT_WRITE 0x40
28#define RTL8187_REQ_GET_REG 0x05
29#define RTL8187_REQ_SET_REG 0x05
30
31#define RTL8187_MAX_RX 0x9C4
32
33struct rtl8187_rx_info {
34 struct urb *urb;
35 struct ieee80211_hw *dev;
36};
37
38struct rtl8187_rx_hdr {
39 __le16 len;
40 __le16 rate;
41 u8 noise;
42 u8 signal;
43 u8 agc;
44 u8 reserved;
45 __le64 mac_time;
46} __attribute__((packed));
47
48struct rtl8187_tx_info {
49 struct ieee80211_tx_control *control;
50 struct urb *urb;
51 struct ieee80211_hw *dev;
52};
53
54struct rtl8187_tx_hdr {
55 __le32 flags;
56#define RTL8187_TX_FLAG_NO_ENCRYPT (1 << 15)
57#define RTL8187_TX_FLAG_MORE_FRAG (1 << 17)
58#define RTL8187_TX_FLAG_CTS (1 << 18)
59#define RTL8187_TX_FLAG_RTS (1 << 23)
60 __le16 rts_duration;
61 __le16 len;
62 __le32 retry;
63} __attribute__((packed));
64
65struct rtl8187_priv {
66 /* common between rtl818x drivers */
67 struct rtl818x_csr *map;
68 void (*rf_init)(struct ieee80211_hw *);
69 int mode;
Daniel Drake7e9ed182007-07-27 15:43:24 +020070 int if_id;
Michael Wu605bebe2007-05-14 01:41:02 -040071
72 /* rtl8187 specific */
73 struct ieee80211_channel channels[14];
74 struct ieee80211_rate rates[12];
75 struct ieee80211_hw_mode modes[2];
76 struct usb_device *udev;
77 u8 *hwaddr;
78 u16 txpwr_base;
79 u8 asic_rev;
80 struct sk_buff_head rx_queue;
81};
82
83void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);
84
85static inline u8 rtl818x_ioread8(struct rtl8187_priv *priv, u8 *addr)
86{
87 u8 val;
88
89 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
90 RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
91 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2);
92
93 return val;
94}
95
96static inline u16 rtl818x_ioread16(struct rtl8187_priv *priv, __le16 *addr)
97{
98 __le16 val;
99
100 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
101 RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
102 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2);
103
104 return le16_to_cpu(val);
105}
106
107static inline u32 rtl818x_ioread32(struct rtl8187_priv *priv, __le32 *addr)
108{
109 __le32 val;
110
111 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
112 RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
113 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2);
114
115 return le32_to_cpu(val);
116}
117
118static inline void rtl818x_iowrite8(struct rtl8187_priv *priv,
119 u8 *addr, u8 val)
120{
121 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
122 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
123 (unsigned long)addr, 0, &val, sizeof(val), HZ / 2);
124}
125
126static inline void rtl818x_iowrite16(struct rtl8187_priv *priv,
127 __le16 *addr, u16 val)
128{
129 __le16 buf = cpu_to_le16(val);
130
131 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
132 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
133 (unsigned long)addr, 0, &buf, sizeof(buf), HZ / 2);
134}
135
136static inline void rtl818x_iowrite32(struct rtl8187_priv *priv,
137 __le32 *addr, u32 val)
138{
139 __le32 buf = cpu_to_le32(val);
140
141 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
142 RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
143 (unsigned long)addr, 0, &buf, sizeof(buf), HZ / 2);
144}
145
146#endif /* RTL8187_H */